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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=58.32.228.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Mon, 15 Jul 2024 13:12:20 +0800 From: zelong dong To: Neil Armstrong , Philipp Zabel , Kevin Hilman , Rob Herring , Martin Blumenstingl , Jerome Brunet , Krzysztof Kozlowski CC: , , , , , Zelong Dong Subject: [PATCH v2 1/3] dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller Date: Mon, 15 Jul 2024 13:12:15 +0800 Message-ID: <20240715051217.5286-2-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240715051217.5286-1-zelong.dong@amlogic.com> References: <20240715051217.5286-1-zelong.dong@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zelong Dong Add new compatible for Amlogic A4/A5 Reset Controller Signed-off-by: Zelong Dong Acked-by: Conor Dooley --- .../bindings/reset/amlogic,meson-reset.yaml | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.ya= ml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index f0c6c0df0ce3..11bfe484a5d3 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -12,13 +12,20 @@ maintainers: =20 properties: compatible: - enum: - - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible= SoCs - - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible= SoCs - - amlogic,meson-axg-reset # Reset Controller on AXG and compatible S= oCs - - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs - - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs + oneOf: + - items: + - enum: + - amlogic,meson8b-reset # Reset Controller on Meson8b and co= mpatible SoCs + - amlogic,meson-gxbb-reset # Reset Controller on GXBB and co= mpatible SoCs + - amlogic,meson-axg-reset # Reset Controller on AXG and comp= atible SoCs + - amlogic,meson-a1-reset # Reset Controller on A1 and compat= ible SoCs + - amlogic,meson-s4-reset # Reset Controller on S4 and compat= ible SoCs + - amlogic,c3-reset # Reset Controller on C3 and compatible S= oCs + - items: + - enum: + - amlogic,a4-reset + - amlogic,a5-reset + - const: amlogic,meson-s4-reset =20 reg: maxItems: 1 --=20 2.35.1 From nobody Wed Dec 17 12:04:49 2025 Received: from mail-sh.amlogic.com (unknown [58.32.228.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E401836CF; 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dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Mon, 15 Jul 2024 13:12:22 +0800 From: zelong dong To: Neil Armstrong , Philipp Zabel , Kevin Hilman , Rob Herring , Martin Blumenstingl , Jerome Brunet , Krzysztof Kozlowski CC: , , , , , Zelong Dong Subject: [PATCH v2 2/3] arm64: dts: amlogic: Add Amlogic A4 reset controller Date: Mon, 15 Jul 2024 13:12:16 +0800 Message-ID: <20240715051217.5286-3-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240715051217.5286-1-zelong.dong@amlogic.com> References: <20240715051217.5286-1-zelong.dong@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zelong Dong Add the device node and related header file for Amlogic A4 reset controller. The count and offset for A4 Soc RESET registers are same as S4 Soc. Signed-off-by: Zelong Dong --- .../arm64/boot/dts/amlogic/amlogic-a4-reset.h | 93 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 10 ++ 2 files changed, 103 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h b/arch/arm64/bo= ot/dts/amlogic/amlogic-a4-reset.h new file mode 100644 index 000000000000..f6a4c90bab3c --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DTS_AMLOGIC_A4_RESET_H +#define __DTS_AMLOGIC_A4_RESET_H + +/* RESET0 */ +/* 0-3 */ +#define RESET_USB 4 +/* 5-6*/ +#define RESET_U2PHY22 7 +#define RESET_USBPHY20 8 +#define RESET_U2PHY21 9 +#define RESET_USB2DRD 10 +#define RESET_U2H 11 +#define RESET_LED_CTRL 12 +/* 13-31 */ + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_AUDIO_VAD 33 +/* 34*/ +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +#define RESET_VOUT_VENC 37 +#define RESET_VOUT 38 +/* 39-47 */ +#define RESET_ETHERNET 48 +/* 49-63 */ + +/* RESET2 */ +#define RESET_DEVICE_MMC_ARB 64 +#define RESET_IRCTRL 65 +/* 66*/ +#define RESET_TS_PLL 67 +/* 68-72*/ +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +/* 75-79*/ +#define RESET_MSR_CLK 80 +/* 81*/ +#define RESET_SAR_ADC 82 +/* 83-87*/ +#define RESET_ACODEC 88 +/* 89-90*/ +#define RESET_WATCHDOG 91 +/* 92-95*/ + +/* RESET3 */ +/* 96-127 */ + +/* RESET4 */ +/* 128-131 */ +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +#define RESET_PWM_GH 135 +/* 136-137*/ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +/* 140*/ +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143-144*/ +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +/* 149-151*/ +#define RESET_SDEMMC_A 152 +/* 153*/ +#define RESET_SDEMMC_C 154 +/* 155-159*/ + +/* RESET5 */ +/* 160-175*/ +#define RESET_BRG_AO_NIC_SYS 176 +/* 177*/ +#define RESET_BRG_AO_NIC_MAIN 178 +#define RESET_BRG_AO_NIC_AUDIO 179 +/* 180-183*/ +#define RESET_BRG_AO_NIC_ALL 184 +/* 185*/ +#define RESET_BRG_NIC_SDIO 186 +#define RESET_BRG_NIC_EMMC 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_CLK81 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a4.dtsi index de10e7aebf21..3fd1c52fb55b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -4,6 +4,7 @@ */ =20 #include "amlogic-a4-common.dtsi" +#include "amlogic-a4-reset.h" #include / { cpus { @@ -48,3 +49,12 @@ pwrc: power-controller { }; }; }; + +&apb { + reset: reset-controller@2000 { + compatible =3D "amlogic,a4-reset", + "amlogic,meson-s4-reset"; + reg =3D <0x0 0x2000 0x0 0x98>; + #reset-cells =3D <1>; + }; +}; --=20 2.35.1 From nobody Wed Dec 17 12:04:49 2025 Received: from mail-sh.amlogic.com (unknown [58.32.228.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FA571836F7; Mon, 15 Jul 2024 05:27:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=58.32.228.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721021263; cv=none; b=E7CIvVOUsSlihqjUMb55s+oYUzjORaArCfV+dZD+rGXQ+A7Z3/kS2mRujKkit4pRMu/vVFQ3LyDcr3TTpDAz9/I9xk+aWjX1/o16kkB7jJukfOUsoyfcNcciFcSPbxq45+9FXq88nUrbBoJwUh98fgIxkiMy/COJyRbxsDWmx6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721021263; c=relaxed/simple; bh=CgdgrjImSEMreUF0Fb3iM3gecQOjj46AxAKBEmAKajE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AxTUFlo8xh8HPfO3Q+UOdqGi6i5AvAUCqwksNaYwEq8gs9WUlh7RJQsvoEFCy5YHl02qPEKIt6Ba7MrllQGV3jln/EA3jNVsLC99IL9wvGV+fc7cHNUMpL+ZUPV1zYmh+jOL7yjUni6HZygOy9EZSnNv4a/gpzmOy6sRWk4Ouzc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=58.32.228.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Mon, 15 Jul 2024 13:12:23 +0800 From: zelong dong To: Neil Armstrong , Philipp Zabel , Kevin Hilman , Rob Herring , Martin Blumenstingl , Jerome Brunet , Krzysztof Kozlowski CC: , , , , , Zelong Dong Subject: [PATCH v2 3/3] arm64: dts: amlogic: Add Amlogic A5 reset controller Date: Mon, 15 Jul 2024 13:12:17 +0800 Message-ID: <20240715051217.5286-4-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240715051217.5286-1-zelong.dong@amlogic.com> References: <20240715051217.5286-1-zelong.dong@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zelong Dong Add the device node and related header file for Amlogic A5 reset controller. The count and offset for A5 Soc RESET registers are same as S4 Soc. Signed-off-by: Zelong Dong --- .../arm64/boot/dts/amlogic/amlogic-a5-reset.h | 95 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 10 ++ 2 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h b/arch/arm64/bo= ot/dts/amlogic/amlogic-a5-reset.h new file mode 100644 index 000000000000..cdf0f5159620 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DTS_AMLOGIC_A5_RESET_H +#define __DTS_AMLOGIC_A5_RESET_H + +/* RESET0 */ +/* 0-3 */ +#define RESET_USB 4 +/* 5-7 */ +#define RESET_USBPHY20 8 +/* 9 */ +#define RESET_USB2DRD 10 +/* 11-31 */ + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_AUDIO_VAD 33 +/* 34 */ +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +/* 37-40 */ +#define RESET_DSPA_DEBUG 41 +/* 42 */ +#define RESET_DSPA 43 +/* 44-46 */ +#define RESET_NNA 47 +#define RESET_ETHERNET 48 +/* 49-63 */ + +/* RESET2 */ +#define RESET_ABUS_ARB 64 +#define RESET_IRCTRL 65 +/* 66 */ +#define RESET_TS_PLL 67 +/* 68-72 */ +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +#define RESET_RSA 75 + +/* 76-79 */ +#define RESET_MSR_CLK 80 +#define RESET_SPIFC 81 +#define RESET_SAR_ADC 82 +/* 83-90 */ +#define RESET_WATCHDOG 91 +/* 92-95 */ + +/* RESET3 */ +/* 96-127 */ + +/* RESET4 */ +#define RESET_RTC 128 +/* 129-131 */ +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +#define RESET_PWM_GH 135 +/* 104-105 */ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +/* 143*/ +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +/* 149-151 */ +#define RESET_SDEMMC_A 152 +/* 153 */ +#define RESET_SDEMMC_C 154 +/* 155-159*/ + +/* RESET5 */ +/* 160-175 */ +#define RESET_BRG_AO_NIC_SYS 176 +#define RESET_BRG_AO_NIC_DSPA 177 +#define RESET_BRG_AO_NIC_MAIN 178 +#define RESET_BRG_AO_NIC_AUDIO 179 +/* 180-183 */ +#define RESET_BRG_AO_NIC_ALL 184 +#define RESET_BRG_NIC_NNA 185 +#define RESET_BRG_NIC_SDIO 186 +#define RESET_BRG_NIC_EMMC 187 +#define RESET_BRG_NIC_DSU 188 +#define RESET_BRG_NIC_SYSCLK 189 +#define RESET_BRG_NIC_MAIN 190 +#define RESET_BRG_NIC_ALL 191 + +#endif diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-a5.dtsi index 43f68a7da2f7..aa035c5c63af 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi @@ -4,6 +4,7 @@ */ =20 #include "amlogic-a4-common.dtsi" +#include "amlogic-a5-reset.h" / { cpus { #address-cells =3D <2>; @@ -38,3 +39,12 @@ cpu3: cpu@300 { }; }; }; + +&apb { + reset: reset-controller@2000 { + compatible =3D "amlogic,a5-reset", + "amlogic,meson-s4-reset"; + reg =3D <0x0 0x2000 0x0 0x98>; + #reset-cells =3D <1>; + }; +}; --=20 2.35.1