From nobody Thu Dec 18 15:28:10 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DAFB186286 for ; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=VndUrXMKq4jAEjHBHn76tu6Fz9mrFvy5KUCLLAsEw2L7dLCw0TeK0JXCc1vH6KCsZ/lFAsoTi04kThosxSQ/qfUsXZY2C9fUPVUWwFBIDRBulaKnP5TOe2iM+owK8mv9YIek3xPlUd2ZLvT8fZCouUEgJYzcgnebSJT/z/8lJqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=9BeMjQzY2D1n5KMEIdhe/MnEyijbRClm3qeQuf/mLsg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=afF3i2rl3phLlTYKRw+V4vNnFYChdK3/VVDl5eQycf68pqRuceLko/+nOO5jnLYmEn24XH+L08Dksmy+s5SBtMk1PG7FDtfW23Nso7vrL8Af14xpgyHwzryFZQyPfjdEK0YQvIROza0wtis5BC8rojxtj0vUsMKD/OJS8YtKMoI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kLFkJl2Y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kLFkJl2Y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0439AC4AF12; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032804; bh=9BeMjQzY2D1n5KMEIdhe/MnEyijbRClm3qeQuf/mLsg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kLFkJl2YoJkPlQdbVr0dJohxtyAGv3v8LdxTg/XjRq7dMmNoSLqWMJ6Arv8bPMb6F l0N0YTQOhC315jUkpTLkFPCyqZwvRQooOSiAZ6ue/EQRVAO//v4mea7eD0+Hc7eng9 +qqYAjhXBsow4e/6/cWDRuHsffDuNJ3DiC22jdJ6suNN0A5VHI4fQlHyaE2iVQim8o I1XhtRzXtn11OJJRLi2BiBXFVwYbrx40U5lA5z0/HsDncJ865Nc7NjM0EKgUl6E/dM MKktdZh98vM2O1KMgInCwAh0JSl2B++7OUXUZcHJwV+s3QZduRNX/iaZZeDbgwdtVr YbIb/n3y5CvXA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED4C6C3DA50; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:23 +0300 Subject: [PATCH v11 19/38] mtd: rawnand: add support for ts72xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-19-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chris Packham , Nikita Shubin Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=8042; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=jHDUJ6eL0sN9Xsu30iSDeAiNw2Ly7ktT7Xc33sA1DRU=; b=dTLYNyLYgnpY/GJf4y6fg+xDSliCxlsGUjB3yJq019vOpzZBmxVeVEMsNZwFmzSK1ttO/vjtj+Zp e8CX4xNlAyj+MXWTpt9WOvgUw5zkYqWmAF7WhDAQfuvNTVl1RX8u X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Technologic Systems has it's own nand controller implementation in CPLD. Signed-off-by: Nikita Shubin Acked-by: Miquel Raynal --- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/technologic-nand-controller.c | 222 +++++++++++++++++= ++++ 3 files changed, 229 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index cbf8ae85e1ae..5a51b835f6b6 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -449,6 +449,12 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. =20 +config MTD_NAND_TS72XX + tristate "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + help + Enables support for NAND controller on ts72xx SBCs. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..d0b0e6b83568 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_MLC_LPC32XX) +=3D lpc32xx_mlc.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) +=3D sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) +=3D mxc_nand.o obj-$(CONFIG_MTD_NAND_SOCRATES) +=3D socrates_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) +=3D technologic-nand-controller.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) +=3D txx9ndfmc.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) +=3D mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) +=3D vf610_nfc.o diff --git a/drivers/mtd/nand/raw/technologic-nand-controller.c b/drivers/m= td/nand/raw/technologic-nand-controller.c new file mode 100644 index 000000000000..0e45a6fd91dd --- /dev/null +++ b/drivers/mtd/nand/raw/technologic-nand-controller.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technologic Systems TS72xx NAND controller driver + * + * Copyright (C) 2023 Nikita Shubin + * + * Derived from: plat_nand.c + * Author: Vitaly Wool + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE BIT(22) /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE BIT(23) /* 0xN0800000 */ + +#define TS72XX_NAND_ALE BIT(0) +#define TS72XX_NAND_CLE BIT(1) +#define TS72XX_NAND_NCE BIT(2) + +#define TS72XX_NAND_CTRL_CLE (TS72XX_NAND_NCE | TS72XX_NAND_CLE) +#define TS72XX_NAND_CTRL_ALE (TS72XX_NAND_NCE | TS72XX_NAND_ALE) + +struct ts72xx_nand_data { + struct nand_controller controller; + struct nand_chip chip; + void __iomem *base; + void __iomem *ctrl; + void __iomem *busy; +}; + +static inline struct ts72xx_nand_data *chip_to_ts72xx(struct nand_chip *ch= ip) +{ + return container_of(chip, struct ts72xx_nand_data, chip); +} + +static int ts72xx_nand_attach_chip(struct nand_chip *chip) +{ + switch (chip->ecc.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: + return -EINVAL; + case NAND_ECC_ENGINE_TYPE_SOFT: + if (chip->ecc.algo =3D=3D NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + fallthrough; + default: + return 0; + } +} + +static void ts72xx_nand_ctrl(struct nand_chip *chip, u8 value) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned char bits =3D ioread8(data->ctrl) & ~GENMASK(2, 0); + + iowrite8(bits | value, data->ctrl); +} + +static int ts72xx_nand_exec_instr(struct nand_chip *chip, + const struct nand_op_instr *instr) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned int timeout_us; + u32 status; + int ret; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_CLE); + iowrite8(instr->ctx.cmd.opcode, data->base); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_ADDR_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_ALE); + iowrite8_rep(data->base, instr->ctx.addr.addrs, instr->ctx.addr.naddrs); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_DATA_IN_INSTR: + ioread8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_DATA_OUT_INSTR: + iowrite8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_WAITRDY_INSTR: + timeout_us =3D instr->ctx.waitrdy.timeout_ms * 1000; + ret =3D readb_poll_timeout(data->busy, status, status & BIT(5), 0, timeo= ut_us); + if (ret) + return ret; + + break; + } + + if (instr->delay_ns) + ndelay(instr->delay_ns); + + return 0; +} + +static int ts72xx_nand_exec_op(struct nand_chip *chip, + const struct nand_operation *op, bool check_only) +{ + unsigned int i; + int ret; + + if (check_only) + return 0; + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D ts72xx_nand_exec_instr(chip, &op->instrs[i]); + if (ret) + return ret; + } + + return 0; +} + +static const struct nand_controller_ops ts72xx_nand_ops =3D { + .attach_chip =3D ts72xx_nand_attach_chip, + .exec_op =3D ts72xx_nand_exec_op, +}; + +static int ts72xx_nand_probe(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data; + struct fwnode_handle *child; + struct mtd_info *mtd; + int err; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + nand_controller_init(&data->controller); + data->controller.ops =3D &ts72xx_nand_ops; + data->chip.controller =3D &data->controller; + + data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + data->ctrl =3D data->base + TS72XX_NAND_CONTROL_ADDR_LINE; + data->busy =3D data->base + TS72XX_NAND_BUSY_ADDR_LINE; + + child =3D fwnode_get_next_child_node(dev_fwnode(&pdev->dev), NULL); + if (!child) + return dev_err_probe(&pdev->dev, -ENXIO, + "ts72xx controller node should have exactly one child\n"); + + nand_set_flash_node(&data->chip, to_of_node(child)); + mtd =3D nand_to_mtd(&data->chip); + mtd->dev.parent =3D &pdev->dev; + platform_set_drvdata(pdev, data); + + /* + * This driver assumes that the default ECC engine should be TYPE_SOFT. + * Set ->engine_type before registering the NAND devices in order to + * provide a driver specific default value. + */ + data->chip.ecc.engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; + + /* Scan to find existence of the device */ + err =3D nand_scan(&data->chip, 1); + if (err) + goto err_handle_put; + + err =3D mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); + if (err) + goto err_clean_nand; + + return 0; + +err_clean_nand: + nand_cleanup(&data->chip); +err_handle_put: + fwnode_handle_put(child); + return err; +} + +static void ts72xx_nand_remove(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data =3D platform_get_drvdata(pdev); + struct fwnode_handle *fwnode =3D dev_fwnode(&pdev->dev); + struct nand_chip *chip =3D &data->chip; + int ret; + + ret =3D mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); + fwnode_handle_put(fwnode); +} + +static const struct of_device_id ts72xx_id_table[] =3D { + { .compatible =3D "technologic,ts7200-nand" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_id_table); + +static struct platform_driver ts72xx_nand_driver =3D { + .driver =3D { + .name =3D "ts72xx-nand", + .of_match_table =3D ts72xx_id_table, + }, + .probe =3D ts72xx_nand_probe, + .remove_new =3D ts72xx_nand_remove, +}; +module_platform_driver(ts72xx_nand_driver); + +MODULE_AUTHOR("Nikita Shubin "); +MODULE_DESCRIPTION("Technologic Systems TS72xx NAND controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.2