From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1063513C9BD; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=XLLxU+K4sqoe9q24VMvKsc/EeHhwi99RD45AK3nIt5oJDa8axATUoJAFUbhPUXUky4vKUk+IImzs4nCelgKfhf/ARuKCUiyR7TcLcnVWCxoiu4bSyEB0FHoHjICetUuWyYJ59GsReu2en9kFsPwbtDsEm3WdvnZdD2W9cIZtyx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; c=relaxed/simple; bh=L9snBqYT6zbxHHzo7JUD/U/ceuDfn72AE374Ib9P4ic=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cctxX8o8Eci3E2LHDY22VtfmXUcULfQe08Jv17AfBIDJPSjGL4O9yvCrkHW00TjWvOUS/TvE9SaSBOy2dMjTA6R1Lqx5tB2uh83cIVVLghQ01qmSyRpX/0uO1Q3OLlESt+kdp5JOK7Xi3ajBly8Ai3dIOJS417EqManJtktaBi0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=todGlMgG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="todGlMgG" Received: by smtp.kernel.org (Postfix) with ESMTPS id A7CD7C4AF0A; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032802; bh=L9snBqYT6zbxHHzo7JUD/U/ceuDfn72AE374Ib9P4ic=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=todGlMgGdLTZBq0/0lhZG2vrUkLSMHQOWLrCPJWOiHkCUM2wToR7o7PtSFkYxVrVk RVvL/MhqU0bpwTBBrtxsxnTm4SoU2ZtLKTten1dogbnOt76ghS1E4Zicrai8Gxe3bd QMx0NIcKQIDwHKda51pC4SYaHerQ8kMALM8TMwv81dXpt5GyIOnsdPQh2KcovQzeO0 8g+WrXA5xjyQbGUEiiw34F8e4pQfTQcwwg8J8tx/7KYE4uzfWwaPKfaTbRv/jS/PtE RbiRmxD+Gsw5CHFxPYbxFDIgCUnZhL6qWL1r1UjqASe1aeGnc4/5XZS1MMTjq/7xJ9 6ouWJs81tFF5Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96DCDC3DA50; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:05 +0300 Subject: [PATCH v11 01/38] gpio: ep93xx: split device in multiple Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-1-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Russell King , Lukasz Majewski , Linus Walleij , Bartosz Golaszewski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=25436; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=H0zNf/mQwjdqPSa7ui7thngDyHREjpx9pAAsGwiVLr4=; b=371rXeMLCApNCnGiJiCoymwXfBY/4iPzJsK6d3Iv/ucRreyjvhEFoj4+7tbdKPPDuAOqsK2Tgtmo H6QJumngA9i22Wx0WwS9lTrNU1vncFwc2SMgrh+qaL/GDJ10uTZ7 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Prepare ep93xx SOC gpio to convert into device tree driver: - dropped banks and legacy defines - split AB IRQ and make it shared We are relying on IRQ number information A, B ports have single shared IRQ, while F port have dedicated IRQ for each line. Also we had to split single ep93xx platform_device into multiple, one for each port, without this we can't do a full working transition from legacy platform code into device tree capable. All GPIO_LOOKUP were change to match new chip namings. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski Reviewed-by: Andy Shevchenko --- arch/arm/mach-ep93xx/core.c | 121 ++++++++++++-- arch/arm/mach-ep93xx/edb93xx.c | 2 +- arch/arm/mach-ep93xx/ts72xx.c | 4 +- arch/arm/mach-ep93xx/vision_ep9307.c | 10 +- drivers/gpio/gpio-ep93xx.c | 311 +++++++++++++------------------= ---- 5 files changed, 228 insertions(+), 220 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 8b1ec60a9a46..03bce5e9d1f1 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 #include "hardware.h" #include @@ -139,9 +140,80 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision); /************************************************************************* * EP93xx GPIO *************************************************************************/ -static struct resource ep93xx_gpio_resource[] =3D { - DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), +/* port A */ +static struct resource ep93xx_a_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_a_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 0, + .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), + .resource =3D ep93xx_a_gpio_resources, +}; + +/* port B */ +static struct resource ep93xx_b_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_b_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 1, + .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), + .resource =3D ep93xx_b_gpio_resources, +}; + +/* port C */ +static struct resource ep93xx_c_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), +}; + +static struct platform_device ep93xx_c_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 2, + .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), + .resource =3D ep93xx_c_gpio_resources, +}; + +/* port D */ +static struct resource ep93xx_d_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_d_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 3, + .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), + .resource =3D ep93xx_d_gpio_resources, +}; + +/* port E */ +static struct resource ep93xx_e_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), +}; + +static struct platform_device ep93xx_e_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 4, + .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), + .resource =3D ep93xx_e_gpio_resources, +}; + +/* port F */ +static struct resource ep93xx_f_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), @@ -152,11 +224,34 @@ static struct resource ep93xx_gpio_resource[] =3D { DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; =20 -static struct platform_device ep93xx_gpio_device =3D { - .name =3D "gpio-ep93xx", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_gpio_resource), - .resource =3D ep93xx_gpio_resource, +static struct platform_device ep93xx_f_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 5, + .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), + .resource =3D ep93xx_f_gpio_resources, +}; + +/* port G */ +static struct resource ep93xx_g_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_g_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 6, + .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), + .resource =3D ep93xx_g_gpio_resources, +}; + +static struct platform_device *ep93xx_gpio_device[] __initdata =3D { + &ep93xx_a_gpio, + &ep93xx_b_gpio, + &ep93xx_c_gpio, + &ep93xx_d_gpio, + &ep93xx_e_gpio, + &ep93xx_f_gpio, + &ep93xx_g_gpio, }; =20 /************************************************************************* @@ -335,9 +430,9 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table= =3D { .dev_id =3D "i2c-gpio.0", .table =3D { /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("G", 1, NULL, 0, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("G", 0, NULL, 1, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), { } }, @@ -441,8 +536,8 @@ static struct gpiod_lookup_table ep93xx_leds_gpio_table= =3D { .dev_id =3D "leds-gpio", .table =3D { /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), { } }, }; @@ -975,6 +1070,7 @@ static struct device __init *ep93xx_init_soc(void) struct device __init *ep93xx_init_devices(void) { struct device *parent; + unsigned int i; =20 /* Disallow access to MaverickCrunch initially */ ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); @@ -989,7 +1085,8 @@ struct device __init *ep93xx_init_devices(void) parent =3D ep93xx_init_soc(); =20 /* Get the GPIO working early, other devices need it */ - platform_device_register(&ep93xx_gpio_device); + for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) + platform_device_register(ep93xx_gpio_device[i]); =20 amba_device_register(&uart1_device, &iomem_resource); amba_device_register(&uart2_device, &iomem_resource); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index dbdb822a0100..356b0460c7ed 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -105,7 +105,7 @@ static struct spi_board_info edb93xx_spi_board_info[] _= _initdata =3D { static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index d3de7283ecb3..0bbdf587c685 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -268,7 +268,7 @@ static struct spi_board_info bk3_spi_board_info[] __ini= tdata =3D { static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), { }, }, }; @@ -318,7 +318,7 @@ static struct gpiod_lookup_table ts72xx_spi_cs_gpio_tab= le =3D { .dev_id =3D "spi0", .table =3D { /* DIO_17 */ - GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c index 9471938df64c..b3087b8eed3f 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -206,9 +206,9 @@ static struct gpiod_lookup_table vision_spi_mmc_gpio_ta= ble =3D { .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ .table =3D { /* Card detect */ - GPIO_LOOKUP_IDX("B", 7, NULL, 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), /* Write protect */ - GPIO_LOOKUP_IDX("F", 0, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), { }, }, }; @@ -253,9 +253,9 @@ static struct gpiod_lookup_table vision_spi_cs4271_gpio= _table =3D { static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("G", 2, "cs", 2, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), { }, }, }; diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 6cedf46efec6..a55f635585f4 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -18,30 +18,10 @@ #include #include #include - -#define EP93XX_GPIO_F_INT_STATUS 0x5c -#define EP93XX_GPIO_A_INT_STATUS 0xa0 -#define EP93XX_GPIO_B_INT_STATUS 0xbc - -/* Maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX 63 - -/* Number of GPIO chips in EP93XX */ -#define EP93XX_GPIO_CHIP_NUM 8 - -/* Maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ 23 - -#define EP93XX_GPIO_A_IRQ_BASE 64 -#define EP93XX_GPIO_B_IRQ_BASE 72 -/* - * Static mapping of GPIO bank F IRQS: - * F0..F7 (16..24) to irq 80..87. - */ -#define EP93XX_GPIO_F_IRQ_BASE 80 +#include =20 struct ep93xx_gpio_irq_chip { - u8 irq_offset; + void __iomem *base; u8 int_unmasked; u8 int_enabled; u8 int_type1; @@ -50,15 +30,11 @@ struct ep93xx_gpio_irq_chip { }; =20 struct ep93xx_gpio_chip { + void __iomem *base; struct gpio_chip gc; struct ep93xx_gpio_irq_chip *eic; }; =20 -struct ep93xx_gpio { - void __iomem *base; - struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; -}; - #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) =20 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) @@ -79,25 +55,23 @@ static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_= chip(struct gpio_chip *gc #define EP93XX_INT_RAW_STATUS_OFFSET 0x14 #define EP93XX_INT_DEBOUNCE_OFFSET 0x18 =20 -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, - struct ep93xx_gpio_irq_chip *eic) +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic) { - writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET); =20 writeb_relaxed(eic->int_type2, - epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); + eic->base + EP93XX_INT_TYPE2_OFFSET); =20 writeb_relaxed(eic->int_type1, - epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); + eic->base + EP93XX_INT_TYPE1_OFFSET); =20 writeb_relaxed(eic->int_unmasked & eic->int_enabled, - epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + eic->base + EP93XX_INT_EN_OFFSET); } =20 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); int port_mask =3D BIT(offset); =20 @@ -106,53 +80,43 @@ static void ep93xx_gpio_int_debounce(struct gpio_chip = *gc, else eic->int_debounce &=3D ~port_mask; =20 - writeb(eic->int_debounce, - epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); + writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET); } =20 -static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) +static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc) { - struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); unsigned long stat; int offset; =20 - chained_irq_enter(irqchip, desc); - - /* - * Dispatch the IRQs to the irqdomain of each A and B - * gpiochip irqdomains depending on what has fired. - * The tricky part is that the IRQ line is shared - * between bank A and B and each has their own gpiochip. - */ - stat =3D readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + stat =3D readb(eic->base + EP93XX_INT_STATUS_OFFSET); for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[0].gc.irq.domain, - offset); + generic_handle_domain_irq(gc->irq.domain, offset); =20 - stat =3D readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[1].gc.irq.domain, - offset); + return stat; +} =20 - chained_irq_exit(irqchip, desc); +static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id) +{ + return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id)); } =20 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) { - /* - * map discontiguous hw irq range to continuous sw irq range: - * - * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} - */ struct irq_chip *irqchip =3D irq_desc_get_chip(desc); - unsigned int irq =3D irq_desc_get_irq(desc); - int port_f_idx =3D (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */ - int gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + port_f_idx; + struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); + struct gpio_irq_chip *gic =3D &gc->irq; + unsigned int parent =3D irq_desc_get_irq(desc); + unsigned int i; =20 chained_irq_enter(irqchip, desc); - generic_handle_irq(gpio_irq); + for (i =3D 0; i < gic->num_parents; i++) + if (gic->parents[i] =3D=3D parent) + break; + + if (i < gic->num_parents) + generic_handle_domain_irq(gc->irq.domain, i); + chained_irq_exit(irqchip, desc); } =20 @@ -160,31 +124,29 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { eic->int_type2 ^=3D port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); } =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) eic->int_type2 ^=3D port_mask; /* switch edge direction */ =20 eic->int_unmasked &=3D ~port_mask; - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -192,10 +154,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 - eic->int_unmasked &=3D ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked &=3D ~BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -203,11 +164,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); - eic->int_unmasked |=3D BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked |=3D BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); } =20 /* @@ -219,8 +179,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int offset =3D d->irq & 7; + irq_hw_number_t offset =3D irqd_to_hwirq(d); int port_mask =3D BIT(offset); irq_flow_handler_t handler; =20 @@ -264,51 +223,11 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) =20 eic->int_enabled |=3D port_mask; =20 - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 return 0; } =20 -/************************************************************************* - * gpiolib interface for EP93xx on-chip GPIOs - *************************************************************************/ -struct ep93xx_gpio_bank { - const char *label; - int data; - int dir; - int irq; - int base; - bool has_irq; - bool has_hierarchical_irq; - unsigned int irq_base; -}; - -#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_= hier, _irq_base) \ - { \ - .label =3D _label, \ - .data =3D _data, \ - .dir =3D _dir, \ - .irq =3D _irq, \ - .base =3D _base, \ - .has_irq =3D _has_irq, \ - .has_hierarchical_irq =3D _has_hier, \ - .irq_base =3D _irq_base, \ - } - -static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { - /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ= _BASE), - /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ= _BASE), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), - /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IR= Q_BASE), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), -}; - static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { @@ -342,110 +261,102 @@ static const struct irq_chip gpio_eic_irq_chip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 -static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, - struct platform_device *pdev, - struct ep93xx_gpio *epg, - struct ep93xx_gpio_bank *bank) +static int ep93xx_setup_irqs(struct platform_device *pdev, + struct ep93xx_gpio_chip *egc) { - void __iomem *data =3D epg->base + bank->data; - void __iomem *dir =3D epg->base + bank->dir; struct gpio_chip *gc =3D &egc->gc; struct device *dev =3D &pdev->dev; - struct gpio_irq_chip *girq; - int err; + struct gpio_irq_chip *girq =3D &gc->irq; + int ret, irq, i; + void __iomem *intr; =20 - err =3D bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); - if (err) - return err; + intr =3D devm_platform_ioremap_resource_byname(pdev, "intr"); + if (IS_ERR(intr)) + return PTR_ERR(intr); =20 - gc->label =3D bank->label; - gc->base =3D bank->base; + gc->set_config =3D ep93xx_gpio_set_config; + egc->eic =3D devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; =20 - girq =3D &gc->irq; - if (bank->has_irq || bank->has_hierarchical_irq) { - gc->set_config =3D ep93xx_gpio_set_config; - egc->eic =3D devm_kcalloc(dev, 1, - sizeof(*egc->eic), - GFP_KERNEL); - if (!egc->eic) - return -ENOMEM; - egc->eic->irq_offset =3D bank->irq; - gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); - } + egc->eic->base =3D intr; + gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); + girq->num_parents =3D platform_irq_count(pdev); + if (girq->num_parents =3D=3D 0) + return -EINVAL; =20 - if (bank->has_irq) { - int ab_parent_irq =3D platform_get_irq(pdev, 0); + girq->parents =3D devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; =20 - girq->parent_handler =3D ep93xx_gpio_ab_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->parents[0] =3D ab_parent_irq; - girq->first =3D bank->irq_base; - } + if (girq->num_parents =3D=3D 1) { /* A/B irqchips */ + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; =20 - /* Only bank F has especially funky IRQ handling */ - if (bank->has_hierarchical_irq) { - int gpio_irq; - int i; + ret =3D devm_request_irq(dev, irq, ep93xx_ab_irq_handler, + IRQF_SHARED, gc->label, gc); + if (ret) + return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq); =20 - /* - * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchical. - */ + girq->parents[0] =3D irq; + } else { /* F irqchip */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; - girq->num_parents =3D 8; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - /* Pick resources 1..8 for these IRQs */ + for (i =3D 0; i < girq->num_parents; i++) { - girq->parents[i] =3D platform_get_irq(pdev, i + 1); - gpio_irq =3D bank->irq_base + i; - irq_set_chip_data(gpio_irq, &epg->gc[5]); - irq_set_chip_and_handler(gpio_irq, - girq->chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + continue; + + girq->parents[i] =3D irq; } - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->first =3D bank->irq_base; + + girq->map =3D girq->parents; } =20 - return devm_gpiochip_add_data(dev, gc, epg); + girq->default_type =3D IRQ_TYPE_NONE; + /* TODO: replace with handle_bad_irq() once we are fully hierarchical */ + girq->handler =3D handle_simple_irq; + + return 0; } =20 static int ep93xx_gpio_probe(struct platform_device *pdev) { - struct ep93xx_gpio *epg; - int i; + struct ep93xx_gpio_chip *egc; + struct gpio_chip *gc; + void __iomem *data; + void __iomem *dir; + int ret; =20 - epg =3D devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL); - if (!epg) + egc =3D devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL); + if (!egc) return -ENOMEM; =20 - epg->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(epg->base)) - return PTR_ERR(epg->base); + data =3D devm_platform_ioremap_resource_byname(pdev, "data"); + if (IS_ERR(data)) + return PTR_ERR(data); =20 - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct ep93xx_gpio_chip *gc =3D &epg->gc[i]; - struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; + dir =3D devm_platform_ioremap_resource_byname(pdev, "dir"); + if (IS_ERR(dir)) + return PTR_ERR(dir); =20 - if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) - dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", - bank->label); + gc =3D &egc->gc; + ret =3D bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0); + if (ret) + return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n"); + + gc->label =3D dev_name(&pdev->dev); + if (platform_irq_count(pdev) > 0) { + dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev)); + ret =3D ep93xx_setup_irqs(pdev, egc); + if (ret) + dev_err_probe(&pdev->dev, ret, "setup irqs failed"); } =20 - return 0; + return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 static struct platform_driver ep93xx_gpio_driver =3D { --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D53B1849E4 for ; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=erXznI/6ZD1iTFioLBwJcs8exwruwujHi8qHj/R5X3Onqq8VOOEhCx27VIfxruIOG4j3+AV9qoDnvg/Cvr98cnWmbFQ7hC2G4XJPK+G7enfk9Qgnp0BXO/Av/7urnKFZ3FyeDE5CDjoo1BPvr3ztjWfNZuanZiBVnnPJMnyJb5U= ARC-Message-Signature: i=1; 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b=dRyhrhGBVnO37w4YPOPJIMnaRQheKTLzUPStb26czHJek9WQm30PgWEAdFxkrd+DR UgnZhdvM3TBUN1Q6aHZ7nMUqf4F16v1d6HtR6phVv1lv+i8RdbpZt4bUqAzIkwE83A Hg7m6IPzOIGOwaHWwWXVNp6o+2d6DnyX67bSOlVqEyuLxMZ2MwOkTc/5shDj9bZ3Kj 43WCvChBJpa1+/wAAnJ2A8sHAJC9Pa2f0MJ4v7AyzmQLTXWFiKEGD+uA4cfeeJvlze JbMHQ8miP3mxidXWBzgggN3TCgWrFpmsgXHNXU5hYXRvPYUC+z7NCl74NtXuNUU7n4 44StMkbmVkAig== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A71F3C3DA52; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:06 +0300 Subject: [PATCH v11 02/38] ARM: ep93xx: add regmap aux_dev Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-2-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Nikita Shubin , Linus Walleij , Sergey Shtylyov , Stephen Boyd , Thierry Reding Cc: Dmitry Torokhov , linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1982; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=qKYG1dvu9jbPQUSaZcYLmIk38kz0vsDfRewTf4KPvt0=; b=LfNFp94jxxV/2Z2wggHFMPynSfzV09a+9Pn/cRu4/72oXutIXD50q8Lp+hxrcY8BDfTObmmP4wsL I4fa8KJXBsK6AtW9eN/K/Ho1v0NOLsWVcupqFHIobRealB/O7V8r X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin The following driver's should be instantiated by ep93xx syscon driver: - reboot - pinctrl - clock They all require access to DEVCFG register with a shared lock held, to avoid conflict writing to swlocked parts of DEVCFG. Provide common resources such as base, regmap and spinlock via auxiliary bus framework. Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin Reviewed-by: Linus Walleij Reviewed-by: Stephen Boyd --- include/linux/soc/cirrus/ep93xx.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 56fbe2dc59b1..a27447971302 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -3,6 +3,18 @@ #define _SOC_EP93XX_H =20 struct platform_device; +struct regmap; +struct spinlock_t; + +enum ep93xx_soc_model { + EP93XX_9301_SOC, + EP93XX_9307_SOC, + EP93XX_9312_SOC, +}; + +#include +#include +#include =20 #define EP93XX_CHIP_REV_D0 3 #define EP93XX_CHIP_REV_D1 4 @@ -10,6 +22,20 @@ struct platform_device; #define EP93XX_CHIP_REV_E1 6 #define EP93XX_CHIP_REV_E2 7 =20 +struct ep93xx_regmap_adev { + struct auxiliary_device adev; + struct regmap *map; + void __iomem *base; + spinlock_t *lock; + void (*write)(struct regmap *map, spinlock_t *lock, unsigned int reg, + unsigned int val); + void (*update_bits)(struct regmap *map, spinlock_t *lock, + unsigned int reg, unsigned int mask, unsigned int val); +}; + +#define to_ep93xx_regmap_adev(_adev) \ + container_of((_adev), struct ep93xx_regmap_adev, adev) + #ifdef CONFIG_ARCH_EP93XX int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); void ep93xx_pwm_release_gpio(struct platform_device *pdev); --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B6991849D3; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=vDceZbYsEdFvokwaYuaJ5o+rbZ+ig9y+9fORuqfxDeRwXsqizOyMNnnpeX/Bu3el1HB1eP5Qkq5nuZ9hYmtySTsw2J9KPrAxzXDDMPOSUZ/f3+aqqb0tuEA5ltAM0H554bB2gIdQ5P250/ZsiVitL4qoxXyk1UCZNNhyAYki1/U= ARC-Message-Signature: i=1; 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b=ow6HpPX1bK+d08j0DZrrGBMxgtOsjfA1fDpUjSyZb0ZVpefXK+f4f0bdNpFqaHrlW LFCAp+C+pNBLOynjKern/1/8kINC5JPpnempOZHpzv0eGRlMdmSZJxR3eqKd3zZn6V Dixzdhzryc3QGK1e/Jv4TTloG42QntwXCzPVVMPY+4GAcUIho/vR7W/edp/UiO89dk IOgim6iSGLvS5yKLct1tDhmFPrDnyhpf6nz27DJcqhGQazKfAeINaz8BfvqXUGzDtU 0K3K9xc8vOLh3M86+ZwdleE/2fJ/iRLVJEarFstRsiYgrP6JFx+2MKAE0LnS9W6Fs8 LrBwdTwMQuT7w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9879C3DA4D; Mon, 15 Jul 2024 08:40:02 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:07 +0300 Subject: [PATCH v11 03/38] clk: ep93xx: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-3-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=27185; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=U7fOx9Rodv4jx5K1uhFoktxaVXXtL2LyQJrXaMQwDm0=; b=Bxjn73rQg4AwAXGGGDh2AbOeDHVTYe8koDOhLwKQtYcCANKSKS1FPRZrtnURIjkILVJ8aJ3SYq0E IhSYbDKWDVUBxz7GLvBfX6vgFPmCe07sJlKGWjBz8P0T9E9oOGg7 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - provide clock acces via of - drop clk_hw_register_clkdev - drop init code and use module_auxiliary_driver Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-ep93xx.c | 846 +++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 855 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3e9099504fad..234b0a8b7650 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523 This driver provides the fixed clocks and gates present on Airoha ARM silicon. =20 +config COMMON_CLK_EP93XX + bool "Clock driver for Cirrus Logic ep93xx SoC" + depends on ARCH_EP93XX || COMPILE_TEST + select MFD_SYSCON + select REGMAP + help + This driver supports the SoC clocks on the Cirrus Logic ep93xx. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4abe16c8ccdf..19d599d706fe 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) +=3D clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) +=3D clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) +=3D clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) +=3D clk-cs2000-cp.o +obj-$(CONFIG_COMMON_CLK_EP93XX) +=3D clk-ep93xx.o obj-$(CONFIG_ARCH_SPARX5) +=3D clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) +=3D clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) +=3D clk-fixed-mmio.o diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c new file mode 100644 index 000000000000..bb1cf59a3d47 --- /dev/null +++ b/drivers/clk/clk-ep93xx.c @@ -0,0 +1,846 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Clock control for Cirrus EP93xx chips. + * Copyright (C) 2021 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/clock.c: + * Copyright (C) 2006 Lennert Buytenhek + */ +#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define EP93XX_EXT_CLK_RATE 14745600 +#define EP93XX_EXT_RTC_RATE 32768 + +#define EP93XX_SYSCON_POWER_STATE 0x00 +#define EP93XX_SYSCON_PWRCNT 0x04 +#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29) +#define EP93XX_SYSCON_PWRCNT_USH_EN 28 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 +#define EP93XX_SYSCON_CLKSET1 0x20 +#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23) +#define EP93XX_SYSCON_CLKSET2 0x24 +#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19) +#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18) +#define EP93XX_SYSCON_DEVCFG 0x80 +#define EP93XX_SYSCON_DEVCFG_U3EN 24 +#define EP93XX_SYSCON_DEVCFG_U2EN 20 +#define EP93XX_SYSCON_DEVCFG_U1EN 18 +#define EP93XX_SYSCON_VIDCLKDIV 0x84 +#define EP93XX_SYSCON_CLKDIV_ENABLE 15 +#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14) +#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13) +#define EP93XX_SYSCON_CLKDIV_MASK GENMASK(14, 13) +#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 +#define EP93XX_SYSCON_I2SCLKDIV 0x8c +#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29) +#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19) +#define EP93XX_SYSCON_KEYTCHCLKDIV 0x90 +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0 +#define EP93XX_SYSCON_CHIPID 0x94 +#define EP93XX_SYSCON_CHIPID_ID 0x9213 + +static const char adc_divisors[] =3D { 16, 4 }; +static const char sclk_divisors[] =3D { 2, 4 }; +static const char lrclk_divisors[] =3D { 32, 64, 128 }; + +struct ep93xx_clk { + struct clk_hw hw; + u16 idx; + u16 reg; + u32 mask; + u8 bit_idx; + u8 shift; + u8 width; + u8 num_div; + const char *div; +}; + +struct ep93xx_clk_priv { + spinlock_t lock; + struct ep93xx_regmap_adev *aux_dev; + struct device *dev; + void __iomem *base; + struct regmap *map; + struct clk_hw *fixed[21]; + struct ep93xx_clk reg[]; +}; + +static struct ep93xx_clk *ep93xx_clk_from(struct clk_hw *hw) +{ + return container_of(hw, struct ep93xx_clk, hw); +} + +static struct ep93xx_clk_priv *ep93xx_priv_from(struct ep93xx_clk *clk) +{ + return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]); +} + +static void ep93xx_clk_write(struct ep93xx_clk_priv *priv, unsigned int re= g, unsigned int val) +{ + struct ep93xx_regmap_adev *aux =3D priv->aux_dev; + + aux->write(aux->map, aux->lock, reg, val); +} + +static int ep93xx_clk_is_enabled(struct clk_hw *hw) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + + regmap_read(priv->map, clk->reg, &val); + + return !!(val & BIT(clk->bit_idx)); +} + +static int ep93xx_clk_enable(struct clk_hw *hw) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + + guard(spinlock_irqsave)(&priv->lock); + + regmap_read(priv->map, clk->reg, &val); + val |=3D BIT(clk->bit_idx); + + ep93xx_clk_write(priv, clk->reg, val); + + return 0; +} + +static void ep93xx_clk_disable(struct clk_hw *hw) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + + guard(spinlock_irqsave)(&priv->lock); + + regmap_read(priv->map, clk->reg, &val); + val &=3D ~BIT(clk->bit_idx); + + ep93xx_clk_write(priv, clk->reg, val); +} + +static const struct clk_ops clk_ep93xx_gate_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, +}; + +static int ep93xx_clk_register_gate(struct ep93xx_clk *clk, + const char *name, + struct clk_parent_data *parent_data, + unsigned long flags, + unsigned int reg, + u8 bit_idx) +{ + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + struct clk_init_data init =3D { }; + + init.name =3D name; + init.ops =3D &clk_ep93xx_gate_ops; + init.flags =3D flags; + init.parent_data =3D parent_data; + init.num_parents =3D 1; + + clk->reg =3D reg; + clk->bit_idx =3D bit_idx; + clk->hw.init =3D &init; + + return devm_clk_hw_register(priv->dev, &clk->hw); +} + +static u8 ep93xx_mux_get_parent(struct clk_hw *hw) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + + regmap_read(priv->map, clk->reg, &val); + + val &=3D EP93XX_SYSCON_CLKDIV_MASK; + + switch (val) { + case EP93XX_SYSCON_CLKDIV_ESEL: + return 1; /* PLL1 */ + case EP93XX_SYSCON_CLKDIV_MASK: + return 2; /* PLL2 */ + default: + return 0; /* XTALI */ + }; +} + +static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + + if (index >=3D 3) + return -EINVAL; + + guard(spinlock_irqsave)(&priv->lock); + + regmap_read(priv->map, clk->reg, &val); + val &=3D ~(EP93XX_SYSCON_CLKDIV_MASK); + val |=3D index > 0 ? EP93XX_SYSCON_CLKDIV_ESEL : 0; + val |=3D index > 1 ? EP93XX_SYSCON_CLKDIV_PSEL : 0; + + ep93xx_clk_write(priv, clk->reg, val); + + return 0; +} + +static bool is_best(unsigned long rate, unsigned long now, + unsigned long best) +{ + return abs_diff(rate, now) < abs_diff(rate, best); +} + +static int ep93xx_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long best_rate =3D 0, actual_rate, mclk_rate; + unsigned long rate =3D req->rate; + struct clk_hw *parent_best =3D NULL; + unsigned long parent_rate_best; + unsigned long parent_rate; + int div, pdiv; + unsigned int i; + + /* + * Try the two pll's and the external clock, + * because the valid predividers are 2, 2.5 and 3, we multiply + * all the clocks by 2 to avoid floating point math. + * + * This is based on the algorithm in the ep93xx raster guide: + * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf + * + */ + for (i =3D 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); + + parent_rate =3D clk_hw_get_rate(parent); + mclk_rate =3D parent_rate * 2; + + /* Try each predivider value */ + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (!in_range(div, 1, 127)) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + if (is_best(rate, actual_rate, best_rate)) { + best_rate =3D actual_rate; + parent_rate_best =3D parent_rate; + parent_best =3D parent; + } + } + } + + if (!parent_best) + return -EINVAL; + + req->best_parent_rate =3D parent_rate_best; + req->best_parent_hw =3D parent_best; + req->rate =3D best_rate; + + return 0; +} + +static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + unsigned int pdiv, div; + u32 val; + + regmap_read(priv->map, clk->reg, &val); + pdiv =3D (val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & GENMASK(1, 0); + div =3D val & GENMASK(6, 0); + if (!div) + return 0; + + return DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div); +} + +static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + int pdiv, div, npdiv, ndiv; + unsigned long actual_rate, mclk_rate, rate_err =3D ULONG_MAX; + u32 val; + + regmap_read(priv->map, clk->reg, &val); + mclk_rate =3D parent_rate * 2; + + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (!in_range(div, 1, 127)) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + if (abs(actual_rate - rate) < rate_err) { + npdiv =3D pdiv - 3; + ndiv =3D div; + rate_err =3D abs(actual_rate - rate); + } + } + + if (rate_err =3D=3D ULONG_MAX) + return -EINVAL; + + /* + * Clear old dividers. + * Bit 7 is reserved bit in all ClkDiv registers. + */ + val &=3D ~(GENMASK(9, 0) & ~BIT(7)); + + /* Set the new pdiv and div bits for the new clock rate */ + val |=3D (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv; + + ep93xx_clk_write(priv, clk->reg, val); + + return 0; +} + +static const struct clk_ops clk_ddiv_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .get_parent =3D ep93xx_mux_get_parent, + .set_parent =3D ep93xx_mux_set_parent_lock, + .determine_rate =3D ep93xx_mux_determine_rate, + .recalc_rate =3D ep93xx_ddiv_recalc_rate, + .set_rate =3D ep93xx_ddiv_set_rate, +}; + +static int clk_hw_register_ddiv(struct ep93xx_clk *clk, + const char *name, + struct clk_parent_data *parent_data, + u8 num_parents, + unsigned int reg, + u8 bit_idx) +{ + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + struct clk_init_data init =3D { }; + + init.name =3D name; + init.ops =3D &clk_ddiv_ops; + init.flags =3D 0; + init.parent_data =3D parent_data; + init.num_parents =3D num_parents; + + clk->reg =3D reg; + clk->bit_idx =3D bit_idx; + clk->hw.init =3D &init; + + return devm_clk_hw_register(priv->dev, &clk->hw); +} + +static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + u32 val; + u8 index; + + regmap_read(priv->map, clk->reg, &val); + index =3D (val & clk->mask) >> clk->shift; + if (index > clk->num_div) + return 0; + + return DIV_ROUND_CLOSEST(parent_rate, clk->div[index]); +} + +static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + unsigned long best =3D 0, now; + unsigned int i; + + for (i =3D 0; i < clk->num_div; i++) { + if ((rate * clk->div[i]) =3D=3D *parent_rate) + return rate; + + now =3D DIV_ROUND_CLOSEST(*parent_rate, clk->div[i]); + if (!best || is_best(rate, now, best)) + best =3D now; + } + + return best; +} + +static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ep93xx_clk *clk =3D ep93xx_clk_from(hw); + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + unsigned int i; + u32 val; + + regmap_read(priv->map, clk->reg, &val); + val &=3D ~clk->mask; + for (i =3D 0; i < clk->num_div; i++) + if (rate =3D=3D DIV_ROUND_CLOSEST(parent_rate, clk->div[i])) + break; + + if (i =3D=3D clk->num_div) + return -EINVAL; + + val |=3D i << clk->shift; + + ep93xx_clk_write(priv, clk->reg, val); + + return 0; +} + +static const struct clk_ops ep93xx_div_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .recalc_rate =3D ep93xx_div_recalc_rate, + .round_rate =3D ep93xx_div_round_rate, + .set_rate =3D ep93xx_div_set_rate, +}; + +static int clk_hw_register_div(struct ep93xx_clk *clk, + const char *name, + struct clk_parent_data *parent_data, + unsigned int reg, + u8 enable_bit, + u8 shift, + u8 width, + const char *clk_divisors, + u8 num_div) +{ + struct ep93xx_clk_priv *priv =3D ep93xx_priv_from(clk); + struct clk_init_data init =3D { }; + + init.name =3D name; + init.ops =3D &ep93xx_div_ops; + init.flags =3D 0; + init.parent_data =3D parent_data; + init.num_parents =3D 1; + + clk->reg =3D reg; + clk->bit_idx =3D enable_bit; + clk->mask =3D GENMASK(shift + width - 1, shift); + clk->shift =3D shift; + clk->div =3D clk_divisors; + clk->num_div =3D num_div; + clk->hw.init =3D &init; + + return devm_clk_hw_register(priv->dev, &clk->hw); +} + +struct ep93xx_gate { + unsigned int idx; + unsigned int bit; + const char *name; +}; + +static const struct ep93xx_gate ep93xx_uarts[] =3D { + { EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" }, + { EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" }, + { EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" }, +}; + +static int ep93xx_uart_clock_init(struct ep93xx_clk_priv *priv) +{ + struct clk_parent_data parent_data =3D { }; + unsigned int i, idx, ret, clk_uart_div; + struct ep93xx_clk *clk; + u32 val; + + regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val); + if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD) + clk_uart_div =3D 1; + else + clk_uart_div =3D 2; + + priv->fixed[EP93XX_CLK_UART] =3D + clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div); + parent_data.hw =3D priv->fixed[EP93XX_CLK_UART]; + + /* parenting uart gate clocks to uart clock */ + for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { + idx =3D ep93xx_uarts[i].idx - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + ret =3D ep93xx_clk_register_gate(clk, + ep93xx_uarts[i].name, + &parent_data, CLK_SET_RATE_PARENT, + EP93XX_SYSCON_DEVCFG, + ep93xx_uarts[i].bit); + if (ret) + return dev_err_probe(priv->dev, ret, + "failed to register uart[%d] clock\n", i); + } + + return 0; +} + +static const struct ep93xx_gate ep93xx_dmas[] =3D { + { EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" }, + { EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" }, + { EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" }, + { EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" }, + { EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" }, + { EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" }, + { EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" }, + { EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" }, + { EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" }, + { EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" }, + { EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" }, + { EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" }, +}; + +static int ep93xx_dma_clock_init(struct ep93xx_clk_priv *priv) +{ + struct clk_parent_data parent_data =3D { }; + unsigned int i, idx; + + parent_data.hw =3D priv->fixed[EP93XX_CLK_HCLK]; + for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { + idx =3D ep93xx_dmas[i].idx; + priv->fixed[idx] =3D devm_clk_hw_register_gate_parent_data(priv->dev, + ep93xx_dmas[i].name, + &parent_data, 0, + priv->base + EP93XX_SYSCON_PWRCNT, + ep93xx_dmas[i].bit, + 0, + &priv->lock); + if (IS_ERR(priv->fixed[idx])) + return PTR_ERR(priv->fixed[idx]); + } + + return 0; +} + +static struct clk_hw *of_clk_ep93xx_get(struct of_phandle_args *clkspec, v= oid *data) +{ + struct ep93xx_clk_priv *priv =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx < EP93XX_CLK_UART1) + return priv->fixed[idx]; + + if (idx <=3D EP93XX_CLK_I2S_LRCLK) + return &priv->reg[idx - EP93XX_CLK_UART1].hw; + + return ERR_PTR(-EINVAL); +} + +/* + * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS + */ +static unsigned long calc_pll_rate(u64 rate, u32 config_word) +{ + rate *=3D ((config_word >> 11) & GENMASK(4, 0)) + 1; /* X1FBD */ + rate *=3D ((config_word >> 5) & GENMASK(5, 0)) + 1; /* X2FBD */ + do_div(rate, (config_word & GENMASK(4, 0)) + 1); /* X2IPD */ + rate >>=3D (config_word >> 16) & GENMASK(1, 0); /* PS */ + + return rate; +} + +#define devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, name, pare= nt_data, flags, fixed_rate) \ + __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \ + (parent_data), (flags), (fixed_rate), 0, 0, true) + +static int ep93xx_plls_init(struct ep93xx_clk_priv *priv) +{ + const char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; + const char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; + const char pclk_divisors[] =3D { 1, 2, 4, 8 }; + struct clk_parent_data xtali =3D { .index =3D 0 }; + unsigned int clk_f_div, clk_h_div, clk_p_div; + unsigned long clk_pll1_rate, clk_pll2_rate; + struct device *dev =3D priv->dev; + struct clk_hw *hw, *pll1; + u32 value; + + /* Determine the bootloader configured pll1 rate */ + regmap_read(priv->map, EP93XX_SYSCON_CLKSET1, &value); + + if (value & EP93XX_SYSCON_CLKSET1_NBYP1) + clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + else + clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; + + pll1 =3D devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, "pll1", = &xtali, + 0, clk_pll1_rate); + if (IS_ERR(pll1)) + return PTR_ERR(pll1); + + priv->fixed[EP93XX_CLK_PLL1] =3D pll1; + + /* Initialize the pll1 derived clocks */ + clk_f_div =3D fclk_divisors[(value >> 25) & GENMASK(2, 0)]; + clk_h_div =3D hclk_divisors[(value >> 20) & GENMASK(2, 0)]; + clk_p_div =3D pclk_divisors[(value >> 18) & GENMASK(1, 0)]; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, = 1, clk_f_div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_FCLK] =3D hw; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, = 1, clk_h_div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_HCLK] =3D hw; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, "pclk", hw, 0, 1,= clk_p_div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_PCLK] =3D hw; + + /* Determine the bootloader configured pll2 rate */ + regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value); + if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) + clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; + else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) + clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + else + clk_pll2_rate =3D 0; + + hw =3D devm_ep93xx_clk_hw_register_fixed_rate_parent_data(dev, "pll2", &x= tali, + 0, clk_pll2_rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_PLL2] =3D hw; + + return 0; +} + +static int ep93xx_clk_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct ep93xx_regmap_adev *rdev =3D to_ep93xx_regmap_adev(adev); + struct clk_parent_data xtali =3D { .index =3D 0 }; + struct clk_parent_data ddiv_pdata[3] =3D { }; + unsigned int clk_spi_div, clk_usb_div; + struct clk_parent_data pdata =3D {}; + struct device *dev =3D &adev->dev; + struct ep93xx_clk_priv *priv; + struct ep93xx_clk *clk; + struct clk_hw *hw; + unsigned int idx; + int ret; + u32 value; + + priv =3D devm_kzalloc(dev, struct_size(priv, reg, 10), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->lock); + priv->dev =3D dev; + priv->aux_dev =3D rdev; + priv->map =3D rdev->map; + priv->base =3D rdev->base; + + ret =3D ep93xx_plls_init(priv); + if (ret) + return ret; + + regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value); + clk_usb_div =3D (value >> 28 & GENMASK(3, 0)) + 1; + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, "usb_clk", + priv->fixed[EP93XX_CLK_PLL2], 0, 1, + clk_usb_div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_USB] =3D hw; + + ret =3D ep93xx_uart_clock_init(priv); + if (ret) + return ret; + + ret =3D ep93xx_dma_clock_init(priv); + if (ret) + return ret; + + clk_spi_div =3D id->driver_data; + hw =3D devm_clk_hw_register_fixed_factor_index(dev, "ep93xx-spi.0", + 0, /* XTALI external clock */ + 0, 1, clk_spi_div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_SPI] =3D hw; + + /* PWM clock */ + hw =3D devm_clk_hw_register_fixed_factor_index(dev, "pwm_clk", 0, /* XTAL= I external clock */ + 0, 1, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_PWM] =3D hw; + + /* USB clock */ + pdata.hw =3D priv->fixed[EP93XX_CLK_USB]; + hw =3D devm_clk_hw_register_gate_parent_data(priv->dev, "ohci-platform", = &pdata, + 0, priv->base + EP93XX_SYSCON_PWRCNT, + EP93XX_SYSCON_PWRCNT_USH_EN, 0, + &priv->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + priv->fixed[EP93XX_CLK_USB] =3D hw; + + ddiv_pdata[0].index =3D 0; /* XTALI external clock */ + ddiv_pdata[1].hw =3D priv->fixed[EP93XX_CLK_PLL1]; + ddiv_pdata[2].hw =3D priv->fixed[EP93XX_CLK_PLL2]; + + /* touchscreen/ADC clock */ + idx =3D EP93XX_CLK_ADC - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + ret =3D clk_hw_register_div(clk, "ep93xx-adc", &xtali, + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, + EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + + /* keypad clock */ + idx =3D EP93XX_CLK_KEYPAD - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + ret =3D clk_hw_register_div(clk, "ep93xx-keypad", &xtali, + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_KEN, + EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + /* + * On reset PDIV and VDIV is set to zero, while PDIV zero + * means clock disable, VDIV shouldn't be zero. + * So we set both video and i2s dividers to minimum. + * ENA - Enable CLK divider. + * PDIV - 00 - Disable clock + * VDIV - at least 2 + */ + + /* Check and enable video clk registers */ + regmap_read(priv->map, EP93XX_SYSCON_VIDCLKDIV, &value); + value |=3D BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + ep93xx_clk_write(priv, EP93XX_SYSCON_VIDCLKDIV, value); + + /* Check and enable i2s clk registers */ + regmap_read(priv->map, EP93XX_SYSCON_I2SCLKDIV, &value); + value |=3D BIT(EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + + /* + * Override the SAI_MSTR_CLK_CFG from the I2S block and use the + * I2SClkDiv Register settings. LRCLK transitions on the falling SCLK + * edge. + */ + value |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; + ep93xx_clk_write(priv, EP93XX_SYSCON_I2SCLKDIV, value); + + /* video clk */ + idx =3D EP93XX_CLK_VIDEO - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + ret =3D clk_hw_register_ddiv(clk, "ep93xx-fb", + ddiv_pdata, ARRAY_SIZE(ddiv_pdata), + EP93XX_SYSCON_VIDCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + /* i2s clk */ + idx =3D EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + ret =3D clk_hw_register_ddiv(clk, "mclk", + ddiv_pdata, ARRAY_SIZE(ddiv_pdata), + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + /* i2s sclk */ + idx =3D EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + pdata.hw =3D &priv->reg[EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1].hw; + ret =3D clk_hw_register_div(clk, "sclk", &pdata, + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + 16, /* EP93XX_I2SCLKDIV_SDIV_SHIFT */ + 1, /* EP93XX_I2SCLKDIV_SDIV_WIDTH */ + sclk_divisors, + ARRAY_SIZE(sclk_divisors)); + + /* i2s lrclk */ + idx =3D EP93XX_CLK_I2S_LRCLK - EP93XX_CLK_UART1; + clk =3D &priv->reg[idx]; + clk->idx =3D idx; + pdata.hw =3D &priv->reg[EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1].hw; + ret =3D clk_hw_register_div(clk, "lrclk", &pdata, + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + 17, /* EP93XX_I2SCLKDIV_LRDIV32_SHIFT */ + 2, /* EP93XX_I2SCLKDIV_LRDIV32_WIDTH */ + lrclk_divisors, + ARRAY_SIZE(lrclk_divisors)); + + /* IrDa clk uses same pattern but no init code presents in original clock= driver */ + return devm_of_clk_add_hw_provider(priv->dev, of_clk_ep93xx_get, priv); +} + +static const struct auxiliary_device_id ep93xx_clk_ids[] =3D { + { .name =3D "soc_ep93xx.clk-ep93xx", .driver_data =3D 2, }, + { .name =3D "soc_ep93xx.clk-ep93xx.e2", .driver_data =3D 1, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, ep93xx_clk_ids); + +static struct auxiliary_driver ep93xx_clk_driver =3D { + .probe =3D ep93xx_clk_probe, + .id_table =3D ep93xx_clk_ids, +}; +module_auxiliary_driver(ep93xx_clk_driver); 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Mon, 15 Jul 2024 08:40:02 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:08 +0300 Subject: [PATCH v11 04/38] pinctrl: add a Cirrus ep93xx SoC pin controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-4-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=52453; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=rWB2mOZn706oEuW9O17ThgnBdP0TfUVXWiECzPhRW5A=; b=LA/xtIvBuu1c28vNHgwG021ENwsLjhGlK0FLBlyluIIxgSRMdlgetyEyazDiixHRBGZQTgLAFEEp hT4UKdP7DQ+7gVMLkL5wEGfThcrbJ7RKSWUNOhumORz5IsAlQ7T+ X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add a pin control (only multiplexing) driver for ep93xx SoC so we can fully convert ep93xx to device tree. This driver is capable of muxing ep9301/ep9302/ep9307/ep9312/ep9315 variants, this is chosen based on "compatible" in device tree. Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-ep93xx.c | 1434 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1442 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7e4f93a3bc7a..85f1c74330ce 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -194,6 +194,13 @@ config PINCTRL_DIGICOLOR select PINMUX select GENERIC_PINCONF =20 +config PINCTRL_EP93XX + bool + depends on ARCH_EP93XX || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + config PINCTRL_EQUILIBRIUM tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain So= C" depends on OF && HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index cc809669405a..f28602d95424 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) +=3D pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) +=3D pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) +=3D pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) +=3D pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_EP93XX) +=3D pinctrl-ep93xx.o obj-$(CONFIG_PINCTRL_GEMINI) +=3D pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) +=3D pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) +=3D pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-ep93xx.c b/drivers/pinctrl/pinctrl-ep9= 3xx.c new file mode 100644 index 000000000000..458cb0e99c65 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ep93xx.c @@ -0,0 +1,1434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the EP93xx pin controller + * based on linux/drivers/pinctrl/pinmux-gemini.c + * + * Copyright (C) 2022 Nikita Shubin + * + * This is a group-only pin controller. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define DRIVER_NAME "pinctrl-ep93xx" + +enum ep93xx_pinctrl_model { + EP93XX_9301_PINCTRL, + EP93XX_9307_PINCTRL, + EP93XX_9312_PINCTRL, +}; + +struct ep93xx_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct ep93xx_regmap_adev *aux_dev; + struct regmap *map; + enum ep93xx_pinctrl_model model; +}; + +static void ep93xx_pinctrl_update_bits(struct ep93xx_pmx *pmx, unsigned in= t reg, + unsigned int mask, unsigned int val) +{ + struct ep93xx_regmap_adev *aux =3D pmx->aux_dev; + + aux->update_bits(aux->map, aux->lock, reg, mask, val); +} + +struct ep93xx_pin_group { + struct pingroup grp; + u32 mask; + u32 value; +}; + +#define PMX_GROUP(_name, _pins, _mask, _value) \ + { \ + .grp =3D PINCTRL_PINGROUP(_name, _pins, ARRAY_SIZE(_pins)), \ + .mask =3D _mask, \ + .value =3D _value, \ + } + +#define EP93XX_SYSCON_DEVCFG 0x80 + +/* + * There are several system configuration options selectable by the Device= Cfg and SysCfg + * registers. These registers provide the selection of several pin multipl= exing options and also + * provide software access to the system reset configuration options. Plea= se refer to the + * descriptions of the registers, =E2=80=9CDeviceCfg=E2=80=9D on page 5-25= and =E2=80=9CSysCfg=E2=80=9D on page 5-34, for a + * detailed explanation. + */ +#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30) +#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29) +#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28) +#define EP93XX_SYSCON_DEVCFG_GONK BIT(27) +#define EP93XX_SYSCON_DEVCFG_TONG BIT(26) +#define EP93XX_SYSCON_DEVCFG_MONG BIT(25) +#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22) +#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21) +#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11) +#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10) +#define EP93XX_SYSCON_DEVCFG_PONG BIT(9) +#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8) +#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7) +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6) +#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4) + +#define PADS_MASK (GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) |= BIT(4)) +#define PADS_MAXBIT 30 + +/* Ordered by bit index */ +static const char * const ep93xx_padgroups[] =3D { + NULL, NULL, NULL, NULL, + "RasOnP3", + NULL, + "I2SonAC97", + "I2SonSSP", + "EonIDE", + "PonG", + "GonIDE", + "HonIDE", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "A1onG", + "A2onG", + NULL, NULL, + "MonG", + "TonG", + "GonK", + "IonU2", + "D0onG", + "D1onG", +}; + +/* ep9301, ep9302 */ +static const struct pinctrl_pin_desc ep9301_pins[] =3D { + PINCTRL_PIN(1, "CSn[7]"), + PINCTRL_PIN(2, "CSn[6]"), + PINCTRL_PIN(3, "CSn[3]"), + PINCTRL_PIN(4, "CSn[2]"), + PINCTRL_PIN(5, "CSn[1]"), + PINCTRL_PIN(6, "AD[25]"), + PINCTRL_PIN(7, "vdd_ring"), + PINCTRL_PIN(8, "gnd_ring"), + PINCTRL_PIN(9, "AD[24]"), + PINCTRL_PIN(10, "SDCLK"), + PINCTRL_PIN(11, "AD[23]"), + PINCTRL_PIN(12, "vdd_core"), + PINCTRL_PIN(13, "gnd_core"), + PINCTRL_PIN(14, "SDWEn"), + PINCTRL_PIN(15, "SDCSn[3]"), + PINCTRL_PIN(16, "SDCSn[2]"), + PINCTRL_PIN(17, "SDCSn[1]"), + PINCTRL_PIN(18, "SDCSn[0]"), + PINCTRL_PIN(19, "vdd_ring"), + PINCTRL_PIN(20, "gnd_ring"), + PINCTRL_PIN(21, "RASn"), + PINCTRL_PIN(22, "CASn"), + PINCTRL_PIN(23, "DQMn[1]"), + PINCTRL_PIN(24, "DQMn[0]"), + PINCTRL_PIN(25, "AD[22]"), + PINCTRL_PIN(26, "AD[21]"), + PINCTRL_PIN(27, "vdd_ring"), + PINCTRL_PIN(28, "gnd_ring"), + PINCTRL_PIN(29, "DA[15]"), + PINCTRL_PIN(30, "AD[7]"), + PINCTRL_PIN(31, "DA[14]"), + PINCTRL_PIN(32, "AD[6]"), + PINCTRL_PIN(33, "DA[13]"), + PINCTRL_PIN(34, "vdd_core"), + PINCTRL_PIN(35, "gnd_core"), + PINCTRL_PIN(36, "AD[5]"), + PINCTRL_PIN(37, "DA[12]"), + PINCTRL_PIN(38, "AD[4]"), + PINCTRL_PIN(39, "DA[11]"), + PINCTRL_PIN(40, "AD[3]"), + PINCTRL_PIN(41, "vdd_ring"), + PINCTRL_PIN(42, "gnd_ring"), + PINCTRL_PIN(43, "DA[10]"), + PINCTRL_PIN(44, "AD[2]"), + PINCTRL_PIN(45, "DA[9]"), + PINCTRL_PIN(46, "AD[1]"), + PINCTRL_PIN(47, "DA[8]"), + PINCTRL_PIN(48, "AD[0]"), + PINCTRL_PIN(49, "vdd_ring"), + PINCTRL_PIN(50, "gnd_ring"), + PINCTRL_PIN(51, "NC"), + PINCTRL_PIN(52, "NC"), + PINCTRL_PIN(53, "vdd_ring"), + PINCTRL_PIN(54, "gnd_ring"), + PINCTRL_PIN(55, "AD[15]"), + PINCTRL_PIN(56, "DA[7]"), + PINCTRL_PIN(57, "vdd_core"), + PINCTRL_PIN(58, "gnd_core"), + PINCTRL_PIN(59, "AD[14]"), + PINCTRL_PIN(60, "DA[6]"), + PINCTRL_PIN(61, "AD[13]"), + PINCTRL_PIN(62, "DA[5]"), + PINCTRL_PIN(63, "AD[12]"), + PINCTRL_PIN(64, "DA[4]"), + PINCTRL_PIN(65, "AD[11]"), + PINCTRL_PIN(66, "vdd_ring"), + PINCTRL_PIN(67, "gnd_ring"), + PINCTRL_PIN(68, "DA[3]"), + PINCTRL_PIN(69, "AD[10]"), + PINCTRL_PIN(70, "DA[2]"), + PINCTRL_PIN(71, "AD[9]"), + PINCTRL_PIN(72, "DA[1]"), + PINCTRL_PIN(73, "AD[8]"), + PINCTRL_PIN(74, "DA[0]"), + PINCTRL_PIN(75, "DSRn"), + PINCTRL_PIN(76, "DTRn"), + PINCTRL_PIN(77, "TCK"), + PINCTRL_PIN(78, "TDI"), + PINCTRL_PIN(79, "TDO"), + PINCTRL_PIN(80, "TMS"), + PINCTRL_PIN(81, "vdd_ring"), + PINCTRL_PIN(82, "gnd_ring"), + PINCTRL_PIN(83, "BOOT[1]"), + PINCTRL_PIN(84, "BOOT[0]"), + PINCTRL_PIN(85, "gnd_ring"), + PINCTRL_PIN(86, "NC"), + PINCTRL_PIN(87, "EECLK"), + PINCTRL_PIN(88, "EEDAT"), + PINCTRL_PIN(89, "ASYNC"), + PINCTRL_PIN(90, "vdd_core"), + PINCTRL_PIN(91, "gnd_core"), + PINCTRL_PIN(92, "ASDO"), + PINCTRL_PIN(93, "SCLK1"), + PINCTRL_PIN(94, "SFRM1"), + PINCTRL_PIN(95, "SSPRX1"), + PINCTRL_PIN(96, "SSPTX1"), + PINCTRL_PIN(97, "GRLED"), + PINCTRL_PIN(98, "RDLED"), + PINCTRL_PIN(99, "vdd_ring"), + PINCTRL_PIN(100, "gnd_ring"), + PINCTRL_PIN(101, "INT[3]"), + PINCTRL_PIN(102, "INT[1]"), + PINCTRL_PIN(103, "INT[0]"), + PINCTRL_PIN(104, "RTSn"), + PINCTRL_PIN(105, "USBm[0]"), + PINCTRL_PIN(106, "USBp[0]"), + PINCTRL_PIN(107, "ABITCLK"), + PINCTRL_PIN(108, "CTSn"), + PINCTRL_PIN(109, "RXD[0]"), + PINCTRL_PIN(110, "RXD[1]"), + PINCTRL_PIN(111, "vdd_ring"), + PINCTRL_PIN(112, "gnd_ring"), + PINCTRL_PIN(113, "TXD[0]"), + PINCTRL_PIN(114, "TXD[1]"), + PINCTRL_PIN(115, "CGPIO[0]"), + PINCTRL_PIN(116, "gnd_core"), + PINCTRL_PIN(117, "PLL_GND"), + PINCTRL_PIN(118, "XTALI"), + PINCTRL_PIN(119, "XTALO"), + PINCTRL_PIN(120, "PLL_VDD"), + PINCTRL_PIN(121, "vdd_core"), + PINCTRL_PIN(122, "gnd_ring"), + PINCTRL_PIN(123, "vdd_ring"), + PINCTRL_PIN(124, "RSTOn"), + PINCTRL_PIN(125, "PRSTn"), + PINCTRL_PIN(126, "CSn[0]"), + PINCTRL_PIN(127, "gnd_core"), + PINCTRL_PIN(128, "vdd_core"), + PINCTRL_PIN(129, "gnd_ring"), + PINCTRL_PIN(130, "vdd_ring"), + PINCTRL_PIN(131, "ADC[4]"), + PINCTRL_PIN(132, "ADC[3]"), + PINCTRL_PIN(133, "ADC[2]"), + PINCTRL_PIN(134, "ADC[1]"), + PINCTRL_PIN(135, "ADC[0]"), + PINCTRL_PIN(136, "ADC_VDD"), + PINCTRL_PIN(137, "RTCXTALI"), + PINCTRL_PIN(138, "RTCXTALO"), + PINCTRL_PIN(139, "ADC_GND"), + PINCTRL_PIN(140, "EGPIO[11]"), + PINCTRL_PIN(141, "EGPIO[10]"), + PINCTRL_PIN(142, "EGPIO[9]"), + PINCTRL_PIN(143, "EGPIO[8]"), + PINCTRL_PIN(144, "EGPIO[7]"), + PINCTRL_PIN(145, "EGPIO[6]"), + PINCTRL_PIN(146, "EGPIO[5]"), + PINCTRL_PIN(147, "EGPIO[4]"), + PINCTRL_PIN(148, "EGPIO[3]"), + PINCTRL_PIN(149, "gnd_ring"), + PINCTRL_PIN(150, "vdd_ring"), + PINCTRL_PIN(151, "EGPIO[2]"), + PINCTRL_PIN(152, "EGPIO[1]"), + PINCTRL_PIN(153, "EGPIO[0]"), + PINCTRL_PIN(154, "ARSTn"), + PINCTRL_PIN(155, "TRSTn"), + PINCTRL_PIN(156, "ASDI"), + PINCTRL_PIN(157, "USBm[2]"), + PINCTRL_PIN(158, "USBp[2]"), + PINCTRL_PIN(159, "WAITn"), + PINCTRL_PIN(160, "EGPIO[15]"), + PINCTRL_PIN(161, "gnd_ring"), + PINCTRL_PIN(162, "vdd_ring"), + PINCTRL_PIN(163, "EGPIO[14]"), + PINCTRL_PIN(164, "EGPIO[13]"), + PINCTRL_PIN(165, "EGPIO[12]"), + PINCTRL_PIN(166, "gnd_core"), + PINCTRL_PIN(167, "vdd_core"), + PINCTRL_PIN(168, "FGPIO[3]"), + PINCTRL_PIN(169, "FGPIO[2]"), + PINCTRL_PIN(170, "FGPIO[1]"), + PINCTRL_PIN(171, "gnd_ring"), + PINCTRL_PIN(172, "vdd_ring"), + PINCTRL_PIN(173, "CLD"), + PINCTRL_PIN(174, "CRS"), + PINCTRL_PIN(175, "TXERR"), + PINCTRL_PIN(176, "TXEN"), + PINCTRL_PIN(177, "MIITXD[0]"), + PINCTRL_PIN(178, "MIITXD[1]"), + PINCTRL_PIN(179, "MIITXD[2]"), + PINCTRL_PIN(180, "MIITXD[3]"), + PINCTRL_PIN(181, "TXCLK"), + PINCTRL_PIN(182, "RXERR"), + PINCTRL_PIN(183, "RXDVAL"), + PINCTRL_PIN(184, "MIIRXD[0]"), + PINCTRL_PIN(185, "MIIRXD[1]"), + PINCTRL_PIN(186, "MIIRXD[2]"), + PINCTRL_PIN(187, "gnd_ring"), + PINCTRL_PIN(188, "vdd_ring"), + PINCTRL_PIN(189, "MIIRXD[3]"), + PINCTRL_PIN(190, "RXCLK"), + PINCTRL_PIN(191, "MDIO"), + PINCTRL_PIN(192, "MDC"), + PINCTRL_PIN(193, "RDn"), + PINCTRL_PIN(194, "WRn"), + PINCTRL_PIN(195, "AD[16]"), + PINCTRL_PIN(196, "AD[17]"), + PINCTRL_PIN(197, "gnd_core"), + PINCTRL_PIN(198, "vdd_core"), + PINCTRL_PIN(199, "HGPIO[2]"), + PINCTRL_PIN(200, "HGPIO[3]"), + PINCTRL_PIN(201, "HGPIO[4]"), + PINCTRL_PIN(202, "HGPIO[5]"), + PINCTRL_PIN(203, "gnd_ring"), + PINCTRL_PIN(204, "vdd_ring"), + PINCTRL_PIN(205, "AD[18]"), + PINCTRL_PIN(206, "AD[19]"), + PINCTRL_PIN(207, "AD[20]"), + PINCTRL_PIN(208, "SDCLKEN"), +}; + +static const unsigned int ssp_ep9301_pins[] =3D { + 93, 94, 95, 96, +}; + +static const unsigned int ac97_ep9301_pins[] =3D { + 89, 92, 107, 154, 156, +}; + +/* + * Note: The EP9307 processor has one PWM with one output, PWMOUT. + * Note: The EP9301, EP9302, EP9312, and EP9315 processors each have two P= WMs with + * two outputs, PWMOUT and PWMO1. PWMO1 is an alternate function for EGPIO= 14. + */ +/* The GPIO14E (14) pin overlap with pwm1 */ +static const unsigned int pwm_9301_pins[] =3D { 163 }; + +static const unsigned int gpio1a_9301_pins[] =3D { 163 }; + +/* ep9301/9302 have only 0 pin of GPIO C Port exposed */ +static const unsigned int gpio2a_9301_pins[] =3D { 115 }; + +/* ep9301/9302 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9301_pins[] =3D { 97, 98 }; + +/* ep9301/9302 have only 4,5 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9301_pins[] =3D { 87, 88 }; + +static const unsigned int gpio7a_9301_pins[] =3D { 199, 200, 201, 202 }; + +/* Groups for the ep9301/ep9302 SoC/package */ +static const struct ep93xx_pin_group ep9301_pin_groups[] =3D { + PMX_GROUP("ssp", ssp_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0), + PMX_GROUP("i2s_on_ssp", ssp_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, + EP93XX_SYSCON_DEVCFG_I2SONSSP), + PMX_GROUP("ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0), + PMX_GROUP("i2s_on_ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, + EP93XX_SYSCON_DEVCFG_I2SONAC97), + PMX_GROUP("pwm1", pwm_9301_pins, EP93XX_SYSCON_DEVCFG_PONG, EP93XX_SYSCON= _DEVCFG_PONG), + PMX_GROUP("gpio1agrp", gpio1a_9301_pins, EP93XX_SYSCON_DEVCFG_PONG, 0), + PMX_GROUP("gpio2agrp", gpio2a_9301_pins, EP93XX_SYSCON_DEVCFG_GONK, + EP93XX_SYSCON_DEVCFG_GONK), + PMX_GROUP("gpio4agrp", gpio4a_9301_pins, EP93XX_SYSCON_DEVCFG_EONIDE, + EP93XX_SYSCON_DEVCFG_EONIDE), + PMX_GROUP("gpio6agrp", gpio6a_9301_pins, EP93XX_SYSCON_DEVCFG_GONIDE, + EP93XX_SYSCON_DEVCFG_GONIDE), + PMX_GROUP("gpio7agrp", gpio7a_9301_pins, EP93XX_SYSCON_DEVCFG_HONIDE, + EP93XX_SYSCON_DEVCFG_HONIDE), +}; + +static const struct pinctrl_pin_desc ep9307_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSn[1]"), /* A1 */ + PINCTRL_PIN(1, "CSn[7]"), /* A2 */ + PINCTRL_PIN(2, "SDCLKEN"), /* A3 */ + PINCTRL_PIN(3, "DA[31]"), /* A4 */ + PINCTRL_PIN(4, "DA[29]"), /* A5 */ + PINCTRL_PIN(5, "DA[27]"), /* A6 */ + PINCTRL_PIN(6, "HGPIO[2]"), /* A7 */ + PINCTRL_PIN(7, "RDn"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[3]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[1]"), /* A11 */ + PINCTRL_PIN(11, "CRS"), /* A12 */ + PINCTRL_PIN(12, "FGPIO[7]"), /* A13 */ + PINCTRL_PIN(13, "FGPIO[0]"), /* A14 */ + PINCTRL_PIN(14, "WAITn"), /* A15 */ + PINCTRL_PIN(15, "USBm[2]"), /* A16 */ + PINCTRL_PIN(16, "ASDI"), /* A17 */ + /* Row B */ + PINCTRL_PIN(17, "AD[25]"), /* B1 */ + PINCTRL_PIN(18, "CSn[2]"), /* B2 */ + PINCTRL_PIN(19, "CSn[6]"), /* B3 */ + PINCTRL_PIN(20, "AD[20]"), /* B4 */ + PINCTRL_PIN(21, "DA[30]"), /* B5 */ + PINCTRL_PIN(22, "AD[18]"), /* B6 */ + PINCTRL_PIN(23, "HGPIO[3]"), /* B7 */ + PINCTRL_PIN(24, "AD[17]"), /* B8 */ + PINCTRL_PIN(25, "RXCLK"), /* B9 */ + PINCTRL_PIN(26, "MIIRXD[1]"), /* B10 */ + PINCTRL_PIN(27, "MIITXD[2]"), /* B11 */ + PINCTRL_PIN(28, "TXEN"), /* B12 */ + PINCTRL_PIN(29, "FGPIO[5]"), /* B13 */ + PINCTRL_PIN(30, "EGPIO[15]"), /* B14 */ + PINCTRL_PIN(31, "USBp[2]"), /* B15 */ + PINCTRL_PIN(32, "ARSTn"), /* B16 */ + PINCTRL_PIN(33, "ADC_VDD"), /* B17 */ + /* Row C */ + PINCTRL_PIN(34, "AD[23]"), /* C1 */ + PINCTRL_PIN(35, "DA[26]"), /* C2 */ + PINCTRL_PIN(36, "CSn[3]"), /* C3 */ + PINCTRL_PIN(37, "DA[25]"), /* C4 */ + PINCTRL_PIN(38, "AD[24]"), /* C5 */ + PINCTRL_PIN(39, "AD[19]"), /* C6 */ + PINCTRL_PIN(40, "HGPIO[5]"), /* C7 */ + PINCTRL_PIN(41, "WRn"), /* C8 */ + PINCTRL_PIN(42, "MDIO"), /* C9 */ + PINCTRL_PIN(43, "MIIRXD[2]"), /* C10 */ + PINCTRL_PIN(44, "TXCLK"), /* C11 */ + PINCTRL_PIN(45, "MIITXD[0]"), /* C12 */ + PINCTRL_PIN(46, "CLD"), /* C13 */ + PINCTRL_PIN(47, "EGPIO[13]"), /* C14 */ + PINCTRL_PIN(48, "TRSTn"), /* C15 */ + PINCTRL_PIN(49, "Xp"), /* C16 */ + PINCTRL_PIN(50, "Xm"), /* C17 */ + /* Row D */ + PINCTRL_PIN(51, "SDCSn[3]"), /* D1 */ + PINCTRL_PIN(52, "DA[23]"), /* D2 */ + PINCTRL_PIN(53, "SDCLK"), /* D3 */ + PINCTRL_PIN(54, "DA[24]"), /* D4 */ + PINCTRL_PIN(55, "HGPIO[7]"), /* D5 */ + PINCTRL_PIN(56, "HGPIO[6]"), /* D6 */ + PINCTRL_PIN(57, "A[28]"), /* D7 */ + PINCTRL_PIN(58, "HGPIO[4]"), /* D8 */ + PINCTRL_PIN(59, "AD[16]"), /* D9 */ + PINCTRL_PIN(60, "MDC"), /* D10 */ + PINCTRL_PIN(61, "RXERR"), /* D11 */ + PINCTRL_PIN(62, "MIITXD[3]"), /* D12 */ + PINCTRL_PIN(63, "EGPIO[12]"), /* D13 */ + PINCTRL_PIN(64, "EGPIO[1]"), /* D14 */ + PINCTRL_PIN(65, "EGPIO[0]"), /* D15 */ + PINCTRL_PIN(66, "Ym"), /* D16 */ + PINCTRL_PIN(67, "Yp"), /* D17 */ + /* Row E */ + PINCTRL_PIN(68, "SDCSn[2]"), /* E1 */ + PINCTRL_PIN(69, "SDWEN"), /* E2 */ + PINCTRL_PIN(70, "DA[22]"), /* E3 */ + PINCTRL_PIN(71, "AD[3]"), /* E4 */ + PINCTRL_PIN(72, "DA[15]"), /* E5 */ + PINCTRL_PIN(73, "AD[21]"), /* E6 */ + PINCTRL_PIN(74, "DA[17]"), /* E7 */ + PINCTRL_PIN(75, "vddr"), /* E8 */ + PINCTRL_PIN(76, "vddr"), /* E9 */ + PINCTRL_PIN(77, "vddr"), /* E10 */ + PINCTRL_PIN(78, "MIIRXD[0]"), /* E11 */ + PINCTRL_PIN(79, "TXERR"), /* E12 */ + PINCTRL_PIN(80, "EGPIO[2]"), /* E13 */ + PINCTRL_PIN(81, "EGPIO[4]"), /* E14 */ + PINCTRL_PIN(82, "EGPIO[3]"), /* E15 */ + PINCTRL_PIN(83, "sXp"), /* E16 */ + PINCTRL_PIN(84, "sXm"), /* E17 */ + /* Row F */ + PINCTRL_PIN(85, "RASn"), /* F1 */ + PINCTRL_PIN(86, "SDCSn[1]"), /* F2 */ + PINCTRL_PIN(87, "SDCSn[0]"), /* F3 */ + PINCTRL_PIN(88, "DQMn[3]"), /* F4 */ + PINCTRL_PIN(89, "AD[5]"), /* F5 */ + PINCTRL_PIN(90, "gndr"), /* F6 */ + PINCTRL_PIN(91, "gndr"), /* F7 */ + PINCTRL_PIN(92, "gndr"), /* F8 */ + PINCTRL_PIN(93, "vddc"), /* F9 */ + PINCTRL_PIN(94, "vddc"), /* F10 */ + PINCTRL_PIN(95, "gndr"), /* F11 */ + PINCTRL_PIN(96, "EGPIO[7]"), /* F12 */ + PINCTRL_PIN(97, "EGPIO[5]"), /* F13 */ + PINCTRL_PIN(98, "ADC GND"), /* F14 */ + PINCTRL_PIN(99, "EGPIO[6]"), /* F15 */ + PINCTRL_PIN(100, "sYm"), /* F16 */ + PINCTRL_PIN(101, "syp"), /* F17 */ + /* Row G */ + PINCTRL_PIN(102, "DQMn[0]"), /* G1 */ + PINCTRL_PIN(103, "CASn"), /* G2 */ + PINCTRL_PIN(104, "DA[21]"), /* G3 */ + PINCTRL_PIN(105, "AD[22]"), /* G4 */ + PINCTRL_PIN(106, "vddr"), /* G5 */ + PINCTRL_PIN(107, "gndr"), /* G6 */ + PINCTRL_PIN(108, "gndr"), /* G12 */ + PINCTRL_PIN(109, "EGPIO[9]"), /* G13 */ + PINCTRL_PIN(110, "EGPIO[10]"), /* G14 */ + PINCTRL_PIN(111, "EGPIO[11]"), /* G15 */ + PINCTRL_PIN(112, "RTCXTALO"), /* G16 */ + PINCTRL_PIN(113, "RTCXTALI"), /* G17 */ + /* Row H */ + PINCTRL_PIN(114, "DA[18]"), /* H1 */ + PINCTRL_PIN(115, "DA[20]"), /* H2 */ + PINCTRL_PIN(116, "DA[19]"), /* H3 */ + PINCTRL_PIN(117, "DA[16]"), /* H4 */ + PINCTRL_PIN(118, "vddr"), /* H5 */ + PINCTRL_PIN(119, "vddc"), /* H6 */ + PINCTRL_PIN(120, "gndc"), /* H7 */ + PINCTRL_PIN(121, "gndc"), /* H9 */ + PINCTRL_PIN(122, "gndc"), /* H10 */ + PINCTRL_PIN(123, "gndr"), /* H12 */ + PINCTRL_PIN(124, "vddr"), /* H13 */ + PINCTRL_PIN(125, "EGPIO[8]"), /* H14 */ + PINCTRL_PIN(126, "PRSTN"), /* H15 */ + PINCTRL_PIN(127, "COL[7]"), /* H16 */ + PINCTRL_PIN(128, "RSTON"), /* H17 */ + /* Row J */ + PINCTRL_PIN(129, "AD[6]"), /* J1 */ + PINCTRL_PIN(130, "DA[14]"), /* J2 */ + PINCTRL_PIN(131, "AD[7]"), /* J3 */ + PINCTRL_PIN(132, "DA[13]"), /* J4 */ + PINCTRL_PIN(133, "vddr"), /* J5 */ + PINCTRL_PIN(134, "vddc"), /* J6 */ + PINCTRL_PIN(135, "gndc"), /* J8 */ + PINCTRL_PIN(136, "gndc"), /* J10 */ + PINCTRL_PIN(137, "vddc"), /* J12 */ + PINCTRL_PIN(138, "vddr"), /* J13 */ + PINCTRL_PIN(139, "COL[5]"), /* J14 */ + PINCTRL_PIN(140, "COL[6]"), /* J15 */ + PINCTRL_PIN(141, "CSn[0]"), /* J16 */ + PINCTRL_PIN(142, "COL[3]"), /* J17 */ + /* Row K */ + PINCTRL_PIN(143, "AD[4]"), /* K1 */ + PINCTRL_PIN(144, "DA[12]"), /* K2 */ + PINCTRL_PIN(145, "DA[10]"), /* K3 */ + PINCTRL_PIN(146, "DA[11]"), /* K4 */ + PINCTRL_PIN(147, "vddr"), /* K5 */ + PINCTRL_PIN(148, "gndr"), /* K6 */ + PINCTRL_PIN(149, "gndc"), /* K8 */ + PINCTRL_PIN(150, "gndc"), /* K9 */ + PINCTRL_PIN(151, "gndc"), /* K10 */ + PINCTRL_PIN(152, "vddc"), /* K12 */ + PINCTRL_PIN(153, "COL[4]"), /* K13 */ + PINCTRL_PIN(154, "PLL_VDD"), /* K14 */ + PINCTRL_PIN(155, "COL[2]"), /* K15 */ + PINCTRL_PIN(156, "COL[1]"), /* K16 */ + PINCTRL_PIN(157, "COL[0]"), /* K17 */ + /* Row L */ + PINCTRL_PIN(158, "DA[9]"), /* L1 */ + PINCTRL_PIN(159, "AD[2]"), /* L2 */ + PINCTRL_PIN(160, "AD[1]"), /* L3 */ + PINCTRL_PIN(161, "DA[8]"), /* L4 */ + PINCTRL_PIN(162, "BLANK"), /* L5 */ + PINCTRL_PIN(163, "gndr"), /* L6 */ + PINCTRL_PIN(164, "gndr"), /* L7 */ + PINCTRL_PIN(165, "ROW[7]"), /* L8 */ + PINCTRL_PIN(166, "ROW[5]"), /* L9 */ + PINCTRL_PIN(167, "PLL GND"), /* L10 */ + PINCTRL_PIN(168, "XTALI"), /* L11 */ + PINCTRL_PIN(169, "XTALO"), /* L12 */ + /* Row M */ + PINCTRL_PIN(170, "BRIGHT"), /* M1 */ + PINCTRL_PIN(171, "AD[0]"), /* M2 */ + PINCTRL_PIN(172, "DQMn[1]"), /* M3 */ + PINCTRL_PIN(173, "DQMn[2]"), /* M4 */ + PINCTRL_PIN(174, "P[17]"), /* M5 */ + PINCTRL_PIN(175, "gndr"), /* M6 */ + PINCTRL_PIN(176, "gndr"), /* M7 */ + PINCTRL_PIN(177, "vddc"), /* M8 */ + PINCTRL_PIN(178, "vddc"), /* M9 */ + PINCTRL_PIN(179, "gndr"), /* M10 */ + PINCTRL_PIN(180, "gndr"), /* M11 */ + PINCTRL_PIN(181, "ROW[6]"), /* M12 */ + PINCTRL_PIN(182, "ROW[4]"), /* M13 */ + PINCTRL_PIN(183, "ROW[1]"), /* M14 */ + PINCTRL_PIN(184, "ROW[0]"), /* M15 */ + PINCTRL_PIN(185, "ROW[3]"), /* M16 */ + PINCTRL_PIN(186, "ROW[2]"), /* M17 */ + /* Row N */ + PINCTRL_PIN(187, "P[14]"), /* N1 */ + PINCTRL_PIN(188, "P[16]"), /* N2 */ + PINCTRL_PIN(189, "P[15]"), /* N3 */ + PINCTRL_PIN(190, "P[13]"), /* N4 */ + PINCTRL_PIN(191, "P[12]"), /* N5 */ + PINCTRL_PIN(192, "DA[5]"), /* N6 */ + PINCTRL_PIN(193, "vddr"), /* N7 */ + PINCTRL_PIN(194, "vddr"), /* N8 */ + PINCTRL_PIN(195, "vddr"), /* N9 */ + PINCTRL_PIN(196, "vddr"), /* N10 */ + PINCTRL_PIN(197, "EECLK"), /* N11 */ + PINCTRL_PIN(198, "ASDO"), /* N12 */ + PINCTRL_PIN(199, "CTSn"), /* N13 */ + PINCTRL_PIN(200, "RXD[0]"), /* N14 */ + PINCTRL_PIN(201, "TXD[0]"), /* N15 */ + PINCTRL_PIN(202, "TXD[1]"), /* N16 */ + PINCTRL_PIN(203, "TXD[2]"), /* N17 */ + /* Row P */ + PINCTRL_PIN(204, "SPCLK"), /* P1 */ + PINCTRL_PIN(205, "P[10]"), /* P2 */ + PINCTRL_PIN(206, "P[11]"), /* P3 */ + PINCTRL_PIN(207, "P[3]"), /* P4 */ + PINCTRL_PIN(208, "AD[15]"), /* P5 */ + PINCTRL_PIN(209, "AD[13]"), /* P6 */ + PINCTRL_PIN(210, "AD[12]"), /* P7 */ + PINCTRL_PIN(211, "DA[2]"), /* P8 */ + PINCTRL_PIN(212, "AD[8]"), /* P9 */ + PINCTRL_PIN(213, "TCK"), /* P10 */ + PINCTRL_PIN(214, "BOOT[1]"), /* P11 */ + PINCTRL_PIN(215, "EEDAT"), /* P12 */ + PINCTRL_PIN(216, "GRLED"), /* P13 */ + PINCTRL_PIN(217, "RDLED"), /* P14 */ + PINCTRL_PIN(218, "GGPIO[2]"), /* P15 */ + PINCTRL_PIN(219, "RXD[1]"), /* P16 */ + PINCTRL_PIN(220, "RXD[2]"), /* P17 */ + /* Row R */ + PINCTRL_PIN(221, "P[9]"), /* R1 */ + PINCTRL_PIN(222, "HSYNC"), /* R2 */ + PINCTRL_PIN(223, "P[6]"), /* R3 */ + PINCTRL_PIN(224, "P[5]"), /* R4 */ + PINCTRL_PIN(225, "P[0]"), /* R5 */ + PINCTRL_PIN(226, "AD[14]"), /* R6 */ + PINCTRL_PIN(227, "DA[4]"), /* R7 */ + PINCTRL_PIN(228, "DA[1]"), /* R8 */ + PINCTRL_PIN(229, "DTRn"), /* R9 */ + PINCTRL_PIN(230, "TDI"), /* R10 */ + PINCTRL_PIN(231, "BOOT[0]"), /* R11 */ + PINCTRL_PIN(232, "ASYNC"), /* R12 */ + PINCTRL_PIN(233, "SSPTX[1]"), /* R13 */ + PINCTRL_PIN(234, "PWMOUT"), /* R14 */ + PINCTRL_PIN(235, "USBm[0]"), /* R15 */ + PINCTRL_PIN(236, "ABITCLK"), /* R16 */ + PINCTRL_PIN(237, "USBp[0]"), /* R17 */ + /* Row T */ + PINCTRL_PIN(238, "NC"), /* T1 */ + PINCTRL_PIN(239, "NC"), /* T2 */ + PINCTRL_PIN(240, "V_CSYNC"), /* T3 */ + PINCTRL_PIN(241, "P[7]"), /* T4 */ + PINCTRL_PIN(242, "P[2]"), /* T5 */ + PINCTRL_PIN(243, "DA[7]"), /* T6 */ + PINCTRL_PIN(244, "AD[11]"), /* T7 */ + PINCTRL_PIN(245, "AD[9]"), /* T8 */ + PINCTRL_PIN(246, "DSRn"), /* T9 */ + PINCTRL_PIN(247, "TMS"), /* T10 */ + PINCTRL_PIN(248, "gndr"), /* T11 */ + PINCTRL_PIN(249, "SFRM[1]"), /* T12 */ + PINCTRL_PIN(250, "INT[2]"), /* T13 */ + PINCTRL_PIN(251, "INT[0]"), /* T14 */ + PINCTRL_PIN(252, "USBp[1]"), /* T15 */ + PINCTRL_PIN(253, "NC"), /* T16 */ + PINCTRL_PIN(254, "NC"), /* T17 */ + /* Row U */ + PINCTRL_PIN(255, "NC"), /* U1 */ + PINCTRL_PIN(256, "NC"), /* U2 */ + PINCTRL_PIN(257, "P[8]"), /* U3 */ + PINCTRL_PIN(258, "P[4]"), /* U4 */ + PINCTRL_PIN(259, "P[1]"), /* U5 */ + PINCTRL_PIN(260, "DA[6]"), /* U6 */ + PINCTRL_PIN(261, "DA[3]"), /* U7 */ + PINCTRL_PIN(262, "AD[10]"), /* U8 */ + PINCTRL_PIN(263, "DA[0]"), /* U9 */ + PINCTRL_PIN(264, "TDO"), /* U10 */ + PINCTRL_PIN(265, "NC"), /* U11 */ + PINCTRL_PIN(266, "SCLK[1]"), /* U12 */ + PINCTRL_PIN(267, "SSPRX[1]"), /* U13 */ + PINCTRL_PIN(268, "INT[1]"), /* U14 */ + PINCTRL_PIN(269, "RTSn"), /* U15 */ + PINCTRL_PIN(270, "USBm[1]"), /* U16 */ + PINCTRL_PIN(271, "NC"), /* U17 */ +}; + +static const unsigned int ssp_ep9307_pins[] =3D { + 233, 249, 266, 267, +}; + +static const unsigned int ac97_ep9307_pins[] =3D { + 16, 32, 198, 232, 236, +}; + +/* I can't find info on those - it's some internal state */ +static const unsigned int raster_on_sdram0_pins[] =3D { +}; + +static const unsigned int raster_on_sdram3_pins[] =3D { +}; + +/* ROW[N] */ +static const unsigned int gpio2a_9307_pins[] =3D { + 165, 166, 181, 182, 183, 184, 185, 186, +}; + +/* COL[N] */ +static const unsigned int gpio3a_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157, +}; + +static const unsigned int keypad_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157, + 165, 166, 181, 182, 183, 184, 185, 186, +}; + +/* ep9307 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9307_pins[] =3D { 216, 217 }; + +/* ep9307 have only 2 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9307_pins[] =3D { 219 }; + +static const unsigned int gpio7a_9307_pins[] =3D { 7, 24, 41, 56, 57, 59 }; + +static const struct ep93xx_pin_group ep9307_pin_groups[] =3D { + PMX_GROUP("ssp", ssp_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0), + PMX_GROUP("i2s_on_ssp", ssp_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, + EP93XX_SYSCON_DEVCFG_I2SONSSP), + PMX_GROUP("ac97", ac97_ep9307_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0), + PMX_GROUP("i2s_on_ac97", ac97_ep9301_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, + EP93XX_SYSCON_DEVCFG_I2SONAC97), + PMX_GROUP("rasteronsdram0grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCF= G_RASONP3, 0), + PMX_GROUP("rasteronsdram3grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCF= G_RASONP3, + EP93XX_SYSCON_DEVCFG_RASONP3), + PMX_GROUP("gpio2agrp", gpio2a_9307_pins, EP93XX_SYSCON_DEVCFG_GONK, + EP93XX_SYSCON_DEVCFG_GONK), + PMX_GROUP("gpio3agrp", gpio3a_9307_pins, EP93XX_SYSCON_DEVCFG_GONK, + EP93XX_SYSCON_DEVCFG_GONK), + PMX_GROUP("keypadgrp", keypad_9307_pins, EP93XX_SYSCON_DEVCFG_GONK, 0), + PMX_GROUP("gpio4agrp", gpio4a_9307_pins, EP93XX_SYSCON_DEVCFG_EONIDE, + EP93XX_SYSCON_DEVCFG_EONIDE), + PMX_GROUP("gpio6agrp", gpio6a_9307_pins, EP93XX_SYSCON_DEVCFG_GONIDE, + EP93XX_SYSCON_DEVCFG_GONIDE), + PMX_GROUP("gpio7agrp", gpio7a_9307_pins, EP93XX_SYSCON_DEVCFG_HONIDE, + EP93XX_SYSCON_DEVCFG_HONIDE), +}; + +/* ep9312, ep9315 */ +static const struct pinctrl_pin_desc ep9312_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSN[7]"), /* A1 */ + PINCTRL_PIN(1, "DA[28]"), /* A2 */ + PINCTRL_PIN(2, "AD[18]"), /* A3 */ + PINCTRL_PIN(3, "DD[8]"), /* A4 */ + PINCTRL_PIN(4, "DD[4]"), /* A5 */ + PINCTRL_PIN(5, "AD[17]"), /* A6 */ + PINCTRL_PIN(6, "RDN"), /* A7 */ + PINCTRL_PIN(7, "RXCLK"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[0]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[2]"), /* A11 */ + PINCTRL_PIN(11, "TXERR"), /* A12 */ + PINCTRL_PIN(12, "CLD"), /* A13 */ + PINCTRL_PIN(13, "NC"), /* A14 */ + PINCTRL_PIN(14, "NC"), /* A15 */ + PINCTRL_PIN(15, "NC"), /* A16 */ + PINCTRL_PIN(16, "EGPIO[12]"), /* A17 */ + PINCTRL_PIN(17, "EGPIO[15]"), /* A18 */ + PINCTRL_PIN(18, "NC"), /* A19 */ + PINCTRL_PIN(19, "NC"), /* A20 */ + /* Row B */ + PINCTRL_PIN(20, "CSN[2]"), /* B1 */ + PINCTRL_PIN(21, "DA[31]"), /* B2 */ + PINCTRL_PIN(22, "DA[30]"), /* B3 */ + PINCTRL_PIN(23, "DA[27]"), /* B4 */ + PINCTRL_PIN(24, "DD[7]"), /* B5 */ + PINCTRL_PIN(25, "DD[3]"), /* B6 */ + PINCTRL_PIN(26, "WRN"), /* B7 */ + PINCTRL_PIN(27, "MDIO"), /* B8 */ + PINCTRL_PIN(28, "MIIRXD[1]"), /* B9 */ + PINCTRL_PIN(29, "RXERR"), /* B10 */ + PINCTRL_PIN(30, "MIITXD[1]"), /* B11 */ + PINCTRL_PIN(31, "CRS"), /* B12 */ + PINCTRL_PIN(32, "NC"), /* B13 */ + PINCTRL_PIN(33, "NC"), /* B14 */ + PINCTRL_PIN(34, "NC"), /* B15 */ + PINCTRL_PIN(35, "NC"), /* B16 */ + PINCTRL_PIN(36, "EGPIO[13]"), /* B17 */ + PINCTRL_PIN(37, "NC"), /* B18 */ + PINCTRL_PIN(38, "WAITN"), /* B19 */ + PINCTRL_PIN(39, "TRSTN"), /* B20 */ + /* Row C */ + PINCTRL_PIN(40, "CSN[1]"), /* C1 */ + PINCTRL_PIN(41, "CSN[3]"), /* C2 */ + PINCTRL_PIN(42, "AD[20]"), /* C3 */ + PINCTRL_PIN(43, "DA[29]"), /* C4 */ + PINCTRL_PIN(44, "DD[10]"), /* C5 */ + PINCTRL_PIN(45, "DD[6]"), /* C6 */ + PINCTRL_PIN(46, "DD[2]"), /* C7 */ + PINCTRL_PIN(47, "MDC"), /* C8 */ + PINCTRL_PIN(48, "MIIRXD[3]"), /* C9 */ + PINCTRL_PIN(49, "TXCLK"), /* C10 */ + PINCTRL_PIN(50, "MIITXD[0]"), /* C11 */ + PINCTRL_PIN(51, "NC"), /* C12 */ + PINCTRL_PIN(52, "NC"), /* C13 */ + PINCTRL_PIN(53, "NC"), /* C14 */ + PINCTRL_PIN(54, "NC"), /* C15 */ + PINCTRL_PIN(55, "NC"), /* C16 */ + PINCTRL_PIN(56, "NC"), /* C17 */ + PINCTRL_PIN(57, "USBP[2]"), /* C18 */ + PINCTRL_PIN(58, "IORDY"), /* C19 */ + PINCTRL_PIN(59, "DMACKN"), /* C20 */ + /* Row D */ + PINCTRL_PIN(60, "AD[24]"), /* D1 */ + PINCTRL_PIN(61, "DA[25]"), /* D2 */ + PINCTRL_PIN(62, "DD[11]"), /* D3 */ + PINCTRL_PIN(63, "SDCLKEN"), /* D4 */ + PINCTRL_PIN(64, "AD[19]"), /* D5 */ + PINCTRL_PIN(65, "DD[9]"), /* D6 */ + PINCTRL_PIN(66, "DD[5]"), /* D7 */ + PINCTRL_PIN(67, "AD[16]"), /* D8 */ + PINCTRL_PIN(68, "MIIRXD[2]"), /* D9 */ + PINCTRL_PIN(69, "MIITXD[3]"), /* D10 */ + PINCTRL_PIN(70, "TXEN"), /* D11 */ + PINCTRL_PIN(71, "NC"), /* D12 */ + PINCTRL_PIN(72, "NC"), /* D13 */ + PINCTRL_PIN(73, "NC"), /* D14 */ + PINCTRL_PIN(74, "EGPIO[14]"), /* D15 */ + PINCTRL_PIN(75, "NC"), /* D16 */ + PINCTRL_PIN(76, "USBM[2]"), /* D17 */ + PINCTRL_PIN(77, "ARSTN"), /* D18 */ + PINCTRL_PIN(78, "DIORN"), /* D19 */ + PINCTRL_PIN(79, "EGPIO[1]"), /* D20 */ + /* Row E */ + PINCTRL_PIN(80, "AD[23]"), /* E1 */ + PINCTRL_PIN(81, "DA[23]"), /* E2 */ + PINCTRL_PIN(82, "DA[26]"), /* E3 */ + PINCTRL_PIN(83, "CSN[6]"), /* E4 */ + PINCTRL_PIN(84, "GND"), /* E5 */ + PINCTRL_PIN(85, "GND"), /* E6 */ + PINCTRL_PIN(86, "CVDD"), /* E7 */ + PINCTRL_PIN(87, "CVDD"), /* E8 */ + PINCTRL_PIN(88, "RVDD"), /* E9 */ + PINCTRL_PIN(89, "GND"), /* E10 */ + PINCTRL_PIN(90, "GND"), /* E11 */ + PINCTRL_PIN(91, "RVDD"), /* E12 */ + PINCTRL_PIN(92, "CVDD"), /* E13 */ + PINCTRL_PIN(93, "CVDD"), /* E14 */ + PINCTRL_PIN(94, "GND"), /* E15 */ + PINCTRL_PIN(95, "ASDI"), /* E16 */ + PINCTRL_PIN(96, "DIOWN"), /* E17 */ + PINCTRL_PIN(97, "EGPIO[0]"), /* E18 */ + PINCTRL_PIN(98, "EGPIO[3]"), /* E19 */ + PINCTRL_PIN(99, "EGPIO[5]"), /* E20 */ + /* Row F */ + PINCTRL_PIN(100, "SDCSN[3]"), /* F1 */ + PINCTRL_PIN(101, "DA[22]"), /* F2 */ + PINCTRL_PIN(102, "DA[24]"), /* F3 */ + PINCTRL_PIN(103, "AD[25]"), /* F4 */ + PINCTRL_PIN(104, "RVDD"), /* F5 */ + PINCTRL_PIN(105, "GND"), /* F6 */ + PINCTRL_PIN(106, "CVDD"), /* F7 */ + PINCTRL_PIN(107, "CVDD"), /* F14 */ + PINCTRL_PIN(108, "GND"), /* F15 */ + PINCTRL_PIN(109, "GND"), /* F16 */ + PINCTRL_PIN(110, "EGPIO[2]"), /* F17 */ + PINCTRL_PIN(111, "EGPIO[4]"), /* F18 */ + PINCTRL_PIN(112, "EGPIO[6]"), /* F19 */ + PINCTRL_PIN(113, "EGPIO[8]"), /* F20 */ + /* Row G */ + PINCTRL_PIN(114, "SDCSN[0]"), /* G1 */ + PINCTRL_PIN(115, "SDCSN[1]"), /* G2 */ + PINCTRL_PIN(116, "SDWEN"), /* G3 */ + PINCTRL_PIN(117, "SDCLK"), /* G4 */ + PINCTRL_PIN(118, "RVDD"), /* G5 */ + PINCTRL_PIN(119, "RVDD"), /* G6 */ + PINCTRL_PIN(120, "RVDD"), /* G15 */ + PINCTRL_PIN(121, "RVDD"), /* G16 */ + PINCTRL_PIN(122, "EGPIO[7]"), /* G17 */ + PINCTRL_PIN(123, "EGPIO[9]"), /* G18 */ + PINCTRL_PIN(124, "EGPIO[10]"), /* G19 */ + PINCTRL_PIN(125, "EGPIO[11]"), /* G20 */ + /* Row H */ + PINCTRL_PIN(126, "DQMN[3]"), /* H1 */ + PINCTRL_PIN(127, "CASN"), /* H2 */ + PINCTRL_PIN(128, "RASN"), /* H3 */ + PINCTRL_PIN(129, "SDCSN[2]"), /* H4 */ + PINCTRL_PIN(130, "CVDD"), /* H5 */ + PINCTRL_PIN(131, "GND"), /* H8 */ + PINCTRL_PIN(132, "GND"), /* H9 */ + PINCTRL_PIN(133, "GND"), /* H10 */ + PINCTRL_PIN(134, "GND"), /* H11 */ + PINCTRL_PIN(135, "GND"), /* H12 */ + PINCTRL_PIN(136, "GND"), /* H13 */ + PINCTRL_PIN(137, "RVDD"), /* H16 */ + PINCTRL_PIN(138, "RTCXTALO"), /* H17 */ + PINCTRL_PIN(139, "ADC_VDD"), /* H18 */ + PINCTRL_PIN(140, "ADC_GND"), /* H19 */ + PINCTRL_PIN(141, "XP"), /* H20 */ + /* Row J */ + PINCTRL_PIN(142, "DA[21]"), /* J1 */ + PINCTRL_PIN(143, "DQMN[0]"), /* J2 */ + PINCTRL_PIN(144, "DQMN[1]"), /* J3 */ + PINCTRL_PIN(145, "DQMN[2]"), /* J4 */ + PINCTRL_PIN(146, "GND"), /* J5 */ + PINCTRL_PIN(147, "GND"), /* J8 */ + PINCTRL_PIN(148, "GND"), /* J9 */ + PINCTRL_PIN(149, "GND"), /* J10 */ + PINCTRL_PIN(150, "GND"), /* J11 */ + PINCTRL_PIN(151, "GND"), /* J12 */ + PINCTRL_PIN(152, "GND"), /* J13 */ + PINCTRL_PIN(153, "CVDD"), /* J16 */ + PINCTRL_PIN(154, "RTCXTALI"), /* J17 */ + PINCTRL_PIN(155, "XM"), /* J18 */ + PINCTRL_PIN(156, "YP"), /* J19 */ + PINCTRL_PIN(157, "YM"), /* J20 */ + /* Row K */ + PINCTRL_PIN(158, "AD[22]"), /* K1 */ + PINCTRL_PIN(159, "DA[20]"), /* K2 */ + PINCTRL_PIN(160, "AD[21]"), /* K3 */ + PINCTRL_PIN(161, "DA[19]"), /* K4 */ + PINCTRL_PIN(162, "RVDD"), /* K5 */ + PINCTRL_PIN(163, "GND"), /* K8 */ + PINCTRL_PIN(164, "GND"), /* K9 */ + PINCTRL_PIN(165, "GND"), /* K10 */ + PINCTRL_PIN(166, "GND"), /* K11 */ + PINCTRL_PIN(167, "GND"), /* K12 */ + PINCTRL_PIN(168, "GND"), /* K13 */ + PINCTRL_PIN(169, "CVDD"), /* K16 */ + PINCTRL_PIN(170, "SYM"), /* K17 */ + PINCTRL_PIN(171, "SYP"), /* K18 */ + PINCTRL_PIN(172, "SXM"), /* K19 */ + PINCTRL_PIN(173, "SXP"), /* K20 */ + /* Row L */ + PINCTRL_PIN(174, "DA[18]"), /* L1 */ + PINCTRL_PIN(175, "DA[17]"), /* L2 */ + PINCTRL_PIN(176, "DA[16]"), /* L3 */ + PINCTRL_PIN(177, "DA[15]"), /* L4 */ + PINCTRL_PIN(178, "GND"), /* L5 */ + PINCTRL_PIN(179, "GND"), /* L8 */ + PINCTRL_PIN(180, "GND"), /* L9 */ + PINCTRL_PIN(181, "GND"), /* L10 */ + PINCTRL_PIN(182, "GND"), /* L11 */ + PINCTRL_PIN(183, "GND"), /* L12 */ + PINCTRL_PIN(184, "GND"), /* L13 */ + PINCTRL_PIN(185, "CVDD"), /* L16 */ + PINCTRL_PIN(186, "COL[5]"), /* L17 */ + PINCTRL_PIN(187, "COL[7]"), /* L18 */ + PINCTRL_PIN(188, "RSTON"), /* L19 */ + PINCTRL_PIN(189, "PRSTN"), /* L20 */ + /* Row M */ + PINCTRL_PIN(190, "AD[7]"), /* M1 */ + PINCTRL_PIN(191, "DA[14]"), /* M2 */ + PINCTRL_PIN(192, "AD[6]"), /* M3 */ + PINCTRL_PIN(193, "AD[5]"), /* M4 */ + PINCTRL_PIN(194, "CVDD"), /* M5 */ + PINCTRL_PIN(195, "GND"), /* M8 */ + PINCTRL_PIN(196, "GND"), /* M9 */ + PINCTRL_PIN(197, "GND"), /* M10 */ + PINCTRL_PIN(198, "GND"), /* M11 */ + PINCTRL_PIN(199, "GND"), /* M12 */ + PINCTRL_PIN(200, "GND"), /* M13 */ + PINCTRL_PIN(201, "GND"), /* M16 */ + PINCTRL_PIN(202, "COL[4]"), /* M17 */ + PINCTRL_PIN(203, "COL[3]"), /* M18 */ + PINCTRL_PIN(204, "COL[6]"), /* M19 */ + PINCTRL_PIN(205, "CSN[0]"), /* M20 */ + /* Row N */ + PINCTRL_PIN(206, "DA[13]"), /* N1 */ + PINCTRL_PIN(207, "DA[12]"), /* N2 */ + PINCTRL_PIN(208, "DA[11]"), /* N3 */ + PINCTRL_PIN(209, "AD[3]"), /* N4 */ + PINCTRL_PIN(210, "CVDD"), /* N5 */ + PINCTRL_PIN(211, "CVDD"), /* N6 */ + PINCTRL_PIN(212, "GND"), /* N8 */ + PINCTRL_PIN(213, "GND"), /* N9 */ + PINCTRL_PIN(214, "GND"), /* N10 */ + PINCTRL_PIN(215, "GND"), /* N11 */ + PINCTRL_PIN(216, "GND"), /* N12 */ + PINCTRL_PIN(217, "GND"), /* N13 */ + PINCTRL_PIN(218, "GND"), /* N15 */ + PINCTRL_PIN(219, "GND"), /* N16 */ + PINCTRL_PIN(220, "XTALO"), /* N17 */ + PINCTRL_PIN(221, "COL[0]"), /* N18 */ + PINCTRL_PIN(222, "COL[1]"), /* N19 */ + PINCTRL_PIN(223, "COL[2]"), /* N20 */ + /* Row P */ + PINCTRL_PIN(224, "AD[4]"), /* P1 */ + PINCTRL_PIN(225, "DA[10]"), /* P2 */ + PINCTRL_PIN(226, "DA[9]"), /* P3 */ + PINCTRL_PIN(227, "BRIGHT"), /* P4 */ + PINCTRL_PIN(228, "RVDD"), /* P5 */ + PINCTRL_PIN(229, "RVDD"), /* P6 */ + PINCTRL_PIN(230, "RVDD"), /* P15 */ + PINCTRL_PIN(231, "RVDD"), /* P16 */ + PINCTRL_PIN(232, "XTALI"), /* P17 */ + PINCTRL_PIN(233, "PLL_VDD"), /* P18 */ + PINCTRL_PIN(234, "ROW[6]"), /* P19 */ + PINCTRL_PIN(235, "ROW[7]"), /* P20 */ + /* Row R */ + PINCTRL_PIN(236, "AD[2]"), /* R1 */ + PINCTRL_PIN(237, "AD[1]"), /* R2 */ + PINCTRL_PIN(238, "P[17]"), /* R3 */ + PINCTRL_PIN(239, "P[14]"), /* R4 */ + PINCTRL_PIN(240, "RVDD"), /* R5 */ + PINCTRL_PIN(241, "RVDD"), /* R6 */ + PINCTRL_PIN(242, "GND"), /* R7 */ + PINCTRL_PIN(243, "CVDD"), /* R8 */ + PINCTRL_PIN(244, "CVDD"), /* R13 */ + PINCTRL_PIN(245, "GND"), /* R14 */ + PINCTRL_PIN(246, "RVDD"), /* R15 */ + PINCTRL_PIN(247, "RVDD"), /* R16 */ + PINCTRL_PIN(248, "ROW[0]"), /* R17 */ + PINCTRL_PIN(249, "ROW[3]"), /* R18 */ + PINCTRL_PIN(250, "PLL_GND"), /* R19 */ + PINCTRL_PIN(251, "ROW[5]"), /* R20 */ + /* Row T */ + PINCTRL_PIN(252, "DA[8]"), /* T1 */ + PINCTRL_PIN(253, "BLANK"), /* T2 */ + PINCTRL_PIN(254, "P[13]"), /* T3 */ + PINCTRL_PIN(255, "SPCLK"), /* T4 */ + PINCTRL_PIN(256, "V_CSYNC"), /* T5 */ + PINCTRL_PIN(257, "DD[14]"), /* T6 */ + PINCTRL_PIN(258, "GND"), /* T7 */ + PINCTRL_PIN(259, "CVDD"), /* T8 */ + PINCTRL_PIN(260, "RVDD"), /* T9 */ + PINCTRL_PIN(261, "GND"), /* T10 */ + PINCTRL_PIN(262, "GND"), /* T11 */ + PINCTRL_PIN(263, "RVDD"), /* T12 */ + PINCTRL_PIN(264, "CVDD"), /* T13 */ + PINCTRL_PIN(265, "GND"), /* T14 */ + PINCTRL_PIN(266, "INT[0]"), /* T15 */ + PINCTRL_PIN(267, "USBM[1]"), /* T16 */ + PINCTRL_PIN(268, "RXD[0]"), /* T17 */ + PINCTRL_PIN(269, "TXD[2]"), /* T18 */ + PINCTRL_PIN(270, "ROW[2]"), /* T19 */ + PINCTRL_PIN(271, "ROW[4]"), /* T20 */ + /* Row U */ + PINCTRL_PIN(272, "AD[0]"), /* U1 */ + PINCTRL_PIN(273, "P[15]"), /* U2 */ + PINCTRL_PIN(274, "P[10]"), /* U3 */ + PINCTRL_PIN(275, "P[7]"), /* U4 */ + PINCTRL_PIN(276, "P[6]"), /* U5 */ + PINCTRL_PIN(277, "P[4]"), /* U6 */ + PINCTRL_PIN(278, "P[0]"), /* U7 */ + PINCTRL_PIN(279, "AD[13]"), /* U8 */ + PINCTRL_PIN(280, "DA[3]"), /* U9 */ + PINCTRL_PIN(281, "DA[0]"), /* U10 */ + PINCTRL_PIN(282, "DSRN"), /* U11 */ + PINCTRL_PIN(283, "BOOT[1]"), /* U12 */ + PINCTRL_PIN(284, "NC"), /* U13 */ + PINCTRL_PIN(285, "SSPRX1"), /* U14 */ + PINCTRL_PIN(286, "INT[1]"), /* U15 */ + PINCTRL_PIN(287, "PWMOUT"), /* U16 */ + PINCTRL_PIN(288, "USBM[0]"), /* U17 */ + PINCTRL_PIN(289, "RXD[1]"), /* U18 */ + PINCTRL_PIN(290, "TXD[1]"), /* U19 */ + PINCTRL_PIN(291, "ROW[1]"), /* U20 */ + /* Row V */ + PINCTRL_PIN(292, "P[16]"), /* V1 */ + PINCTRL_PIN(293, "P[11]"), /* V2 */ + PINCTRL_PIN(294, "P[8]"), /* V3 */ + PINCTRL_PIN(295, "DD[15]"), /* V4 */ + PINCTRL_PIN(296, "DD[13]"), /* V5 */ + PINCTRL_PIN(297, "P[1]"), /* V6 */ + PINCTRL_PIN(298, "AD[14]"), /* V7 */ + PINCTRL_PIN(299, "AD[12]"), /* V8 */ + PINCTRL_PIN(300, "DA[2]"), /* V9 */ + PINCTRL_PIN(301, "IDECS0N"), /* V10 */ + PINCTRL_PIN(302, "IDEDA[2]"), /* V11 */ + PINCTRL_PIN(303, "TDI"), /* V12 */ + PINCTRL_PIN(304, "GND"), /* V13 */ + PINCTRL_PIN(305, "ASYNC"), /* V14 */ + PINCTRL_PIN(306, "SSPTX1"), /* V15 */ + PINCTRL_PIN(307, "INT[2]"), /* V16 */ + PINCTRL_PIN(308, "RTSN"), /* V17 */ + PINCTRL_PIN(309, "USBP[0]"), /* V18 */ + PINCTRL_PIN(310, "CTSN"), /* V19 */ + PINCTRL_PIN(311, "TXD[0]"), /* V20 */ + /* Row W */ + PINCTRL_PIN(312, "P[12]"), /* W1 */ + PINCTRL_PIN(313, "P[9]"), /* W2 */ + PINCTRL_PIN(314, "DD[0]"), /* W3 */ + PINCTRL_PIN(315, "P[5]"), /* W4 */ + PINCTRL_PIN(316, "P[3]"), /* W5 */ + PINCTRL_PIN(317, "DA[7]"), /* W6 */ + PINCTRL_PIN(318, "DA[5]"), /* W7 */ + PINCTRL_PIN(319, "AD[11]"), /* W8 */ + PINCTRL_PIN(320, "AD[9]"), /* W9 */ + PINCTRL_PIN(321, "IDECS1N"), /* W10 */ + PINCTRL_PIN(322, "IDEDA[1]"), /* W11 */ + PINCTRL_PIN(323, "TCK"), /* W12 */ + PINCTRL_PIN(324, "TMS"), /* W13 */ + PINCTRL_PIN(325, "EECLK"), /* W14 */ + PINCTRL_PIN(326, "SCLK1"), /* W15 */ + PINCTRL_PIN(327, "GRLED"), /* W16 */ + PINCTRL_PIN(328, "INT[3]"), /* W17 */ + PINCTRL_PIN(329, "SLA[1]"), /* W18 */ + PINCTRL_PIN(330, "SLA[0]"), /* W19 */ + PINCTRL_PIN(331, "RXD[2]"), /* W20 */ + /* Row Y */ + PINCTRL_PIN(332, "HSYNC"), /* Y1 */ + PINCTRL_PIN(333, "DD[1]"), /* Y2 */ + PINCTRL_PIN(334, "DD[12]"), /* Y3 */ + PINCTRL_PIN(335, "P[2]"), /* Y4 */ + PINCTRL_PIN(336, "AD[15]"), /* Y5 */ + PINCTRL_PIN(337, "DA[6]"), /* Y6 */ + PINCTRL_PIN(338, "DA[4]"), /* Y7 */ + PINCTRL_PIN(339, "AD[10]"), /* Y8 */ + PINCTRL_PIN(340, "DA[1]"), /* Y9 */ + PINCTRL_PIN(341, "AD[8]"), /* Y10 */ + PINCTRL_PIN(342, "IDEDA[0]"), /* Y11 */ + PINCTRL_PIN(343, "DTRN"), /* Y12 */ + PINCTRL_PIN(344, "TDO"), /* Y13 */ + PINCTRL_PIN(345, "BOOT[0]"), /* Y14 */ + PINCTRL_PIN(346, "EEDAT"), /* Y15 */ + PINCTRL_PIN(347, "ASDO"), /* Y16 */ + PINCTRL_PIN(348, "SFRM1"), /* Y17 */ + PINCTRL_PIN(349, "RDLED"), /* Y18 */ + PINCTRL_PIN(350, "USBP[1]"), /* Y19 */ + PINCTRL_PIN(351, "ABITCLK"), /* Y20 */ +}; + +static const unsigned int ssp_ep9312_pins[] =3D { + 285, 306, 326, 348, +}; + +static const unsigned int ac97_ep9312_pins[] =3D { + 77, 95, 305, 347, 351, +}; + +static const unsigned int pwm_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio1a_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio2a_9312_pins[] =3D { + 234, 235, 248, 249, 251, 270, 271, 291, +}; + +static const unsigned int gpio3a_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223, +}; + +static const unsigned int keypad_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223, + 234, 235, 248, 249, 251, 270, 271, 291, +}; + +static const unsigned int gpio4a_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342, +}; + +static const unsigned int gpio6a_9312_pins[] =3D { + 257, 295, 296, 334, +}; + +static const unsigned int gpio7a_9312_pins[] =3D { + 4, 24, 25, 45, 46, 66, 314, 333, +}; + +static const unsigned int ide_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342, 257, 295, + 296, 334, 4, 24, 25, 45, 46, 66, + 314, 333, +}; + +static const struct ep93xx_pin_group ep9312_pin_groups[] =3D { + PMX_GROUP("ssp", ssp_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, 0), + PMX_GROUP("i2s_on_ssp", ssp_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONSSP, + EP93XX_SYSCON_DEVCFG_I2SONSSP), + PMX_GROUP("pwm1", pwm_ep9312_pins, EP93XX_SYSCON_DEVCFG_PONG, + EP93XX_SYSCON_DEVCFG_PONG), + PMX_GROUP("gpio1agrp", gpio1a_ep9312_pins, EP93XX_SYSCON_DEVCFG_PONG, 0), + PMX_GROUP("ac97", ac97_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, 0), + PMX_GROUP("i2s_on_ac97", ac97_ep9312_pins, EP93XX_SYSCON_DEVCFG_I2SONAC97, + EP93XX_SYSCON_DEVCFG_I2SONAC97), + PMX_GROUP("rasteronsdram0grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCF= G_RASONP3, 0), + PMX_GROUP("rasteronsdram3grp", raster_on_sdram0_pins, EP93XX_SYSCON_DEVCF= G_RASONP3, + EP93XX_SYSCON_DEVCFG_RASONP3), + PMX_GROUP("gpio2agrp", gpio2a_9312_pins, EP93XX_SYSCON_DEVCFG_GONK, + EP93XX_SYSCON_DEVCFG_GONK), + PMX_GROUP("gpio3agrp", gpio3a_9312_pins, EP93XX_SYSCON_DEVCFG_GONK, + EP93XX_SYSCON_DEVCFG_GONK), + PMX_GROUP("keypadgrp", keypad_9312_pins, EP93XX_SYSCON_DEVCFG_GONK, 0), + PMX_GROUP("gpio4agrp", gpio4a_9312_pins, EP93XX_SYSCON_DEVCFG_EONIDE, + EP93XX_SYSCON_DEVCFG_EONIDE), + PMX_GROUP("gpio6agrp", gpio6a_9312_pins, EP93XX_SYSCON_DEVCFG_GONIDE, + EP93XX_SYSCON_DEVCFG_GONIDE), + PMX_GROUP("gpio7agrp", gpio7a_9312_pins, EP93XX_SYSCON_DEVCFG_HONIDE, + EP93XX_SYSCON_DEVCFG_HONIDE), + PMX_GROUP("idegrp", ide_9312_pins, EP93XX_SYSCON_DEVCFG_EONIDE | + EP93XX_SYSCON_DEVCFG_GONIDE | EP93XX_SYSCON_DEVCFG_HONIDE, 0), +}; + +static int ep93xx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ARRAY_SIZE(ep9301_pin_groups); + case EP93XX_9307_PINCTRL: + return ARRAY_SIZE(ep9307_pin_groups); + case EP93XX_9312_PINCTRL: + return ARRAY_SIZE(ep9312_pin_groups); + default: + return 0; + } +} + +static const char *ep93xx_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ep9301_pin_groups[selector].grp.name; + case EP93XX_9307_PINCTRL: + return ep9307_pin_groups[selector].grp.name; + case EP93XX_9312_PINCTRL: + return ep9312_pin_groups[selector].grp.name; + default: + return NULL; + } +} + +static int ep93xx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + *pins =3D ep9301_pin_groups[selector].grp.pins; + *num_pins =3D ep9301_pin_groups[selector].grp.npins; + break; + case EP93XX_9307_PINCTRL: + *pins =3D ep9307_pin_groups[selector].grp.pins; + *num_pins =3D ep9307_pin_groups[selector].grp.npins; + break; + case EP93XX_9312_PINCTRL: + *pins =3D ep9312_pin_groups[selector].grp.pins; + *num_pins =3D ep9312_pin_groups[selector].grp.npins; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct pinctrl_ops ep93xx_pctrl_ops =3D { + .get_groups_count =3D ep93xx_get_groups_count, + .get_group_name =3D ep93xx_get_group_name, + .get_group_pins =3D ep93xx_get_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +static const char * const spigrps[] =3D { "ssp" }; +static const char * const ac97grps[] =3D { "ac97" }; +static const char * const i2sgrps[] =3D { "i2s_on_ssp", "i2s_on_ac97" }; +static const char * const pwm1grps[] =3D { "pwm1" }; +static const char * const gpiogrps[] =3D { "gpio1agrp", "gpio2agrp", "gpio= 3agrp", + "gpio4agrp", "gpio6agrp", "gpio7agrp" }; +static const char * const rastergrps[] =3D { "rasteronsdram0grp", "rastero= nsdram3grp"}; +static const char * const keypadgrps[] =3D { "keypadgrp"}; +static const char * const idegrps[] =3D { "idegrp"}; + +static const struct pinfunction ep93xx_pmx_functions[] =3D { + PINCTRL_PINFUNCTION("spi", spigrps, ARRAY_SIZE(spigrps)), + PINCTRL_PINFUNCTION("ac97", ac97grps, ARRAY_SIZE(ac97grps)), + PINCTRL_PINFUNCTION("i2s", i2sgrps, ARRAY_SIZE(i2sgrps)), + PINCTRL_PINFUNCTION("pwm", pwm1grps, ARRAY_SIZE(pwm1grps)), + PINCTRL_PINFUNCTION("keypad", keypadgrps, ARRAY_SIZE(keypadgrps)), + PINCTRL_PINFUNCTION("pata", idegrps, ARRAY_SIZE(idegrps)), + PINCTRL_PINFUNCTION("lcd", rastergrps, ARRAY_SIZE(rastergrps)), + PINCTRL_PINFUNCTION("gpio", gpiogrps, ARRAY_SIZE(gpiogrps)), +}; + +static int ep93xx_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct ep93xx_pmx *pmx; + const struct pinfunction *func; + const struct ep93xx_pin_group *grp; + u32 before, after, expected; + unsigned long tmp; + int i; + + pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + grp =3D &ep9301_pin_groups[group]; + break; + case EP93XX_9307_PINCTRL: + grp =3D &ep9307_pin_groups[group]; + break; + case EP93XX_9312_PINCTRL: + grp =3D &ep9312_pin_groups[group]; + break; + default: + dev_err(pmx->dev, "invalid SoC type\n"); + return -ENODEV; + } + + func =3D &ep93xx_pmx_functions[selector]; + + dev_dbg(pmx->dev, + "ACTIVATE function \"%s\" with group \"%s\" (mask=3D0x%x, value=3D0x%x)\= n", + func->name, grp->grp.name, grp->mask, grp->value); + + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &before); + ep93xx_pinctrl_update_bits(pmx, EP93XX_SYSCON_DEVCFG, + grp->mask, grp->value); + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &after); + + dev_dbg(pmx->dev, "before=3D0x%x, after=3D0x%x, mask=3D0x%lx\n", + before, after, PADS_MASK); + + /* Which bits changed */ + before &=3D PADS_MASK; + after &=3D PADS_MASK; + expected =3D before & ~grp->mask; + expected |=3D grp->value; + expected &=3D PADS_MASK; + + /* Print changed states */ + tmp =3D expected ^ after; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + bool enabled =3D expected & BIT(i); + + dev_err(pmx->dev, + "pin group %s could not be %s: probably a hardware limitation\n", + ep93xx_padgroups[i], str_enabled_disabled(enabled)); + dev_err(pmx->dev, + "DeviceCfg before: %08x, after %08x, expected %08x\n", + before, after, expected); + } + + return tmp ? -EINVAL : 0; +}; + +static int ep93xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(ep93xx_pmx_functions); +} + +static const char *ep93xx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return ep93xx_pmx_functions[selector].name; +} + +static int ep93xx_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D ep93xx_pmx_functions[selector].groups; + *num_groups =3D ep93xx_pmx_functions[selector].ngroups; + return 0; +} + +static const struct pinmux_ops ep93xx_pmx_ops =3D { + .get_functions_count =3D ep93xx_pmx_get_funcs_count, + .get_function_name =3D ep93xx_pmx_get_func_name, + .get_function_groups =3D ep93xx_pmx_get_groups, + .set_mux =3D ep93xx_pmx_set_mux, +}; + +static struct pinctrl_desc ep93xx_pmx_desc =3D { + .name =3D DRIVER_NAME, + .pctlops =3D &ep93xx_pctrl_ops, + .pmxops =3D &ep93xx_pmx_ops, + .owner =3D THIS_MODULE, +}; + +static int ep93xx_pmx_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct ep93xx_regmap_adev *rdev =3D to_ep93xx_regmap_adev(adev); + struct device *dev =3D &adev->dev; + struct ep93xx_pmx *pmx; + + /* Create state holders etc for this driver */ + pmx =3D devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev =3D dev; + pmx->map =3D rdev->map; + pmx->aux_dev =3D rdev; + pmx->model =3D (enum ep93xx_pinctrl_model)(uintptr_t)id->driver_data; + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9301_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9301_pins); + dev_info(dev, "detected 9301/9302 chip variant\n"); + break; + case EP93XX_9307_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9307_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9307_pins); + dev_info(dev, "detected 9307 chip variant\n"); + break; + case EP93XX_9312_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9312_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9312_pins); + dev_info(dev, "detected 9312/9315 chip variant\n"); + break; + default: + return dev_err_probe(dev, -EINVAL, "unknown pin control model: %u\n", pm= x->model); + } + + /* using parent of_node to match in get_pinctrl_dev_from_of_node() */ + device_set_node(dev, dev_fwnode(adev->dev.parent)); + pmx->pctl =3D devm_pinctrl_register(dev, &ep93xx_pmx_desc, pmx); + if (IS_ERR(pmx->pctl)) + return dev_err_probe(dev, PTR_ERR(pmx->pctl), "could not register pinmux= driver\n"); + + return 0; +}; + +static const struct auxiliary_device_id ep93xx_pinctrl_ids[] =3D { + { + .name =3D "soc_ep93xx.pinctrl-ep9301", + .driver_data =3D (kernel_ulong_t)EP93XX_9301_PINCTRL, + }, + { + .name =3D "soc_ep93xx.pinctrl-ep9307", + .driver_data =3D (kernel_ulong_t)EP93XX_9307_PINCTRL, + }, + { + .name =3D "soc_ep93xx.pinctrl-ep9312", + .driver_data =3D (kernel_ulong_t)EP93XX_9312_PINCTRL, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, ep93xx_pinctrl_ids); + +static struct auxiliary_driver ep93xx_pmx_driver =3D { + .probe =3D ep93xx_pmx_probe, + .id_table =3D ep93xx_pinctrl_ids, +}; +module_auxiliary_driver(ep93xx_pmx_driver); --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56E25185094; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=DBl6WT8gG01G0jdBfRivplcGgSTsyKLejsZwx/vRRuyj8ibKh4w1I2DnbiN8PQDI59cae32x4kjWLf/WuVyWohybamvdZPzadSfY6DLNXBazkhDvvFXfPdN8161EduxuhwJ/2e93mQ2SWKrVpHmXr4+B6pn7iX4XZFXFrG56jI4= ARC-Message-Signature: i=1; a=rsa-sha256; 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<20240715-ep93xx-v11-5-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Sebastian Reichel Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=4433; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=onC/yUOhswI9EYOcxGSoR30thUvusn3WXoEialTiwl4=; b=dZEYfMdHs1rJy9XoKOuEB/r5os+D/nGwnOMro6xuqDTvbQ+n2p7eXbtFRJiF4eXhINbPTQVFP/Lk kbJtlupLBepFPmps1n+6T4r5MhD0TDpEC/ADdR3I4qQj99fF6/QB X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Implement the reset behaviour of the various EP93xx SoCS in drivers/power/reset. It used to be located in arch/arm/mach-ep93xx. Signed-off-by: Nikita Shubin Acked-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 10 +++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/ep93xx-restart.c | 84 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 95 insertions(+) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fece990af4a7..389d5a193e5d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -75,6 +75,16 @@ config POWER_RESET_BRCMSTB Say Y here if you have a Broadcom STB board and you wish to have restart support. =20 +config POWER_RESET_EP93XX + bool "Cirrus EP93XX reset driver" if COMPILE_TEST + depends on MFD_SYSCON + default ARCH_EP93XX + help + This driver provides restart support for Cirrus EP93XX SoC. + + Say Y here if you have a Cirrus EP93XX SoC and you wish + to have restart support. + config POWER_RESET_GEMINI_POWEROFF bool "Cortina Gemini power-off driver" depends on ARCH_GEMINI || COMPILE_TEST diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index a95d1bd275d1..10782d32e1da 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_POWER_RESET_ATC260X) +=3D atc260x-poweroff.o obj-$(CONFIG_POWER_RESET_AXXIA) +=3D axxia-reset.o obj-$(CONFIG_POWER_RESET_BRCMKONA) +=3D brcm-kona-reset.o obj-$(CONFIG_POWER_RESET_BRCMSTB) +=3D brcmstb-reboot.o +obj-$(CONFIG_POWER_RESET_EP93XX) +=3D ep93xx-restart.o obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) +=3D gemini-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO) +=3D gpio-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO_RESTART) +=3D gpio-restart.o diff --git a/drivers/power/reset/ep93xx-restart.c b/drivers/power/reset/ep9= 3xx-restart.c new file mode 100644 index 000000000000..57cfb8620faf --- /dev/null +++ b/drivers/power/reset/ep93xx-restart.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cirrus EP93xx SoC reset driver + * + * Copyright (C) 2021 Nikita Shubin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EP93XX_SYSCON_DEVCFG 0x80 +#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31) + +struct ep93xx_restart { + struct ep93xx_regmap_adev *aux_dev; + struct notifier_block restart_handler; +}; + +static int ep93xx_restart_handle(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + struct ep93xx_restart *priv =3D + container_of(this, struct ep93xx_restart, restart_handler); + struct ep93xx_regmap_adev *aux =3D priv->aux_dev; + + /* Issue the reboot */ + aux->update_bits(aux->map, aux->lock, EP93XX_SYSCON_DEVCFG, + EP93XX_SYSCON_DEVCFG_SWRST, EP93XX_SYSCON_DEVCFG_SWRST); + aux->update_bits(aux->map, aux->lock, EP93XX_SYSCON_DEVCFG, + EP93XX_SYSCON_DEVCFG_SWRST, 0); + + return NOTIFY_DONE; +} + +static int ep93xx_reboot_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct ep93xx_regmap_adev *rdev =3D to_ep93xx_regmap_adev(adev); + struct device *dev =3D &adev->dev; + struct ep93xx_restart *priv; + int err; + + if (!rdev->update_bits) + return -ENODEV; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->aux_dev =3D rdev; + + priv->restart_handler.notifier_call =3D ep93xx_restart_handle; + priv->restart_handler.priority =3D 128; + + err =3D register_restart_handler(&priv->restart_handler); + if (err) + return dev_err_probe(dev, err, "can't register restart notifier\n"); + + return 0; +} + +static const struct auxiliary_device_id ep93xx_reboot_ids[] =3D { + { + .name =3D "soc_ep93xx.reset-ep93xx", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, ep93xx_reboot_ids); + +static struct auxiliary_driver ep93xx_reboot_driver =3D { + .probe =3D ep93xx_reboot_probe, + .id_table =3D ep93xx_reboot_ids, +}; +module_auxiliary_driver(ep93xx_reboot_driver); --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74FDD1850AD; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-6-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Nikita Shubin , Alexander Sverdlin Cc: Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=6134; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=3qRH8iBzDzq1XDMd29PQTUf0/U/lo+zRZQ47DrczBzM=; b=RjB/JAhhA5VLyteob8W1OGdQSth/21/AC5heCSD9XABCeWwEMZ2c87T2qh+0OAau9NDoPS6aoWnt fxIRFa6sBqN4xhpZ5Qe6RGrRkbPnVIBV6jjaoVrVMgyHo9QbP5G6 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add device tree bindings for the Cirrus Logic EP93xx SoC. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd --- .../bindings/arm/cirrus/cirrus,ep9301.yaml | 38 +++++++++ .../bindings/soc/cirrus/cirrus,ep9301-syscon.yaml | 94 ++++++++++++++++++= ++++ include/dt-bindings/clock/cirrus,ep9301-syscon.h | 46 +++++++++++ 3 files changed, 178 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yam= l b/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml new file mode 100644 index 000000000000..170aad5dd7ed --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cirrus/cirrus,ep9301.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cirrus/cirrus,ep9301.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx platforms + +description: + The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU. + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The TS-7250 is a compact, full-featured Single Board + Computer (SBC) based upon the Cirrus EP9302 ARM9 CPU + items: + - const: technologic,ts7250 + - const: cirrus,ep9301 + + - description: The Liebherr BK3 is a derivate from ts7250 board + items: + - const: liebherr,bk3 + - const: cirrus,ep9301 + + - description: EDB302 is an evaluation board by Cirrus Logic, + based on a Cirrus Logic EP9302 CPU + items: + - const: cirrus,edb9302 + - const: cirrus,ep9301 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-sys= con.yaml b/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-sysco= n.yaml new file mode 100644 index 000000000000..7cb1b4114985 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cirrus/cirrus,ep9301-syscon.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cirrus/cirrus,ep9301-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx Platforms System Controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +description: | + Central resources are controlled by a set of software-locked registers, + which can be used to prevent accidental accesses. Syscon generates + the various bus and peripheral clocks and controls the system startup + configuration. + + The System Controller (Syscon) provides: + - Clock control + - Power management + - System configuration management + + Syscon registers are common for all EP93xx SoC's, through some actual pe= ripheral + may be missing depending on actual SoC model. + +properties: + compatible: + oneOf: + - items: + - enum: + - cirrus,ep9302-syscon + - cirrus,ep9307-syscon + - cirrus,ep9312-syscon + - cirrus,ep9315-syscon + - const: cirrus,ep9301-syscon + - const: syscon + - items: + - const: cirrus,ep9301-syscon + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + items: + - description: reference clock + +patternProperties: + '^pins-': + type: object + description: pin node + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + enum: [ spi, ac97, i2s, pwm, keypad, pata, lcd, gpio ] + + groups: + enum: [ ssp, ac97, i2s_on_ssp, i2s_on_ac97, pwm1, gpio1agrp, + gpio2agrp, gpio3agrp, gpio4agrp, gpio6agrp, gpio7agrp, + rasteronsdram0grp, rasteronsdram3grp, keypadgrp, idegrp ] + + required: + - function + - groups + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", "syscon"; + reg =3D <0x80930000 0x1000>; + + #clock-cells =3D <1>; + clocks =3D <&xtali>; + + spi_default_pins: pins-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + }; diff --git a/include/dt-bindings/clock/cirrus,ep9301-syscon.h b/include/dt-= bindings/clock/cirrus,ep9301-syscon.h new file mode 100644 index 000000000000..6bb8f532e7d0 --- /dev/null +++ b/include/dt-bindings/clock/cirrus,ep9301-syscon.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H +#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H + +#define EP93XX_CLK_PLL1 0 +#define EP93XX_CLK_PLL2 1 + +#define EP93XX_CLK_FCLK 2 +#define EP93XX_CLK_HCLK 3 +#define EP93XX_CLK_PCLK 4 + +#define EP93XX_CLK_UART 5 +#define EP93XX_CLK_SPI 6 +#define EP93XX_CLK_PWM 7 +#define EP93XX_CLK_USB 8 + +#define EP93XX_CLK_M2M0 9 +#define EP93XX_CLK_M2M1 10 + +#define EP93XX_CLK_M2P0 11 +#define EP93XX_CLK_M2P1 12 +#define EP93XX_CLK_M2P2 13 +#define EP93XX_CLK_M2P3 14 +#define EP93XX_CLK_M2P4 15 +#define EP93XX_CLK_M2P5 16 +#define EP93XX_CLK_M2P6 17 +#define EP93XX_CLK_M2P7 18 +#define EP93XX_CLK_M2P8 19 +#define EP93XX_CLK_M2P9 20 + +#define EP93XX_CLK_UART1 21 +#define EP93XX_CLK_UART2 22 +#define EP93XX_CLK_UART3 23 + +#define EP93XX_CLK_ADC 24 +#define EP93XX_CLK_ADC_EN 25 + +#define EP93XX_CLK_KEYPAD 26 + +#define EP93XX_CLK_VIDEO 27 + +#define EP93XX_CLK_I2S_MCLK 28 +#define EP93XX_CLK_I2S_SCLK 29 +#define EP93XX_CLK_I2S_LRCLK 30 + +#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */ --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 771211850AE for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-7-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Conor Dooley , Ulf Hansson , Wei Xu , Linus Walleij , Huisong Li , Nikita Shubin , Arnd Bergmann , Yangyu Chen , Alexander Sverdlin Cc: Samuel Holland , linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=10094; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=h+nsr3/JzUq8M03+M6Q37Bv92w6lA4fD8MhEeOMM2lo=; b=SqPLurSXLfpWEeND0E/pAU5SD+L9iffHZTKtkVBAwEI63h2J9bl3ZuvalcXsIrjX5hxGQ+hz5Mf/ IS/BeS1JDAiZLSPbUIrGeunlJItokmDvXCMSFUnrWKYyo74lZxKX X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add an SoC driver for the ep93xx. Currently there is only one thing not fitting into any other framework, and that is the swlock setting. Used for clock settings, pinctrl and restart. Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin Acked-by: Alexander Sverdlin Reviewed-by: Linus Walleij --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cirrus/Kconfig | 17 +++ drivers/soc/cirrus/Makefile | 2 + drivers/soc/cirrus/soc-ep93xx.c | 252 ++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 273 insertions(+) diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 5d924e946507..6a8daeb8c4b9 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -7,6 +7,7 @@ source "drivers/soc/aspeed/Kconfig" source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" +source "drivers/soc/cirrus/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/hisilicon/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index fb2bd31387d0..b10a52a91fe4 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -8,6 +8,7 @@ obj-y +=3D aspeed/ obj-$(CONFIG_ARCH_AT91) +=3D atmel/ obj-y +=3D bcm/ obj-$(CONFIG_ARCH_CANAAN) +=3D canaan/ +obj-$(CONFIG_EP93XX_SOC) +=3D cirrus/ obj-$(CONFIG_ARCH_DOVE) +=3D dove/ obj-$(CONFIG_MACH_DOVE) +=3D dove/ obj-y +=3D fsl/ diff --git a/drivers/soc/cirrus/Kconfig b/drivers/soc/cirrus/Kconfig new file mode 100644 index 000000000000..f2fd0e16a196 --- /dev/null +++ b/drivers/soc/cirrus/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if ARCH_EP93XX + +config EP93XX_SOC + bool "Cirrus EP93xx chips SoC" + select SOC_BUS + select AUXILIARY_BUS + default y if !EP93XX_SOC_COMMON + help + Enable support SoC for Cirrus EP93xx chips. + + Cirrus EP93xx chips have several swlocked registers, + this driver provides locked access for reset, pinctrl + and clk devices implemented as auxiliary devices. + +endif diff --git a/drivers/soc/cirrus/Makefile b/drivers/soc/cirrus/Makefile new file mode 100644 index 000000000000..9e6608b67f76 --- /dev/null +++ b/drivers/soc/cirrus/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y +=3D soc-ep93xx.o diff --git a/drivers/soc/cirrus/soc-ep93xx.c b/drivers/soc/cirrus/soc-ep93x= x.c new file mode 100644 index 000000000000..3e79b3b13aef --- /dev/null +++ b/drivers/soc/cirrus/soc-ep93xx.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SoC driver for Cirrus EP93xx chips. + * Copyright (C) 2022 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/core.c + * Copyright (C) 2006 Lennert Buytenhek + * Copyright (C) 2007 Herbert Valerio Riedel + * + * Thanks go to Michael Burian and Ray Lehtiniemi for their key + * role in the ep93xx Linux community. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EP93XX_SYSCON_DEVCFG 0x80 + +#define EP93XX_SWLOCK_MAGICK 0xaa +#define EP93XX_SYSCON_SWLOCK 0xc0 +#define EP93XX_SYSCON_SYSCFG 0x9c +#define EP93XX_SYSCON_SYSCFG_REV_MASK GENMASK(31, 28) +#define EP93XX_SYSCON_SYSCFG_REV_SHIFT 28 + +struct ep93xx_map_info { + spinlock_t lock; + void __iomem *base; + struct regmap *map; +}; + +/* + * EP93xx System Controller software locked register write + * + * Logic safeguards are included to condition the control signals for + * power connection to the matrix to prevent part damage. In addition, a + * software lock register is included that must be written with 0xAA + * before each register write to change the values of the four switch + * matrix control registers. + */ +static void ep93xx_regmap_write(struct regmap *map, spinlock_t *lock, + unsigned int reg, unsigned int val) +{ + guard(spinlock_irqsave)(lock); + + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, reg, val); +} + +static void ep93xx_regmap_update_bits(struct regmap *map, spinlock_t *lock, + unsigned int reg, unsigned int mask, + unsigned int val) +{ + guard(spinlock_irqsave)(lock); + + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + /* force write is required to clear swlock if no changes are made */ + regmap_update_bits_base(map, reg, mask, val, NULL, false, true); +} + +static void ep93xx_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev =3D _adev; + + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static void ep93xx_adev_release(struct device *dev) +{ + struct auxiliary_device *adev =3D to_auxiliary_dev(dev); + struct ep93xx_regmap_adev *rdev =3D to_ep93xx_regmap_adev(adev); + + kfree(rdev); +} + +static struct auxiliary_device __init *ep93xx_adev_alloc(struct device *pa= rent, + const char *name, + struct ep93xx_map_info *info) +{ + struct ep93xx_regmap_adev *rdev __free(kfree) =3D NULL; + struct auxiliary_device *adev; + int ret; + + rdev =3D kzalloc(sizeof(*rdev), GFP_KERNEL); + if (!rdev) + return ERR_PTR(-ENOMEM); + + rdev->map =3D info->map; + rdev->base =3D info->base; + rdev->lock =3D &info->lock; + rdev->write =3D ep93xx_regmap_write; + rdev->update_bits =3D ep93xx_regmap_update_bits; + + adev =3D &rdev->adev; + adev->name =3D name; + adev->dev.parent =3D parent; + adev->dev.release =3D ep93xx_adev_release; + + ret =3D auxiliary_device_init(adev); + if (ret) + return ERR_PTR(ret); + + return &no_free_ptr(rdev)->adev; +} + +static int __init ep93xx_controller_register(struct device *parent, const = char *name, + struct ep93xx_map_info *info) +{ + struct auxiliary_device *adev; + int ret; + + adev =3D ep93xx_adev_alloc(parent, name, info); + if (IS_ERR(adev)) + return PTR_ERR(adev); + + ret =3D auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; + } + + return devm_add_action_or_reset(parent, ep93xx_unregister_adev, adev); +} + +static unsigned int __init ep93xx_soc_revision(struct regmap *map) +{ + unsigned int val; + + regmap_read(map, EP93XX_SYSCON_SYSCFG, &val); + val &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; + val >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; + return val; +} + +static const char __init *ep93xx_get_soc_rev(unsigned int rev) +{ + switch (rev) { + case EP93XX_CHIP_REV_D0: + return "D0"; + case EP93XX_CHIP_REV_D1: + return "D1"; + case EP93XX_CHIP_REV_E0: + return "E0"; + case EP93XX_CHIP_REV_E1: + return "E1"; + case EP93XX_CHIP_REV_E2: + return "E2"; + default: + return "unknown"; + } +} + +static const char *pinctrl_names[] __initconst =3D { + "pinctrl-ep9301", /* EP93XX_9301_SOC */ + "pinctrl-ep9307", /* EP93XX_9307_SOC */ + "pinctrl-ep9312", /* EP93XX_9312_SOC */ +}; + +static int __init ep93xx_syscon_probe(struct platform_device *pdev) +{ + enum ep93xx_soc_model model; + struct ep93xx_map_info *map_info; + struct soc_device_attribute *attrs; + struct soc_device *soc_dev; + struct device *dev =3D &pdev->dev; + struct regmap *map; + void __iomem *base; + unsigned int rev; + int ret; + + model =3D (enum ep93xx_soc_model)(uintptr_t)device_get_match_data(dev); + + map =3D device_node_to_regmap(dev->of_node); + if (IS_ERR(map)) + return PTR_ERR(map); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + attrs =3D devm_kzalloc(dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + rev =3D ep93xx_soc_revision(map); + + attrs->machine =3D of_flat_dt_get_machine_name(); + attrs->family =3D "Cirrus Logic EP93xx"; + attrs->revision =3D ep93xx_get_soc_rev(rev); + + soc_dev =3D soc_device_register(attrs); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + map_info =3D devm_kzalloc(dev, sizeof(*map_info), GFP_KERNEL); + if (!map_info) + return -ENOMEM; + + spin_lock_init(&map_info->lock); + map_info->map =3D map; + map_info->base =3D base; + + ret =3D ep93xx_controller_register(dev, pinctrl_names[model], map_info); + if (ret) + dev_err(dev, "registering pinctrl controller failed\n"); + + /* + * EP93xx SSP clock rate was doubled in version E2. For more information + * see section 6 "2x SSP (Synchronous Serial Port) Clock =E2=80=93 Revisi= on E2 only": + * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf + */ + if (rev =3D=3D EP93XX_CHIP_REV_E2) + ret =3D ep93xx_controller_register(dev, "clk-ep93xx.e2", map_info); + else + ret =3D ep93xx_controller_register(dev, "clk-ep93xx", map_info); + if (ret) + dev_err(dev, "registering clock controller failed\n"); + + ret =3D ep93xx_controller_register(dev, "reset-ep93xx", map_info); + if (ret) + dev_err(dev, "registering reset controller failed\n"); + + return 0; +} + +static const struct of_device_id ep9301_syscon_of_device_ids[] =3D { + { .compatible =3D "cirrus,ep9301-syscon", .data =3D (void *)EP93XX_9301_S= OC }, + { .compatible =3D "cirrus,ep9302-syscon", .data =3D (void *)EP93XX_9301_S= OC }, + { .compatible =3D "cirrus,ep9307-syscon", .data =3D (void *)EP93XX_9307_S= OC }, + { .compatible =3D "cirrus,ep9312-syscon", .data =3D (void *)EP93XX_9312_S= OC }, + { .compatible =3D "cirrus,ep9315-syscon", .data =3D (void *)EP93XX_9312_S= OC }, + { /* sentinel */ } +}; + +static struct platform_driver ep9301_syscon_driver =3D { + .driver =3D { + .name =3D "ep9301-syscon", + .of_match_table =3D ep9301_syscon_of_device_ids, + }, +}; +builtin_platform_driver_probe(ep9301_syscon_driver, ep93xx_syscon_probe); --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 954EA185600; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=H+YvtR6FV0Gzly9zTC6hBMWPgTJz3zkCznn8L7Rd6gszaZ9BC1d5KTvS01OsYC3aFro6zCBDixHAXBUbfT8cQAzdjGfShS5ZDmX6bt8BII7zuX44QBIy7dcy55m9tFQAeTmF7PNUMrz3LPZCO40KLeWYR1MyHyVPSBp/3iqXVbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:12 +0300 Subject: [PATCH v11 08/38] dt-bindings: dma: Add Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-8-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Sverdlin , Nikita Shubin Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=7696; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=Y0DItFCDipfwR6StRBre7127VedaUlKJubOzvlu96UM=; b=7dFmAkBz7QE3VxJ6WkIoiypYmMr5KL0m9mEOxy/BXsaT+D5HNEEwkFu3B6z4Xk7rVFUgIq9mHRLR dfkawcPTC9EbFNgkQK+zW0UHjEFs1hYQ27fmXaHCaRJs0Ppp/2hZ X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ep93xx SoC DMA. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski Acked-by: Vinod Koul --- .../bindings/dma/cirrus,ep9301-dma-m2m.yaml | 84 ++++++++++++ .../bindings/dma/cirrus,ep9301-dma-m2p.yaml | 144 +++++++++++++++++= ++++ 2 files changed, 228 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml new file mode 100644 index 000000000000..871b76ddf90f --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx SoC DMA controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2m + - items: + - enum: + - cirrus,ep9302-dma-m2m + - cirrus,ep9307-dma-m2m + - cirrus,ep9312-dma-m2m + - cirrus,ep9315-dma-m2m + - const: cirrus,ep9301-dma-m2m + + reg: + items: + - description: m2m0 channel registers + - description: m2m1 channel registers + + clocks: + items: + - description: m2m0 channel gate clock + - description: m2m1 channel gate clock + + clock-names: + items: + - const: m2m0 + - const: m2m1 + + interrupts: + items: + - description: m2m0 channel interrupt + - description: m2m1 channel interrupt + + '#dma-cells': + const: 2 + description: | + The first cell is the unique device channel number as indicated by t= his + table for ep93xx: + + 10: SPI controller + 11: IDE controller + + The second cell is the DMA direction line number: + + 1: Memory to device + 2: Device to memory + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + #dma-cells =3D <2>; + }; diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml new file mode 100644 index 000000000000..d14c31553543 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx SoC M2P DMA controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2p + - items: + - enum: + - cirrus,ep9302-dma-m2p + - cirrus,ep9307-dma-m2p + - cirrus,ep9312-dma-m2p + - cirrus,ep9315-dma-m2p + - const: cirrus,ep9301-dma-m2p + + reg: + items: + - description: m2p0 channel registers + - description: m2p1 channel registers + - description: m2p2 channel registers + - description: m2p3 channel registers + - description: m2p4 channel registers + - description: m2p5 channel registers + - description: m2p6 channel registers + - description: m2p7 channel registers + - description: m2p8 channel registers + - description: m2p9 channel registers + + clocks: + items: + - description: m2p0 channel gate clock + - description: m2p1 channel gate clock + - description: m2p2 channel gate clock + - description: m2p3 channel gate clock + - description: m2p4 channel gate clock + - description: m2p5 channel gate clock + - description: m2p6 channel gate clock + - description: m2p7 channel gate clock + - description: m2p8 channel gate clock + - description: m2p9 channel gate clock + + clock-names: + items: + - const: m2p0 + - const: m2p1 + - const: m2p2 + - const: m2p3 + - const: m2p4 + - const: m2p5 + - const: m2p6 + - const: m2p7 + - const: m2p8 + - const: m2p9 + + interrupts: + items: + - description: m2p0 channel interrupt + - description: m2p1 channel interrupt + - description: m2p2 channel interrupt + - description: m2p3 channel interrupt + - description: m2p4 channel interrupt + - description: m2p5 channel interrupt + - description: m2p6 channel interrupt + - description: m2p7 channel interrupt + - description: m2p8 channel interrupt + - description: m2p9 channel interrupt + + '#dma-cells': + const: 2 + description: | + The first cell is the unique device channel number as indicated by t= his + table for ep93xx: + + 0: I2S channel 1 + 1: I2S channel 2 (unused) + 2: AC97 channel 1 (unused) + 3: AC97 channel 2 (unused) + 4: AC97 channel 3 (unused) + 5: I2S channel 3 (unused) + 6: UART1 (unused) + 7: UART2 (unused) + 8: UART3 (unused) + 9: IRDA (unused) + + The second cell is the DMA direction line number: + + 1: Memory to device + 2: Device to memory + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, = <16>; + #dma-cells =3D <2>; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67D2C1850A9; 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Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Acked-by: Vinod Koul Signed-off-by: Nikita Shubin --- drivers/dma/ep93xx_dma.c | 239 ++++++++++++++++++++++++---= ---- include/linux/platform_data/dma-ep93xx.h | 6 + 2 files changed, 191 insertions(+), 54 deletions(-) diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index d6c60635e90d..17c8e2badee2 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include =20 @@ -104,6 +106,11 @@ #define DMA_MAX_CHAN_BYTES 0xffff #define DMA_MAX_CHAN_DESCRIPTORS 32 =20 +enum ep93xx_dma_type { + M2P_DMA, + M2M_DMA, +}; + struct ep93xx_dma_engine; static int ep93xx_dma_slave_config_write(struct dma_chan *chan, enum dma_transfer_direction dir, @@ -129,11 +136,17 @@ struct ep93xx_dma_desc { struct list_head node; }; =20 +struct ep93xx_dma_chan_cfg { + u8 port; + enum dma_transfer_direction dir; +}; + /** * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel * @chan: dmaengine API channel * @edma: pointer to the engine device * @regs: memory mapped registers + * @dma_cfg: channel number, direction * @irq: interrupt number of the channel * @clk: clock used by this channel * @tasklet: channel specific tasklet used for callbacks @@ -157,14 +170,12 @@ struct ep93xx_dma_desc { * descriptor in the chain. When a descriptor is moved to the @active queu= e, * the first and chained descriptors are flattened into a single list. * - * @chan.private holds pointer to &struct ep93xx_dma_data which contains - * necessary channel configuration information. For memcpy channels this m= ust - * be %NULL. */ struct ep93xx_dma_chan { struct dma_chan chan; const struct ep93xx_dma_engine *edma; void __iomem *regs; + struct ep93xx_dma_chan_cfg dma_cfg; int irq; struct clk *clk; struct tasklet_struct tasklet; @@ -216,6 +227,11 @@ struct ep93xx_dma_engine { struct ep93xx_dma_chan channels[] __counted_by(num_channels); }; =20 +struct ep93xx_edma_data { + u32 id; + size_t num_channels; +}; + static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac) { return &edmac->chan.dev->device; @@ -318,10 +334,9 @@ static void m2p_set_control(struct ep93xx_dma_chan *ed= mac, u32 control) =20 static int m2p_hw_setup(struct ep93xx_dma_chan *edmac) { - struct ep93xx_dma_data *data =3D edmac->chan.private; u32 control; =20 - writel(data->port & 0xf, edmac->regs + M2P_PPALLOC); + writel(edmac->dma_cfg.port & 0xf, edmac->regs + M2P_PPALLOC); =20 control =3D M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE | M2P_CONTROL_ENABLE; @@ -458,16 +473,15 @@ static int m2p_hw_interrupt(struct ep93xx_dma_chan *e= dmac) =20 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac) { - const struct ep93xx_dma_data *data =3D edmac->chan.private; u32 control =3D 0; =20 - if (!data) { + if (edmac->dma_cfg.dir =3D=3D DMA_MEM_TO_MEM) { /* This is memcpy channel, nothing to configure */ writel(control, edmac->regs + M2M_CONTROL); return 0; } =20 - switch (data->port) { + switch (edmac->dma_cfg.port) { case EP93XX_DMA_SSP: /* * This was found via experimenting - anything less than 5 @@ -477,7 +491,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac) control =3D (5 << M2M_CONTROL_PWSC_SHIFT); control |=3D M2M_CONTROL_NO_HDSK; =20 - if (data->direction =3D=3D DMA_MEM_TO_DEV) { + if (edmac->dma_cfg.dir =3D=3D DMA_MEM_TO_DEV) { control |=3D M2M_CONTROL_DAH; control |=3D M2M_CONTROL_TM_TX; control |=3D M2M_CONTROL_RSS_SSPTX; @@ -493,7 +507,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac) * This IDE part is totally untested. Values below are taken * from the EP93xx Users's Guide and might not be correct. */ - if (data->direction =3D=3D DMA_MEM_TO_DEV) { + if (edmac->dma_cfg.dir =3D=3D DMA_MEM_TO_DEV) { /* Worst case from the UG */ control =3D (3 << M2M_CONTROL_PWSC_SHIFT); control |=3D M2M_CONTROL_DAH; @@ -548,7 +562,6 @@ static void m2m_fill_desc(struct ep93xx_dma_chan *edmac) =20 static void m2m_hw_submit(struct ep93xx_dma_chan *edmac) { - struct ep93xx_dma_data *data =3D edmac->chan.private; u32 control =3D readl(edmac->regs + M2M_CONTROL); =20 /* @@ -574,7 +587,7 @@ static void m2m_hw_submit(struct ep93xx_dma_chan *edmac) control |=3D M2M_CONTROL_ENABLE; writel(control, edmac->regs + M2M_CONTROL); =20 - if (!data) { + if (edmac->dma_cfg.dir =3D=3D DMA_MEM_TO_MEM) { /* * For memcpy channels the software trigger must be asserted * in order to start the memcpy operation. @@ -636,7 +649,7 @@ static int m2m_hw_interrupt(struct ep93xx_dma_chan *edm= ac) */ if (ep93xx_dma_advance_active(edmac)) { m2m_fill_desc(edmac); - if (done && !edmac->chan.private) { + if (done && edmac->dma_cfg.dir =3D=3D DMA_MEM_TO_MEM) { /* Software trigger for memcpy channel */ control =3D readl(edmac->regs + M2M_CONTROL); control |=3D M2M_CONTROL_START; @@ -867,25 +880,22 @@ static dma_cookie_t ep93xx_dma_tx_submit(struct dma_a= sync_tx_descriptor *tx) static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan) { struct ep93xx_dma_chan *edmac =3D to_ep93xx_dma_chan(chan); - struct ep93xx_dma_data *data =3D chan->private; const char *name =3D dma_chan_name(chan); int ret, i; =20 /* Sanity check the channel parameters */ if (!edmac->edma->m2m) { - if (!data) + if (edmac->dma_cfg.port < EP93XX_DMA_I2S1 || + edmac->dma_cfg.port > EP93XX_DMA_IRDA) return -EINVAL; - if (data->port < EP93XX_DMA_I2S1 || - data->port > EP93XX_DMA_IRDA) - return -EINVAL; - if (data->direction !=3D ep93xx_dma_chan_direction(chan)) + if (edmac->dma_cfg.dir !=3D ep93xx_dma_chan_direction(chan)) return -EINVAL; } else { - if (data) { - switch (data->port) { + if (edmac->dma_cfg.dir !=3D DMA_MEM_TO_MEM) { + switch (edmac->dma_cfg.port) { case EP93XX_DMA_SSP: case EP93XX_DMA_IDE: - if (!is_slave_direction(data->direction)) + if (!is_slave_direction(edmac->dma_cfg.dir)) return -EINVAL; break; default: @@ -894,9 +904,6 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_c= han *chan) } } =20 - if (data && data->name) - name =3D data->name; - ret =3D clk_prepare_enable(edmac->clk); if (ret) return ret; @@ -1315,36 +1322,53 @@ static void ep93xx_dma_issue_pending(struct dma_cha= n *chan) ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan)); } =20 -static int __init ep93xx_dma_probe(struct platform_device *pdev) +static struct ep93xx_dma_engine *ep93xx_dma_of_probe(struct platform_devic= e *pdev) { - struct ep93xx_dma_platform_data *pdata =3D dev_get_platdata(&pdev->dev); + const struct ep93xx_edma_data *data; + struct device *dev =3D &pdev->dev; struct ep93xx_dma_engine *edma; struct dma_device *dma_dev; - int ret, i; + char dma_clk_name[5]; + int i; =20 - edma =3D kzalloc(struct_size(edma, channels, pdata->num_channels), GFP_KE= RNEL); + data =3D device_get_match_data(dev); + if (!data) + return ERR_PTR(dev_err_probe(dev, -ENODEV, "No device match found\n")); + + edma =3D devm_kzalloc(dev, struct_size(edma, channels, data->num_channels= ), + GFP_KERNEL); if (!edma) - return -ENOMEM; + return ERR_PTR(-ENOMEM); =20 + edma->m2m =3D data->id; + edma->num_channels =3D data->num_channels; dma_dev =3D &edma->dma_dev; - edma->m2m =3D platform_get_device_id(pdev)->driver_data; - edma->num_channels =3D pdata->num_channels; =20 INIT_LIST_HEAD(&dma_dev->channels); - for (i =3D 0; i < pdata->num_channels; i++) { - const struct ep93xx_dma_chan_data *cdata =3D &pdata->channels[i]; + for (i =3D 0; i < edma->num_channels; i++) { struct ep93xx_dma_chan *edmac =3D &edma->channels[i]; =20 edmac->chan.device =3D dma_dev; - edmac->regs =3D cdata->base; - edmac->irq =3D cdata->irq; + edmac->regs =3D devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(edmac->regs)) + return edmac->regs; + + edmac->irq =3D fwnode_irq_get(dev_fwnode(dev), i); + if (edmac->irq < 0) + return ERR_PTR(edmac->irq); + edmac->edma =3D edma; =20 - edmac->clk =3D clk_get(NULL, cdata->name); + if (edma->m2m) + sprintf(dma_clk_name, "m2m%u", i); + else + sprintf(dma_clk_name, "m2p%u", i); + + edmac->clk =3D devm_clk_get(dev, dma_clk_name); if (IS_ERR(edmac->clk)) { - dev_warn(&pdev->dev, "failed to get clock for %s\n", - cdata->name); - continue; + dev_err_probe(dev, PTR_ERR(edmac->clk), + "no %s clock found\n", dma_clk_name); + return ERR_CAST(edmac->clk); } =20 spin_lock_init(&edmac->lock); @@ -1357,6 +1381,90 @@ static int __init ep93xx_dma_probe(struct platform_d= evice *pdev) &dma_dev->channels); } =20 + return edma; +} + +static bool ep93xx_m2p_dma_filter(struct dma_chan *chan, void *filter_para= m) +{ + struct ep93xx_dma_chan *echan =3D to_ep93xx_dma_chan(chan); + struct ep93xx_dma_chan_cfg *cfg =3D filter_param; + + if (cfg->dir !=3D ep93xx_dma_chan_direction(chan)) + return false; + + echan->dma_cfg =3D *cfg; + return true; +} + +static struct dma_chan *ep93xx_m2p_dma_of_xlate(struct of_phandle_args *dm= a_spec, + struct of_dma *ofdma) +{ + struct ep93xx_dma_engine *edma =3D ofdma->of_dma_data; + dma_cap_mask_t mask =3D edma->dma_dev.cap_mask; + struct ep93xx_dma_chan_cfg dma_cfg; + u8 port =3D dma_spec->args[0]; + u8 direction =3D dma_spec->args[1]; + + if (port > EP93XX_DMA_IRDA) + return NULL; + + if (!is_slave_direction(direction)) + return NULL; + + dma_cfg.port =3D port; + dma_cfg.dir =3D direction; + + return __dma_request_channel(&mask, ep93xx_m2p_dma_filter, &dma_cfg, ofdm= a->of_node); +} + +static bool ep93xx_m2m_dma_filter(struct dma_chan *chan, void *filter_para= m) +{ + struct ep93xx_dma_chan *echan =3D to_ep93xx_dma_chan(chan); + struct ep93xx_dma_chan_cfg *cfg =3D filter_param; + + echan->dma_cfg =3D *cfg; + + return true; +} + +static struct dma_chan *ep93xx_m2m_dma_of_xlate(struct of_phandle_args *dm= a_spec, + struct of_dma *ofdma) +{ + struct ep93xx_dma_engine *edma =3D ofdma->of_dma_data; + dma_cap_mask_t mask =3D edma->dma_dev.cap_mask; + struct ep93xx_dma_chan_cfg dma_cfg; + u8 port =3D dma_spec->args[0]; + u8 direction =3D dma_spec->args[1]; + + if (!is_slave_direction(direction)) + return NULL; + + switch (port) { + case EP93XX_DMA_SSP: + case EP93XX_DMA_IDE: + break; + default: + return NULL; + } + + dma_cfg.port =3D port; + dma_cfg.dir =3D direction; + + return __dma_request_channel(&mask, ep93xx_m2m_dma_filter, &dma_cfg, ofdm= a->of_node); +} + +static int ep93xx_dma_probe(struct platform_device *pdev) +{ + struct ep93xx_dma_engine *edma; + struct dma_device *dma_dev; + int ret; + + edma =3D ep93xx_dma_of_probe(pdev); + if (!edma) + return PTR_ERR(edma); + + dma_dev =3D &edma->dma_dev; + dma_cap_zero(dma_dev->cap_mask); dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask); @@ -1393,21 +1501,46 @@ static int __init ep93xx_dma_probe(struct platform_= device *pdev) } =20 ret =3D dma_async_device_register(dma_dev); - if (unlikely(ret)) { - for (i =3D 0; i < edma->num_channels; i++) { - struct ep93xx_dma_chan *edmac =3D &edma->channels[i]; - if (!IS_ERR_OR_NULL(edmac->clk)) - clk_put(edmac->clk); - } - kfree(edma); + if (ret) + return ret; + + if (edma->m2m) { + ret =3D of_dma_controller_register(pdev->dev.of_node, ep93xx_m2m_dma_of_= xlate, + edma); } else { - dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n", - edma->m2m ? "M" : "P"); + ret =3D of_dma_controller_register(pdev->dev.of_node, ep93xx_m2p_dma_of_= xlate, + edma); } + if (ret) + goto err_dma_unregister; + + dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n", edma->m2m ? "M" : "P"); + + return 0; + +err_dma_unregister: + dma_async_device_unregister(dma_dev); =20 return ret; } =20 +static const struct ep93xx_edma_data edma_m2p =3D { + .id =3D M2P_DMA, + .num_channels =3D 10, +}; + +static const struct ep93xx_edma_data edma_m2m =3D { + .id =3D M2M_DMA, + .num_channels =3D 2, +}; + +static const struct of_device_id ep93xx_dma_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-dma-m2p", .data =3D &edma_m2p }, + { .compatible =3D "cirrus,ep9301-dma-m2m", .data =3D &edma_m2m }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_dma_of_ids); + static const struct platform_device_id ep93xx_dma_driver_ids[] =3D { { "ep93xx-dma-m2p", 0 }, { "ep93xx-dma-m2m", 1 }, @@ -1417,15 +1550,13 @@ static const struct platform_device_id ep93xx_dma_d= river_ids[] =3D { static struct platform_driver ep93xx_dma_driver =3D { .driver =3D { .name =3D "ep93xx-dma", + .of_match_table =3D ep93xx_dma_of_ids, }, .id_table =3D ep93xx_dma_driver_ids, + .probe =3D ep93xx_dma_probe, }; =20 -static int __init ep93xx_dma_module_init(void) -{ - return platform_driver_probe(&ep93xx_dma_driver, ep93xx_dma_probe); -} -subsys_initcall(ep93xx_dma_module_init); +module_platform_driver(ep93xx_dma_driver); =20 MODULE_AUTHOR("Mika Westerberg "); MODULE_DESCRIPTION("EP93xx DMA driver"); diff --git a/include/linux/platform_data/dma-ep93xx.h b/include/linux/platf= orm_data/dma-ep93xx.h index eb9805bb3fe8..9ec5cdd5a1eb 100644 --- a/include/linux/platform_data/dma-ep93xx.h +++ b/include/linux/platform_data/dma-ep93xx.h @@ -3,8 +3,11 @@ #define __ASM_ARCH_DMA_H =20 #include +#include #include #include +#include +#include =20 /* * M2P channels. @@ -70,6 +73,9 @@ struct ep93xx_dma_platform_data { =20 static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) { + if (device_is_compatible(chan->device->dev, "cirrus,ep9301-dma-m2p")) + return true; + return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); } =20 --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84C611850B9; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-10-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nikita Shubin , Alexander Sverdlin Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1622; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=ms3IjWYaELf8kHC/xQEvZjvjU7YonAObO6Tdf+8gNec=; b=rPf2GwjEnDK/qWoOo9zaMyW+ZhLhWJ1n4WTd4UaWksjHNhCeYmBwfVmXDbhn4tvIFGCrbEkY3HJh jKhUDq+0A2B4IBSS9YRRUDqK6VjxlJkSsgiFCsw9C+5I8me4or33 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add device tree bindings for the Cirrus Logic EP93xx watchdog block used in these SoCs. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- .../bindings/watchdog/cirrus,ep9301-wdt.yaml | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.y= aml b/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.yaml new file mode 100644 index 000000000000..5dbe891c70c6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/cirrus,ep9301-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx Watchdog Timer + +maintainers: + - Nikita Shubin + - Alexander Sverdlin + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-wdt + - items: + - enum: + - cirrus,ep9302-wdt + - cirrus,ep9307-wdt + - cirrus,ep9312-wdt + - cirrus,ep9315-wdt + - const: cirrus,ep9301-wdt + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7F32185E4D; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=Uc7i81dzfExrTVRTgOJhxoTbnoRLSmFZi+LDIQuw439Fq3MN2w99mLmmf9Vhwk/SWb0ILxjpbPY3qblgTyPYZsjY+5VcGkHqGXw8E/vuCDTZQlL0ugJFU5bVjk7E3JwVurDLjDP3c5iXXTtgAgDyEyz/8kcHZyDGdO5Y+5halmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; c=relaxed/simple; bh=p7ruUPyc+63NALcCZNunH+Nk2cdQEW4DXh1uDsweETM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eQs/dZ7AxemXVODwvdLzSaZxrNb5ecxW7NnerSWABvjxV5WX2oan26NAlblDKH76pq4WY9dIY8hzJwqd0Xf5EjV5AfJOmYU9ker3KB3DUMh2YExK9GhJ1ZxVYOq9wbfXW1e70RutBi+J6SzSIRcm+BdNkQgojT1Wzv0BzPt3+JI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YXDY8A4v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YXDY8A4v" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6A372C4AF5F; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032803; bh=p7ruUPyc+63NALcCZNunH+Nk2cdQEW4DXh1uDsweETM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YXDY8A4v8CWrlM/wcJ6U4xqxigEHKwEVvYXDAnnVirJxOmyg5YBr4otbXM2QKT45K 8lB99ii9WpYNdMS0c+AMqY21dyrZSh02Z/WwC3l9VQpM+p00QDx4rtWVQrE6NRyhRq hSewgejeHJJgbgkjAdOfKjVkw4sriWv3YRyFj2GBu5nNsKhBlVl8KI6hjEXwSnCXBk JwwLs8gPGI2vYwaBIihy+7so3EHoddraGo2NGqtxE35EUVgJ6A5BsYQ8/qQrpLQaSu qRhLWuAnTvhxqsmanGiwnYTHCq4U/jj4s+kW1rZJyN5UVt3xkA9afOFcXpwlbtUFzO P9EFthGZ2eMVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E53CC2BD09; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:15 +0300 Subject: [PATCH v11 11/38] watchdog: ep93xx: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-11-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Wim Van Sebroeck , Guenter Roeck Cc: linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1193; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=JD3ei7UZOSn3iRCJWHAn8GIoBZ2EOdmGr+0MVn+KIfc=; b=D5JPJUXQh2OnL984T2HXAEWwZRYpQrJNWo7xm1De0vO5VIR/iBRhk2MVttfZCoyqbFteLyVjtSq8 YVJ8dcXCBh/RNbSyg5i2rvNrDfzxKJq8Wz9dba8HT8Sh0mZSh0gd X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add OF ID match table. Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin Reviewed-by: Guenter Roeck Reviewed-by: Andy Shevchenko --- drivers/watchdog/ep93xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index 59dfd7f6bf0b..af89b7bb8f66 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -19,6 +19,7 @@ */ =20 #include +#include #include #include #include @@ -127,9 +128,16 @@ static int ep93xx_wdt_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_wdt_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-wdt" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_wdt_of_ids); + static struct platform_driver ep93xx_wdt_driver =3D { .driver =3D { .name =3D "ep93xx-wdt", + .of_match_table =3D ep93xx_wdt_of_ids, }, .probe =3D ep93xx_wdt_probe, }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3B64185631; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=X0BeXKSZt2aU2vIqDpe4Drq83EuOrNfHbd3ZcvbMoolXQlkSrwFWbddEW1MJTOGnH4soh4d7LM3vx5/lmRyrTJKb/97Wa8/umZmLXsOEFH/iymNdN7buUVzYRBZrHZB/pKZQxrt0ogF6Xjk9GtQhX15PIvcJcjvFmKVpxGNC6WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; c=relaxed/simple; bh=3Q2bRQKoQu0LqnylJP2cSZjMQXfgAIE/N3cWrJixn1M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gV5EYsMHo9iipXnOIifG/Rzx5QLZBQSY+85dYzfKTW2eLWDU3LBFPelM0SGtO4uFyPfd/v9jNQMUGwqAh5uJmf9tbQd/havfyITRE0T89PhrtSV7LXRk/84F7HcVZh/9q/yZV4cF006Nt/PcCJHhfHNwI+7jzABhTu8h3ZoevUI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bhvnOXtP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bhvnOXtP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7CBDBC4AF48; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032803; bh=3Q2bRQKoQu0LqnylJP2cSZjMQXfgAIE/N3cWrJixn1M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bhvnOXtPe2V+0ZE6xhkclKdKucwzv0M9Wem0d7QYueCK543uzMexHXjjHjda5GflE ShoSwSe+2uJbUdqPyBR6AaGiwcLveSjx6PQQW6q+hE8lcIKZIJ+GPF5Hj/WQms+hTT 93TRPk2K1DDcgleifljDiKhC9ffdmFE5NUEtxVztQ3hzHHegGO8e1JhQ8cLRbJrRW/ 2s79UGnm/39nCYoUl5iOtXFx3mrthKfVW05s1ITOdLVKN7YYbNv57j2x2IN8SW50z8 zolK1FuU6+5JfnzA4TUZok7GfmHmHUDG6QYfca7AA5g0aafX6T46A6m7mAF7mRt8T0 ua9K0wXbA+14w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74C29C3DA4D; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:16 +0300 Subject: [PATCH v11 12/38] dt-bindings: pwm: Add Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-12-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Sverdlin , Nikita Shubin Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1848; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=z+2yOwm4hvQxzJhJWQahTMtiq2gz+415iGkW4eGQ8Eg=; b=lg/mg2q13y006104VQFi6zPTrOkSBNnSHGgpmfx2fsZOMNar6wn+joch6V/RrtHNgNOhNhdmopWT Ck5NlT7CCk4ng4MbUZvPpEjBSA1yRP57OrdrK77IZrAbaXV3kAQG X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ep93xx SoC PWM. Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml | 53 ++++++++++++++++++= ++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml b= /Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml new file mode 100644 index 000000000000..903210ef9c31 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/cirrus,ep9301-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx PWM controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-pwm + - items: + - enum: + - cirrus,ep9302-pwm + - cirrus,ep9307-pwm + - cirrus,ep9312-pwm + - cirrus,ep9315-pwm + - const: cirrus,ep9301-pwm + + reg: + maxItems: 1 + + clocks: + items: + - description: SoC PWM clock + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; 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Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:17 +0300 Subject: [PATCH v11 13/38] pwm: ep93xx: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-13-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Andy Shevchenko X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1236; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=ct0L8elpTvHj/aUU/OBJY6iv8PSAIzqZyzV/Ce2gcnk=; b=IurMjiG3ORAMJ24hvQXeM7cfSyoy0LEDTkoAD6kJXeH9LnHe3505zdi92/DRRIG6cQT4ZKw9rsD5 cV+CUPIPCucaBKIbxuldcywBbyMTmxaUWhvBYW4f5aGWkGlKcVCJ X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add OF ID match table. Signed-off-by: Nikita Shubin Reviewed-by: Uwe Kleine-K=C3=B6nig Reviewed-by: Andy Shevchenko Reviewed-by: Andy Shevchenko Acked-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index 666f2954133c..67c3fdbf7ae3 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -17,6 +17,7 @@ */ =20 #include +#include #include #include #include @@ -188,9 +189,16 @@ static int ep93xx_pwm_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_pwm_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-pwm" }, + { /* sentinel */} +}; +MODULE_DEVICE_TABLE(of, ep93xx_pwm_of_ids); + static struct platform_driver ep93xx_pwm_driver =3D { .driver =3D { .name =3D "ep93xx-pwm", + .of_match_table =3D ep93xx_pwm_of_ids, }, .probe =3D ep93xx_pwm_probe, }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CABBC185E46; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=O1ZWk4xnaTMJgImYWPsA6XHo5Zbqbqi08Enfu2xpvroo8FGfeDtB1clJ/4a/V35Z5EvlL+cX/HrWU/mq8I5TdLMHqakEsb45lpE1f7lK9UGSWFRDXrbyK0CBUDCEf6kWcRxNzlB85HlTkotCMaWeIivvbEswHjnTYZMJWORWRqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; c=relaxed/simple; bh=DG6Gyo/AhYeDkc08pgAbNNL+jl66p9ctVC7NLxEKR68=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s/ZdB3LoEUmG2A+wgV5DHuI40X1JLfZd2ziHy2JlgCJKfaTSmf77sjQPpIj3bEGIur4SJzcu1rmM/XZhKjqHAEGFB7I8qT4EJUmaYQWY6bWRX18VAH7h2e6DD0L3xEWhj9TASFwc7yPONFCD8AemluuhbPtlfPY4sQhpJP+28AQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AJHSb8Ey; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AJHSb8Ey" Received: by smtp.kernel.org (Postfix) with ESMTPS id A0732C4DDEB; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032803; bh=DG6Gyo/AhYeDkc08pgAbNNL+jl66p9ctVC7NLxEKR68=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AJHSb8EyggidIExL7CJdm9PIp1B+MmhYB4MkRSBEoFcRYQ4TOOv5Haqt+5CxKDOb9 4qK53ySEfV0+ajhV7M6QCqIkuCRS3BN+CoC7FrzPaHOeEEkBuqIQXVbGrGVprzhHuX V5U53EKjkN41yXKn1LhKGGun3aa9ndzbjwOMEvCra05BLzeU7+ylvFbhct3aLKagod NAcLBxGGToEIIE6xtxt4CH33GYm0A3jMkrzdpwehAtIamdIWNjpAnKKmB2xZtr2xv7 Xb56sQ+tUDeQLaPVI4t2fHCQxwHJXL035a5KAJ41LR+3JU7h4CNU7FTZVozLfoDNuL THO/ESTh2IMUw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94BA8C3DA56; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:18 +0300 Subject: [PATCH v11 14/38] dt-bindings: spi: Add Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-14-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Sverdlin , Nikita Shubin Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=2297; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=jJL2qB0kTVm0ECXQdY2vGGR9TsGC8ONTPNp8ZLPMM2E=; b=slWoATJ3k/YWKns0wVMGexGJOeXETO57mJOJt4eTQpI0sWs3mkDmARDsF8/HibUrRmewZ7P5i7Kh +LDZKyKCDbm1Go/oCBni6QT5yR9LgfjwqoJ5jslunlLOwmg8T6Ya X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ep93xx SoC SPI. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski Reviewed-by: Mark Brown --- .../devicetree/bindings/spi/cirrus,ep9301-spi.yaml | 70 ++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/cirrus,ep9301-spi.yaml b= /Documentation/devicetree/bindings/spi/cirrus,ep9301-spi.yaml new file mode 100644 index 000000000000..73980a27dc00 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cirrus,ep9301-spi.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cirrus,ep9301-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx SoC SPI controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-spi + - items: + - enum: + - cirrus,ep9302-spi + - cirrus,ep9307-spi + - cirrus,ep9312-spi + - cirrus,ep9315-spi + - const: cirrus,ep9301-spi + + reg: + items: + - description: SPI registers region + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI Controller reference clock source + + dmas: + items: + - description: rx DMA channel + - description: tx DMA channel + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + #include + spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + reg =3D <0x808a0000 0x18>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&syscon EP93XX_CLK_SPI>; + dmas =3D <&dma1 10 2>, <&dma1 10 1>; + dma-names =3D "rx", "tx"; + cs-gpios =3D <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEEA7185E49; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032803; cv=none; b=lbMyOFBZAhBe6pR8Eeg2BU7D6fRTF4VrBmD9M5xw/KWR3CUSnk+eA2R0w9m6ZbbX+5/5NMm2p8FneZ6LNB0g3B0nCFJXuAJnNBE1zuOrTLwgSwgJOw6eSKX/DHQNN/8GkKMnXBqrQL/wH7OUPkyLW+HXmoUB6yN+7D8B3p26+j0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:19 +0300 Subject: [PATCH v11 15/38] spi: ep93xx: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-15-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=4901; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=Bt1o2cb87iUEqTTj1qSqH0uuj7VeyHE3n45reTOPXeo=; b=d7c3woyS8gs8Tvw4ci2a7XzOMinkmEZ1DXwN7eqjVP972Ci+QgpoE087TcLApra+L32ncRD42NiY yROq94vXA8c6Fzzi9yChP5t7PtsuTX7PTsZVRQG4A5eai8rwd/8N X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin - add OF ID match table - add device tree DMA request, so we can probe defer, in case DMA is not ready yet - drop DMA platform code Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij Tested-by: Alexander Sverdlin Acked-by: Alexander Sverdlin Reviewed-by: Mark Brown --- drivers/spi/spi-ep93xx.c | 66 +++++++++++++++++---------------------------= ---- 1 file changed, 23 insertions(+), 43 deletions(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index a1d60e51c053..ffbe0d522bce 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -18,18 +18,18 @@ #include #include #include +#include +#include #include #include #include #include +#include #include #include #include #include =20 -#include -#include - #define SSPCR0 0x0000 #define SSPCR0_SPO BIT(6) #define SSPCR0_SPH BIT(7) @@ -92,8 +92,6 @@ struct ep93xx_spi { size_t fifo_level; struct dma_chan *dma_rx; struct dma_chan *dma_tx; - struct ep93xx_dma_data dma_rx_data; - struct ep93xx_dma_data dma_tx_data; struct sg_table rx_sgt; struct sg_table tx_sgt; void *zeropage; @@ -575,46 +573,23 @@ static int ep93xx_spi_unprepare_hardware(struct spi_c= ontroller *host) return 0; } =20 -static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_para= m) +static int ep93xx_spi_setup_dma(struct device *dev, struct ep93xx_spi *esp= i) { - if (ep93xx_dma_chan_is_m2p(chan)) - return false; - - chan->private =3D filter_param; - return true; -} - -static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi) -{ - dma_cap_mask_t mask; int ret; =20 espi->zeropage =3D (void *)get_zeroed_page(GFP_KERNEL); if (!espi->zeropage) return -ENOMEM; =20 - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); - - espi->dma_rx_data.port =3D EP93XX_DMA_SSP; - espi->dma_rx_data.direction =3D DMA_DEV_TO_MEM; - espi->dma_rx_data.name =3D "ep93xx-spi-rx"; - - espi->dma_rx =3D dma_request_channel(mask, ep93xx_spi_dma_filter, - &espi->dma_rx_data); - if (!espi->dma_rx) { - ret =3D -ENODEV; + espi->dma_rx =3D dma_request_chan(dev, "rx"); + if (IS_ERR(espi->dma_rx)) { + ret =3D dev_err_probe(dev, PTR_ERR(espi->dma_rx), "rx DMA setup failed"); goto fail_free_page; } =20 - espi->dma_tx_data.port =3D EP93XX_DMA_SSP; - espi->dma_tx_data.direction =3D DMA_MEM_TO_DEV; - espi->dma_tx_data.name =3D "ep93xx-spi-tx"; - - espi->dma_tx =3D dma_request_channel(mask, ep93xx_spi_dma_filter, - &espi->dma_tx_data); - if (!espi->dma_tx) { - ret =3D -ENODEV; + espi->dma_tx =3D dma_request_chan(dev, "tx"); + if (IS_ERR(espi->dma_tx)) { + ret =3D dev_err_probe(dev, PTR_ERR(espi->dma_tx), "tx DMA setup failed"); goto fail_release_rx; } =20 @@ -647,18 +622,11 @@ static void ep93xx_spi_release_dma(struct ep93xx_spi = *espi) static int ep93xx_spi_probe(struct platform_device *pdev) { struct spi_controller *host; - struct ep93xx_spi_info *info; struct ep93xx_spi *espi; struct resource *res; int irq; int error; =20 - info =3D dev_get_platdata(&pdev->dev); - if (!info) { - dev_err(&pdev->dev, "missing platform data\n"); - return -EINVAL; - } - irq =3D platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -713,12 +681,17 @@ static int ep93xx_spi_probe(struct platform_device *p= dev) goto fail_release_host; } =20 - if (info->use_dma && ep93xx_spi_setup_dma(espi)) + error =3D ep93xx_spi_setup_dma(&pdev->dev, espi); + if (error =3D=3D -EPROBE_DEFER) + goto fail_release_host; + + if (error) dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); =20 /* make sure that the hardware is disabled */ writel(0, espi->mmio + SSPCR1); =20 + device_set_node(&host->dev, dev_fwnode(&pdev->dev)); error =3D devm_spi_register_controller(&pdev->dev, host); if (error) { dev_err(&pdev->dev, "failed to register SPI host\n"); @@ -746,9 +719,16 @@ static void ep93xx_spi_remove(struct platform_device *= pdev) ep93xx_spi_release_dma(espi); } =20 +static const struct of_device_id ep93xx_spi_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-spi" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids); + static struct platform_driver ep93xx_spi_driver =3D { .driver =3D { .name =3D "ep93xx-spi", + .of_match_table =3D ep93xx_spi_of_ids, }, .probe =3D ep93xx_spi_probe, .remove_new =3D ep93xx_spi_remove, --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09AC4185E60; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=g0BcCqCHaG8P8535ABqeDo8ia5hgQJu8NJelthdVgTOYlYC9/RHfDw5f2rxg6QfUV3mqOzViHryTMsUTY2xw110YNxQoxpAaXTPiWA/N37/BmqAwc0lSurWmWD3qi+x0aN8ykVvZaNT1SbF26Bt3cJG8rMXHaAQlOOzLDbdToPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=4P6bcFjMz2Z81KccelmzzJW3x4QXkAmbT0oSpWl6AJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Px5kbsKS4uZDC215x5NZGzu2bXS99qQ4IAO+Ifx+M0S/7Cbmci2vldiRMLbtP/iBwlZ1K8wLaxVXJqKZiZ93Qc7w83pCdF9g62J5o38QCJFCq/I6sHZMeQI5m9IXJlO7RTMnLBmt7jA6Pz7OMBO+fmHjtBBog6MikG5xKgGR52g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ljQrMVSu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ljQrMVSu" Received: by smtp.kernel.org (Postfix) with ESMTPS id BECE2C4AF19; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032803; bh=4P6bcFjMz2Z81KccelmzzJW3x4QXkAmbT0oSpWl6AJs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ljQrMVSuMnOlbkKTDtx+Val/d2JWs1bX3R1owqGK3poxk9OJAmCMsXbYzkbWOhnOb zgToTNPxVy7YIbmJWiiJDDVKRJlEmkk4PiAoxRKDVmLfJs7a61TiCEpRVqz0n6CJ9H oU3/fV5EZ6REiZXHCxks2cjN1n+4eh5ifwbCmMvo5ZNUtzNGq6ksSEfYndqetj97QK /YmBU1pT5XavaGGCADf9Si7s7cgWLVyyDt1XH6Rrw9r1qYUfj698CBGgOWjJtaycx1 L0szgIE0Mv7L/73xCMfB2H+pNzgV+fZoX97bPzMX/cLvb+vOJyfa6sMkvlzGcMkVq8 ipiwrqQNNKuoA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B696CC3DA50; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:20 +0300 Subject: [PATCH v11 16/38] dt-bindings: net: Add Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-16-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Sverdlin , Nikita Shubin Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=2030; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=2EI3oik4KHOxom6rjRW5fPr9iZissgfzSJoa2Vw9jd0=; b=i05NcwoUS8bi5oc+5uiGsb54nZME5zijYoJx3mLqg9hD+idgvWpMbJxFFsiM4bUcTSAzfn4OaXPJ rl/p5PWNALaW5ia3bC76xbkQKl9tpWlOYzSs9uCqFQQcfWXinRVr X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ep93xx SoC Ethernet Controller. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/cirrus,ep9301-eth.yaml | 59 ++++++++++++++++++= ++++ 1 file changed, 59 insertions(+) diff --git a/Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml b= /Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml new file mode 100644 index 000000000000..ad0915307095 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx SoC Ethernet Controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-eth + - items: + - enum: + - cirrus,ep9302-eth + - cirrus,ep9307-eth + - cirrus,ep9312-eth + - cirrus,ep9315-eth + - const: cirrus,ep9301-eth + + reg: + items: + - description: The physical base address and size of IO range + + interrupts: + items: + - description: Combined signal for various interrupt events + + phy-handle: true + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: optional node for embedded MDIO controller + +required: + - compatible + - reg + - interrupts + - phy-handle + +additionalProperties: false + +examples: + - | + ethernet@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + phy-handle =3D <&phy0>; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 839ED185E7F; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=Y00tHAaSV8PEnJvE7bFfe0Z/4e/Fxj++9ILf894/uvPL5xBFdubk6KLjExoHAwBOpNyzn7BxHxx6TWYDAJo1JMrekBCzeTB4E+oWeJwDscdXFPhpw0QFAWvMYr2L7NJvUJSwhRqcyMHGlfdpQsRQdtDncnnyvAnVX06Svv5o2cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=hu+7JHtL6Prd6V/S2TJxZvc5nnlMUcfi+uYAd+zwbqo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M4lsb0r7FCxQSsXBMuUG9a69qLIpqoP3E30/TvazF031YYkad3twv0OgnzYfK2hOez5FOt3Lzo5xamwsK5jcc2mtVAsc883fE7eVf+4Nmv7PZZNFFBK+Y85S4bT2WNwA1PNrQHo8nPyAI34oHLWSA1YwvjtGMoiPkVLMdCHn8GQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m5y9Gi9N; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m5y9Gi9N" Received: by smtp.kernel.org (Postfix) with ESMTPS id D36C3C4DE07; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032803; bh=hu+7JHtL6Prd6V/S2TJxZvc5nnlMUcfi+uYAd+zwbqo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=m5y9Gi9NoHE9iAcMYXWAerQd7GwouDwHIAA/bSsxf7m1cMcDZ7FIgaU4KENubXCjp KW01Vx/KE/Cvy5HxNU67NROWO7k9Ay4e5wdAkYRCd+PskOFKRbFW6FHTvKxtEiQMIe jwwzCO3bdX+P4PhCL4PtQCepXJfNvdZj9fdfb9QvNVIIWXouNgov8B8wFFCJShbUmM 26V4VeNjxOWbdTBK6AF1fuRWp/aoyqcGJx5VD14LR2OXT9nkD4WExsqwT1Be0t1yBh X0MBpNhexEfuZdBlnMlTszTJvzghW2Xfoo2xRx72B+CQfDvtkeCekR7haQj74bY+EX BbgeP+0ajWgQw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8896C2BD09; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:21 +0300 Subject: [PATCH v11 17/38] net: cirrus: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-17-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=4277; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=b1GOTD5HubzYgxiOB7lYJxNswjw8j/5q0+HrSptbhew=; b=rKabVJ2eVAk5cAgCA0iDMlooaUUDvBHdd9owdLmcit71rrco09VSAxRewR9Sddc4di01P3+XGmus GH3En/IxBnWAKgdyOQh0k5hpONEAaIsyEga8q4Sns4B8lPrZViVE X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin - add OF ID match table - get phy_id from the device tree, as part of mdio - copy_addr is now always used, as there is no SoC/board that aren't - dropped platform header Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij --- drivers/net/ethernet/cirrus/ep93xx_eth.c | 63 ++++++++++++++++------------= ---- 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/etherne= t/cirrus/ep93xx_eth.c index 1f495cfd7959..2523d9c9d1b8 100644 --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c @@ -16,13 +16,12 @@ #include #include #include +#include #include #include #include #include =20 -#include - #define DRV_MODULE_NAME "ep93xx-eth" =20 #define RX_QUEUE_ENTRIES 64 @@ -738,25 +737,6 @@ static const struct net_device_ops ep93xx_netdev_ops = =3D { .ndo_set_mac_address =3D eth_mac_addr, }; =20 -static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data) -{ - struct net_device *dev; - - dev =3D alloc_etherdev(sizeof(struct ep93xx_priv)); - if (dev =3D=3D NULL) - return NULL; - - eth_hw_addr_set(dev, data->dev_addr); - - dev->ethtool_ops =3D &ep93xx_ethtool_ops; - dev->netdev_ops =3D &ep93xx_netdev_ops; - - dev->features |=3D NETIF_F_SG | NETIF_F_HW_CSUM; - - return dev; -} - - static void ep93xx_eth_remove(struct platform_device *pdev) { struct net_device *dev; @@ -786,27 +766,47 @@ static void ep93xx_eth_remove(struct platform_device = *pdev) =20 static int ep93xx_eth_probe(struct platform_device *pdev) { - struct ep93xx_eth_data *data; struct net_device *dev; struct ep93xx_priv *ep; struct resource *mem; + void __iomem *base_addr; + struct device_node *np; + u32 phy_id; int irq; int err; =20 if (pdev =3D=3D NULL) return -ENODEV; - data =3D dev_get_platdata(&pdev->dev); =20 mem =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); irq =3D platform_get_irq(pdev, 0); if (!mem || irq < 0) return -ENXIO; =20 - dev =3D ep93xx_dev_alloc(data); + base_addr =3D ioremap(mem->start, resource_size(mem)); + if (!base_addr) + return dev_err_probe(&pdev->dev, -EIO, "Failed to ioremap ethernet regis= ters\n"); + + np =3D of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); + if (!np) + return dev_err_probe(&pdev->dev, -ENODEV, "Please provide \"phy-handle\"= \n"); + + err =3D of_property_read_u32(np, "reg", &phy_id); + of_node_put(np); + if (err) + return dev_err_probe(&pdev->dev, -ENOENT, "Failed to locate \"phy_id\"\n= "); + + dev =3D alloc_etherdev(sizeof(struct ep93xx_priv)); if (dev =3D=3D NULL) { err =3D -ENOMEM; goto err_out; } + + eth_hw_addr_set(dev, base_addr + 0x50); + dev->ethtool_ops =3D &ep93xx_ethtool_ops; + dev->netdev_ops =3D &ep93xx_netdev_ops; + dev->features |=3D NETIF_F_SG | NETIF_F_HW_CSUM; + ep =3D netdev_priv(dev); ep->dev =3D dev; SET_NETDEV_DEV(dev, &pdev->dev); @@ -822,15 +822,10 @@ static int ep93xx_eth_probe(struct platform_device *p= dev) goto err_out; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-18-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nikita Shubin Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1633; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=7r17/fFhBG5Dh5YlKHGbUghicWp/sbQ+SRw1TNILVrU=; b=1f7TqxagAEcOnV9Y0GsX1+c0L3Cxrj1SA5IscId+56GgZNgZ/hrN0mObprBRCYT56yGBqi5pxK06 9CWNRhQMDNvh5fP6ecH+A0CEYE7ajMGxNg2Z6TEXvXpiVIvLNLwI X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ts7200 NAND Controller. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mtd/technologic,nand.yaml | 45 ++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/technologic,nand.yaml b/= Documentation/devicetree/bindings/mtd/technologic,nand.yaml new file mode 100644 index 000000000000..f9d87c46094b --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/technologic,nand.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/technologic,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems NAND controller + +maintainers: + - Nikita Shubin + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + oneOf: + - const: technologic,ts7200-nand + - items: + - enum: + - technologic,ts7300-nand + - technologic,ts7260-nand + - technologic,ts7250-nand + - const: technologic,ts7200-nand + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + nand@0 { + reg =3D <0>; + }; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DAFB186286 for ; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=VndUrXMKq4jAEjHBHn76tu6Fz9mrFvy5KUCLLAsEw2L7dLCw0TeK0JXCc1vH6KCsZ/lFAsoTi04kThosxSQ/qfUsXZY2C9fUPVUWwFBIDRBulaKnP5TOe2iM+owK8mv9YIek3xPlUd2ZLvT8fZCouUEgJYzcgnebSJT/z/8lJqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=9BeMjQzY2D1n5KMEIdhe/MnEyijbRClm3qeQuf/mLsg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=afF3i2rl3phLlTYKRw+V4vNnFYChdK3/VVDl5eQycf68pqRuceLko/+nOO5jnLYmEn24XH+L08Dksmy+s5SBtMk1PG7FDtfW23Nso7vrL8Af14xpgyHwzryFZQyPfjdEK0YQvIROza0wtis5BC8rojxtj0vUsMKD/OJS8YtKMoI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kLFkJl2Y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kLFkJl2Y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0439AC4AF12; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032804; bh=9BeMjQzY2D1n5KMEIdhe/MnEyijbRClm3qeQuf/mLsg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kLFkJl2YoJkPlQdbVr0dJohxtyAGv3v8LdxTg/XjRq7dMmNoSLqWMJ6Arv8bPMb6F l0N0YTQOhC315jUkpTLkFPCyqZwvRQooOSiAZ6ue/EQRVAO//v4mea7eD0+Hc7eng9 +qqYAjhXBsow4e/6/cWDRuHsffDuNJ3DiC22jdJ6suNN0A5VHI4fQlHyaE2iVQim8o I1XhtRzXtn11OJJRLi2BiBXFVwYbrx40U5lA5z0/HsDncJ865Nc7NjM0EKgUl6E/dM MKktdZh98vM2O1KMgInCwAh0JSl2B++7OUXUZcHJwV+s3QZduRNX/iaZZeDbgwdtVr YbIb/n3y5CvXA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED4C6C3DA50; Mon, 15 Jul 2024 08:40:03 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:23 +0300 Subject: [PATCH v11 19/38] mtd: rawnand: add support for ts72xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-19-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chris Packham , Nikita Shubin Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=8042; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=jHDUJ6eL0sN9Xsu30iSDeAiNw2Ly7ktT7Xc33sA1DRU=; b=dTLYNyLYgnpY/GJf4y6fg+xDSliCxlsGUjB3yJq019vOpzZBmxVeVEMsNZwFmzSK1ttO/vjtj+Zp e8CX4xNlAyj+MXWTpt9WOvgUw5zkYqWmAF7WhDAQfuvNTVl1RX8u X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Technologic Systems has it's own nand controller implementation in CPLD. Signed-off-by: Nikita Shubin Acked-by: Miquel Raynal --- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/technologic-nand-controller.c | 222 +++++++++++++++++= ++++ 3 files changed, 229 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index cbf8ae85e1ae..5a51b835f6b6 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -449,6 +449,12 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. =20 +config MTD_NAND_TS72XX + tristate "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + help + Enables support for NAND controller on ts72xx SBCs. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..d0b0e6b83568 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_MLC_LPC32XX) +=3D lpc32xx_mlc.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) +=3D sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) +=3D mxc_nand.o obj-$(CONFIG_MTD_NAND_SOCRATES) +=3D socrates_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) +=3D technologic-nand-controller.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) +=3D txx9ndfmc.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) +=3D mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) +=3D vf610_nfc.o diff --git a/drivers/mtd/nand/raw/technologic-nand-controller.c b/drivers/m= td/nand/raw/technologic-nand-controller.c new file mode 100644 index 000000000000..0e45a6fd91dd --- /dev/null +++ b/drivers/mtd/nand/raw/technologic-nand-controller.c @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technologic Systems TS72xx NAND controller driver + * + * Copyright (C) 2023 Nikita Shubin + * + * Derived from: plat_nand.c + * Author: Vitaly Wool + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE BIT(22) /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE BIT(23) /* 0xN0800000 */ + +#define TS72XX_NAND_ALE BIT(0) +#define TS72XX_NAND_CLE BIT(1) +#define TS72XX_NAND_NCE BIT(2) + +#define TS72XX_NAND_CTRL_CLE (TS72XX_NAND_NCE | TS72XX_NAND_CLE) +#define TS72XX_NAND_CTRL_ALE (TS72XX_NAND_NCE | TS72XX_NAND_ALE) + +struct ts72xx_nand_data { + struct nand_controller controller; + struct nand_chip chip; + void __iomem *base; + void __iomem *ctrl; + void __iomem *busy; +}; + +static inline struct ts72xx_nand_data *chip_to_ts72xx(struct nand_chip *ch= ip) +{ + return container_of(chip, struct ts72xx_nand_data, chip); +} + +static int ts72xx_nand_attach_chip(struct nand_chip *chip) +{ + switch (chip->ecc.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: + return -EINVAL; + case NAND_ECC_ENGINE_TYPE_SOFT: + if (chip->ecc.algo =3D=3D NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + fallthrough; + default: + return 0; + } +} + +static void ts72xx_nand_ctrl(struct nand_chip *chip, u8 value) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned char bits =3D ioread8(data->ctrl) & ~GENMASK(2, 0); + + iowrite8(bits | value, data->ctrl); +} + +static int ts72xx_nand_exec_instr(struct nand_chip *chip, + const struct nand_op_instr *instr) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned int timeout_us; + u32 status; + int ret; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_CLE); + iowrite8(instr->ctx.cmd.opcode, data->base); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_ADDR_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_ALE); + iowrite8_rep(data->base, instr->ctx.addr.addrs, instr->ctx.addr.naddrs); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_DATA_IN_INSTR: + ioread8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_DATA_OUT_INSTR: + iowrite8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_WAITRDY_INSTR: + timeout_us =3D instr->ctx.waitrdy.timeout_ms * 1000; + ret =3D readb_poll_timeout(data->busy, status, status & BIT(5), 0, timeo= ut_us); + if (ret) + return ret; + + break; + } + + if (instr->delay_ns) + ndelay(instr->delay_ns); + + return 0; +} + +static int ts72xx_nand_exec_op(struct nand_chip *chip, + const struct nand_operation *op, bool check_only) +{ + unsigned int i; + int ret; + + if (check_only) + return 0; + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D ts72xx_nand_exec_instr(chip, &op->instrs[i]); + if (ret) + return ret; + } + + return 0; +} + +static const struct nand_controller_ops ts72xx_nand_ops =3D { + .attach_chip =3D ts72xx_nand_attach_chip, + .exec_op =3D ts72xx_nand_exec_op, +}; + +static int ts72xx_nand_probe(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data; + struct fwnode_handle *child; + struct mtd_info *mtd; + int err; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + nand_controller_init(&data->controller); + data->controller.ops =3D &ts72xx_nand_ops; + data->chip.controller =3D &data->controller; + + data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + data->ctrl =3D data->base + TS72XX_NAND_CONTROL_ADDR_LINE; + data->busy =3D data->base + TS72XX_NAND_BUSY_ADDR_LINE; + + child =3D fwnode_get_next_child_node(dev_fwnode(&pdev->dev), NULL); + if (!child) + return dev_err_probe(&pdev->dev, -ENXIO, + "ts72xx controller node should have exactly one child\n"); + + nand_set_flash_node(&data->chip, to_of_node(child)); + mtd =3D nand_to_mtd(&data->chip); + mtd->dev.parent =3D &pdev->dev; + platform_set_drvdata(pdev, data); + + /* + * This driver assumes that the default ECC engine should be TYPE_SOFT. + * Set ->engine_type before registering the NAND devices in order to + * provide a driver specific default value. + */ + data->chip.ecc.engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; + + /* Scan to find existence of the device */ + err =3D nand_scan(&data->chip, 1); + if (err) + goto err_handle_put; + + err =3D mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); + if (err) + goto err_clean_nand; + + return 0; + +err_clean_nand: + nand_cleanup(&data->chip); +err_handle_put: + fwnode_handle_put(child); + return err; +} + +static void ts72xx_nand_remove(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data =3D platform_get_drvdata(pdev); + struct fwnode_handle *fwnode =3D dev_fwnode(&pdev->dev); + struct nand_chip *chip =3D &data->chip; + int ret; + + ret =3D mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); + fwnode_handle_put(fwnode); +} + +static const struct of_device_id ts72xx_id_table[] =3D { + { .compatible =3D "technologic,ts7200-nand" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_id_table); + +static struct platform_driver ts72xx_nand_driver =3D { + .driver =3D { + .name =3D "ts72xx-nand", + .of_match_table =3D ts72xx_id_table, + }, + .probe =3D ts72xx_nand_probe, + .remove_new =3D ts72xx_nand_remove, +}; +module_platform_driver(ts72xx_nand_driver); + +MODULE_AUTHOR("Nikita Shubin "); +MODULE_DESCRIPTION("Technologic Systems TS72xx NAND controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D82186287; 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Signed-off-by: Nikita Shubin Acked-by: Damien Le Moal Reviewed-by: Krzysztof Kozlowski --- .../bindings/ata/cirrus,ep9312-pata.yaml | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml = b/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml new file mode 100644 index 000000000000..8130923fdc72 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP9312 PATA controller + +maintainers: + - Damien Le Moal + +properties: + compatible: + oneOf: + - const: cirrus,ep9312-pata + - items: + - const: cirrus,ep9315-pata + - const: cirrus,ep9312-pata + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF4C186294; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=bve1daT34BX1cHxQQUzPQRQeAZ9kV5+Nc9MsnGbxnKDjmuXnUeBEOXKT1KoSwFbaZMmUIXrPuFCKwPNYyEsc0dYNSftTWi/QP3OCx+PI6MKCWs7R3CXXl81jSqgF8O1pBIA2iInjKKAHjcvEZZGXx5n8MoRd+f8fYwOSl4LxpUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=TWeaRg+noW1lFeYfIFR9lOmT7O43s2anpkkQpN+Euww=; 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Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:25 +0300 Subject: [PATCH v11 21/38] ata: pata_ep93xx: add device tree support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-21-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Sergey Shtylyov , Damien Le Moal , Niklas Cassel Cc: linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=5839; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=NFhw+S6yqjvbTLxtqXwJdogYQOJyOLBy6lAMN4VNI8U=; b=2EQ0f3QKhxGo97IgvcsXmqAXJkq7IOjN5v5aGvnhuXjcePbFqhvnvwXGdcqKtkGyrSSNvgkc/A8V nnjVi5wFDnc4NERJJGJkoyXbdtNZ/ZOF2S2GSoloIK3pYL8E/UBL X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin - add OF ID match table - drop platform DMA and filters - change DMA setup to OF, so we can defer probe Signed-off-by: Nikita Shubin Reviewed-by: Sergey Shtylyov Acked-by: Damien Le Moal --- drivers/ata/pata_ep93xx.c | 80 +++++++++++++++++++++++++------------------= ---- 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c index c84a20892f1b..13246a92e29f 100644 --- a/drivers/ata/pata_ep93xx.c +++ b/drivers/ata/pata_ep93xx.c @@ -44,8 +44,8 @@ #include #include #include +#include =20 -#include #include =20 #define DRV_NAME "ep93xx-ide" @@ -126,7 +126,7 @@ enum { }; =20 struct ep93xx_pata_data { - const struct platform_device *pdev; + struct platform_device *pdev; void __iomem *ide_base; struct ata_timing t; bool iordy; @@ -135,9 +135,7 @@ struct ep93xx_pata_data { unsigned long udma_out_phys; =20 struct dma_chan *dma_rx_channel; - struct ep93xx_dma_data dma_rx_data; struct dma_chan *dma_tx_channel; - struct ep93xx_dma_data dma_tx_data; }; =20 static void ep93xx_pata_clear_regs(void __iomem *base) @@ -637,20 +635,13 @@ static void ep93xx_pata_release_dma(struct ep93xx_pat= a_data *drv_data) } } =20 -static bool ep93xx_pata_dma_filter(struct dma_chan *chan, void *filter_par= am) +static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data) { - if (ep93xx_dma_chan_is_m2p(chan)) - return false; - - chan->private =3D filter_param; - return true; -} - -static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data) -{ - const struct platform_device *pdev =3D drv_data->pdev; + struct platform_device *pdev =3D drv_data->pdev; + struct device *dev =3D &pdev->dev; dma_cap_mask_t mask; struct dma_slave_config conf; + int ret; =20 dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); @@ -660,22 +651,16 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_d= ata *drv_data) * to request only one channel, and reprogram it's direction at * start of new transfer. */ - drv_data->dma_rx_data.port =3D EP93XX_DMA_IDE; - drv_data->dma_rx_data.direction =3D DMA_DEV_TO_MEM; - drv_data->dma_rx_data.name =3D "ep93xx-pata-rx"; - drv_data->dma_rx_channel =3D dma_request_channel(mask, - ep93xx_pata_dma_filter, &drv_data->dma_rx_data); - if (!drv_data->dma_rx_channel) - return; + drv_data->dma_rx_channel =3D dma_request_chan(dev, "rx"); + if (IS_ERR(drv_data->dma_rx_channel)) + return dev_err_probe(dev, PTR_ERR(drv_data->dma_rx_channel), + "rx DMA setup failed\n"); =20 - drv_data->dma_tx_data.port =3D EP93XX_DMA_IDE; - drv_data->dma_tx_data.direction =3D DMA_MEM_TO_DEV; - drv_data->dma_tx_data.name =3D "ep93xx-pata-tx"; - drv_data->dma_tx_channel =3D dma_request_channel(mask, - ep93xx_pata_dma_filter, &drv_data->dma_tx_data); - if (!drv_data->dma_tx_channel) { - dma_release_channel(drv_data->dma_rx_channel); - return; + drv_data->dma_tx_channel =3D dma_request_chan(&pdev->dev, "tx"); + if (IS_ERR(drv_data->dma_tx_channel)) { + ret =3D dev_err_probe(dev, PTR_ERR(drv_data->dma_tx_channel), + "tx DMA setup failed\n"); + goto fail_release_rx; } =20 /* Configure receive channel direction and source address */ @@ -683,10 +668,10 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_d= ata *drv_data) conf.direction =3D DMA_DEV_TO_MEM; conf.src_addr =3D drv_data->udma_in_phys; conf.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; - if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) { - dev_err(&pdev->dev, "failed to configure rx dma channel\n"); - ep93xx_pata_release_dma(drv_data); - return; + ret =3D dmaengine_slave_config(drv_data->dma_rx_channel, &conf); + if (ret) { + dev_err_probe(dev, ret, "failed to configure rx dma channel"); + goto fail_release_dma; } =20 /* Configure transmit channel direction and destination address */ @@ -694,10 +679,20 @@ static void ep93xx_pata_dma_init(struct ep93xx_pata_d= ata *drv_data) conf.direction =3D DMA_MEM_TO_DEV; conf.dst_addr =3D drv_data->udma_out_phys; conf.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; - if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) { - dev_err(&pdev->dev, "failed to configure tx dma channel\n"); - ep93xx_pata_release_dma(drv_data); + ret =3D dmaengine_slave_config(drv_data->dma_tx_channel, &conf); + if (ret) { + dev_err_probe(dev, ret, "failed to configure tx dma channel"); + goto fail_release_dma; } + + return 0; + +fail_release_rx: + dma_release_channel(drv_data->dma_rx_channel); +fail_release_dma: + ep93xx_pata_release_dma(drv_data); + + return ret; } =20 static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc) @@ -954,7 +949,9 @@ static int ep93xx_pata_probe(struct platform_device *pd= ev) drv_data->ide_base =3D ide_base; drv_data->udma_in_phys =3D mem_res->start + IDEUDMADATAIN; drv_data->udma_out_phys =3D mem_res->start + IDEUDMADATAOUT; - ep93xx_pata_dma_init(drv_data); + err =3D ep93xx_pata_dma_init(drv_data); + if (err) + return err; =20 /* allocate host */ host =3D ata_host_alloc(&pdev->dev, 1); @@ -1021,9 +1018,16 @@ static void ep93xx_pata_remove(struct platform_devic= e *pdev) ep93xx_ide_release_gpio(pdev); } =20 +static const struct of_device_id ep93xx_pata_of_ids[] =3D { + { .compatible =3D "cirrus,ep9312-pata" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids); + static struct platform_driver ep93xx_pata_platform_driver =3D { .driver =3D { .name =3D DRV_NAME, + .of_match_table =3D ep93xx_pata_of_ids, }, .probe =3D ep93xx_pata_probe, .remove_new =3D ep93xx_pata_remove, --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FF6186297; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=eyYiJw1ulOmdN8P+QkDKNfARMTheBOdHCgkGDsqVtt11cXnpRv8iCHmy2W0FRVXlvCY/IaH9VYxSidnpdMt2fVZrMx90cDlFWpFmpfqsfKAMbfME3pTwevXbp7JSu52WmJieF6RwJOBXt6ui/Vq6xDUF/XM81JQQLH+o2XfW4FQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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a=ed25519-sha256; t=1721032799; l=3131; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=ArW40vHeN5DKryw3IpGISVSZUOgIwSTy8lnGeu9e4oI=; b=LGSUhrFMJXOAO6skqmd1bnj4eoDbAIMRVsdzRob4VlvJ0sLShvf5RBYl8m8sQoGTxvHjslgjZzZG jl8Rzi0ACxpXV5IrDgbewB02QXnUyPyXSUxud5FeDt3Ap0Kcm+qj X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add YAML bindings for ep93xx SoC keypad. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- .../bindings/input/cirrus,ep9307-keypad.yaml | 87 ++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.y= aml b/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml new file mode 100644 index 000000000000..a0d2460c55ab --- /dev/null +++ b/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cirrus,ep9307-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus ep93xx keypad + +maintainers: + - Alexander Sverdlin + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + +description: + The KPP is designed to interface with a keypad matrix with 2-point conta= ct + or 3-point contact keys. The KPP is designed to simplify the software ta= sk + of scanning a keypad matrix. The KPP is capable of detecting, debouncing, + and decoding one or multiple keys pressed simultaneously on a keypad. + +properties: + compatible: + oneOf: + - const: cirrus,ep9307-keypad + - items: + - enum: + - cirrus,ep9312-keypad + - cirrus,ep9315-keypad + - const: cirrus,ep9307-keypad + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + debounce-delay-ms: + description: | + Time in microseconds that key must be pressed or + released for state change interrupt to trigger. + + cirrus,prescale: + description: row/column counter pre-scaler load value + $ref: /schemas/types.yaml#/definitions/uint16 + maximum: 1023 + +required: + - compatible + - reg + - interrupts + - clocks + - linux,keymap + +unevaluatedProperties: false + +examples: + - | + #include + #include + keypad@800f0000 { + compatible =3D "cirrus,ep9307-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&eclk EP93XX_CLK_KEYPAD>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE62D18629A; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=RYdiRoI0OsZZMVIpwZtlIt1pmt/RO4fM0UD2NEeI43xD8qxO5NY6k65/ed99wQj/UWihmwopLUQbClK2BftkFuosFSHGdVdc3wQH9fBpXEEMOOzUK2UO4pkSeqD3SUpc+yZgrOfqJ0/nFmjxJi11abjJ19ZPum/fVstiyGweI5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=po+5T0wh+fhKAezWoDiKbxek/0D9dOCI2JEJkcLo7wQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:27 +0300 Subject: [PATCH v11 23/38] input: keypad: ep93xx: add DT support for Cirrus EP93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-23-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Russell King , Dmitry Torokhov , Nikita Shubin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Linus Walleij , Andy Shevchenko , Sergey Shtylyov Cc: Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-input@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=9166; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=6owwUYuhs8wvXnhQGQ+viSMw8D764eFnQVFxYe2CFoo=; b=q9Q0yY1Bx4dt1SC+Ma7oOWG6/R3PEWu8CsOpryvKl0aSwngB8vzwZl69qQ0SiJqTzAE5eFuy6CPb T/FzaQ3GAD01mWUoueHpEB+d3Ds73lu2zCH/6gWuaJIyUZPpPskU X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin - drop flags, they were not used anyway - add OF ID match table - process "autorepeat", "debounce-delay-ms", prescale from device tree - drop platform data usage and it's header - keymap goes from device tree now on Signed-off-by: Nikita Shubin Acked-by: Dmitry Torokhov --- arch/arm/mach-ep93xx/core.c | 46 --------------------- drivers/input/keyboard/ep93xx_keypad.c | 74 ++++++++++--------------------= ---- include/linux/soc/cirrus/ep93xx.h | 4 -- 3 files changed, 22 insertions(+), 102 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 03bce5e9d1f1..b99c46d22c4d 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -697,52 +697,6 @@ void __init ep93xx_register_keypad(struct ep93xx_keypa= d_platform_data *data) platform_device_register(&ep93xx_keypad_device); } =20 -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_c; - err =3D gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_d; - } - - /* Enable the keypad controller; GPIO ports C and D used for keypad */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); - - return 0; - -fail_gpio_d: - gpio_free(EP93XX_GPIO_LINE_C(i)); -fail_gpio_c: - for (--i; i >=3D 0; --i) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - return err; -} -EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); - -void ep93xx_keypad_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 0; i < 8; i++) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - - /* Disable the keypad controller; GPIO ports C and D used for GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); -} -EXPORT_SYMBOL(ep93xx_keypad_release_gpio); - /************************************************************************* * EP93xx I2S audio peripheral handling *************************************************************************/ diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboar= d/ep93xx_keypad.c index 6b811d6bf625..dcbc50304a5a 100644 --- a/drivers/input/keyboard/ep93xx_keypad.c +++ b/drivers/input/keyboard/ep93xx_keypad.c @@ -6,20 +6,13 @@ * * Based on the pxa27x matrix keypad controller by Rodolfo Giometti. * - * NOTE: - * - * The 3-key reset is triggered by pressing the 3 keys in - * Row 0, Columns 2, 4, and 7 at the same time. This action can - * be disabled by setting the EP93XX_KEYPAD_DISABLE_3_KEY flag. - * - * Normal operation for the matrix does not autorepeat the key press. - * This action can be enabled by setting the EP93XX_KEYPAD_AUTOREPEAT - * flag. */ =20 #include +#include #include #include +#include #include #include #include @@ -27,7 +20,6 @@ #include #include #include -#include #include =20 /* @@ -61,12 +53,16 @@ #define KEY_REG_KEY1_MASK GENMASK(5, 0) #define KEY_REG_KEY1_SHIFT 0 =20 +#define EP93XX_MATRIX_ROWS (8) +#define EP93XX_MATRIX_COLS (8) + #define EP93XX_MATRIX_SIZE (EP93XX_MATRIX_ROWS * EP93XX_MATRIX_COLS) =20 struct ep93xx_keypad { - struct ep93xx_keypad_platform_data *pdata; struct input_dev *input_dev; struct clk *clk; + unsigned int debounce; + u16 prescale; =20 void __iomem *mmio_base; =20 @@ -133,23 +129,11 @@ static irqreturn_t ep93xx_keypad_irq_handler(int irq,= void *dev_id) =20 static void ep93xx_keypad_config(struct ep93xx_keypad *keypad) { - struct ep93xx_keypad_platform_data *pdata =3D keypad->pdata; unsigned int val =3D 0; =20 - clk_set_rate(keypad->clk, pdata->clk_rate); + val |=3D (keypad->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK; =20 - if (pdata->flags & EP93XX_KEYPAD_DISABLE_3_KEY) - val |=3D KEY_INIT_DIS3KY; - if (pdata->flags & EP93XX_KEYPAD_DIAG_MODE) - val |=3D KEY_INIT_DIAG; - if (pdata->flags & EP93XX_KEYPAD_BACK_DRIVE) - val |=3D KEY_INIT_BACK; - if (pdata->flags & EP93XX_KEYPAD_TEST_MODE) - val |=3D KEY_INIT_T2; - - val |=3D ((pdata->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK); - - val |=3D ((pdata->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK= ); + val |=3D (keypad->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK; =20 __raw_writel(val, keypad->mmio_base + KEY_INIT); } @@ -220,17 +204,10 @@ static int ep93xx_keypad_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(ep93xx_keypad_pm_ops, ep93xx_keypad_suspend, ep93xx_keypad_resume); =20 -static void ep93xx_keypad_release_gpio_action(void *_pdev) -{ - struct platform_device *pdev =3D _pdev; - - ep93xx_keypad_release_gpio(pdev); -} - static int ep93xx_keypad_probe(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; struct ep93xx_keypad *keypad; - const struct matrix_keymap_data *keymap_data; struct input_dev *input_dev; int err; =20 @@ -238,14 +215,6 @@ static int ep93xx_keypad_probe(struct platform_device = *pdev) if (!keypad) return -ENOMEM; =20 - keypad->pdata =3D dev_get_platdata(&pdev->dev); - if (!keypad->pdata) - return -EINVAL; - - keymap_data =3D keypad->pdata->keymap_data; - if (!keymap_data) - return -EINVAL; - keypad->irq =3D platform_get_irq(pdev, 0); if (keypad->irq < 0) return keypad->irq; @@ -254,19 +223,13 @@ static int ep93xx_keypad_probe(struct platform_device= *pdev) if (IS_ERR(keypad->mmio_base)) return PTR_ERR(keypad->mmio_base); =20 - err =3D ep93xx_keypad_acquire_gpio(pdev); - if (err) - return err; - - err =3D devm_add_action_or_reset(&pdev->dev, - ep93xx_keypad_release_gpio_action, pdev); - if (err) - return err; - keypad->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(keypad->clk)) return PTR_ERR(keypad->clk); =20 + device_property_read_u32(dev, "debounce-delay-ms", &keypad->debounce); + device_property_read_u16(dev, "cirrus,prescale", &keypad->prescale); + input_dev =3D devm_input_allocate_device(&pdev->dev); if (!input_dev) return -ENOMEM; @@ -278,13 +241,13 @@ static int ep93xx_keypad_probe(struct platform_device= *pdev) input_dev->open =3D ep93xx_keypad_open; input_dev->close =3D ep93xx_keypad_close; =20 - err =3D matrix_keypad_build_keymap(keymap_data, NULL, + err =3D matrix_keypad_build_keymap(NULL, NULL, EP93XX_MATRIX_ROWS, EP93XX_MATRIX_COLS, keypad->keycodes, input_dev); if (err) return err; =20 - if (keypad->pdata->flags & EP93XX_KEYPAD_AUTOREPEAT) + if (device_property_read_bool(&pdev->dev, "autorepeat")) __set_bit(EV_REP, input_dev->evbit); input_set_drvdata(input_dev, keypad); =20 @@ -313,10 +276,17 @@ static void ep93xx_keypad_remove(struct platform_devi= ce *pdev) dev_pm_clear_wake_irq(&pdev->dev); } =20 +static const struct of_device_id ep93xx_keypad_of_ids[] =3D { + { .compatible =3D "cirrus,ep9307-keypad" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_keypad_of_ids); + static struct platform_driver ep93xx_keypad_driver =3D { .driver =3D { .name =3D "ep93xx-keypad", .pm =3D pm_sleep_ptr(&ep93xx_keypad_pm_ops), + .of_match_table =3D ep93xx_keypad_of_ids, }, .probe =3D ep93xx_keypad_probe, .remove_new =3D ep93xx_keypad_remove, diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index a27447971302..8942bfaf1545 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -41,8 +41,6 @@ int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); void ep93xx_pwm_release_gpio(struct platform_device *pdev); int ep93xx_ide_acquire_gpio(struct platform_device *pdev); void ep93xx_ide_release_gpio(struct platform_device *pdev); -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); -void ep93xx_keypad_release_gpio(struct platform_device *pdev); int ep93xx_i2s_acquire(void); void ep93xx_i2s_release(void); unsigned int ep93xx_chip_revision(void); @@ -52,8 +50,6 @@ static inline int ep93xx_pwm_acquire_gpio(struct platform= _device *pdev) { return static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { = return 0; } static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {} -static inline int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)= { return 0; } -static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev= ) {} static inline int ep93xx_i2s_acquire(void) { return 0; } static inline void ep93xx_i2s_release(void) {} static inline unsigned int ep93xx_chip_revision(void) { return 0; } --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8C8418629F; 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Signed-off-by: Nikita Shubin Reviewed-by: Guenter Roeck Reviewed-by: Andy Shevchenko --- drivers/watchdog/ts72xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c index 3d57670befe1..ac709dc31a65 100644 --- a/drivers/watchdog/ts72xx_wdt.c +++ b/drivers/watchdog/ts72xx_wdt.c @@ -12,6 +12,7 @@ */ =20 #include +#include #include #include #include @@ -160,10 +161,17 @@ static int ts72xx_wdt_probe(struct platform_device *p= dev) return 0; } =20 +static const struct of_device_id ts72xx_wdt_of_ids[] =3D { + { .compatible =3D "technologic,ts7200-wdt" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_wdt_of_ids); + static struct platform_driver ts72xx_wdt_driver =3D { .probe =3D ts72xx_wdt_probe, .driver =3D { .name =3D "ts72xx-wdt", + .of_match_table =3D ts72xx_wdt_of_ids, }, }; =20 --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8D211862A0; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; cv=none; b=MyGqqLDHBThOau5UDCRQuY29n/zy+Nfw9KjR86C4syYq6FMbPx2Td5n0Bx5uUc5mzeYso1XSwzk1j574A4mXetcWfusf069qcNQCbMGsza/OHa12Iz1ep66AABMSZiM2zimD5Ppm5vhtLJea+52kg+2nCP4zcOdTgIxNl7G423k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032804; c=relaxed/simple; bh=tpBb5gzOmG5ywIjVVdpHQ0mPmmXATJF1+bBKgyaj2zo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Mhbow6SU44yxDLz2TuO90B9f3KPfMyzjncOirc8v5FMW0L1tuFMuOah3OzzsahvgVkIa0nXO4iL6w/HEFeg4QwovEWhWZDg+ffKIyMPRM48emcu8I4djl+p8LVdfPqHHRFVWkT5Vb88rfmA38UMjIv4Qo+jqwRQUB3vZoxsbIDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MZ5NIhpD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MZ5NIhpD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6B573C4AF15; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032804; bh=tpBb5gzOmG5ywIjVVdpHQ0mPmmXATJF1+bBKgyaj2zo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MZ5NIhpDTOqSV3KSbieF8xJ/zuSk9OSY+99tIF3E5vEe67eE3B8YuRfGVuO1Datp2 gex5JR7SaMcLRiZS5TrWAwKvSN/Y51+IpHh7EJBmbO8azijKNgF5ImqB/O3tsshAQs c1A0N4HeDYpTYn/xvEVcP3kKYtNOY0gAG1wRfivbWEFCBkFN456b/mkNvzRQ3wqq28 SvYXzQiKMHPXxz1g7/3ptk0mE/70kX66s01jVSCWMJx15YUp6LaKumCyTvX5IOmc1U x4y9YK56t2TsWwzc2/RohPZtGceA51D6NbUdzI04WlcTkS1/1aHs6cJwU22DtNa6BN j0wF1Lcw/t0aA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64462C2BD09; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:29 +0300 Subject: [PATCH v11 25/38] gpio: ep93xx: add DT support for gpio-ep93xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-25-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Linus Walleij , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Bartosz Golaszewski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=4650; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=b6Hs2Wne/sgWTtBW5GkGY2qFIl/1bEenUx4OuZqg2Gs=; b=qIcZQB7+g4B8Lx1/JBXDMGh/MgEpoxAJNLeqMknmRFLrM6x8euIdkzCEJLunaqdqlclpdxc/Az7w itoCfnjWBuJL/+1gN1xRp907hpq0XkgGRXKKi1W5/kntuPVzGM+O X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add OF ID match table. Signed-off-by: Nikita Shubin Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski --- drivers/gpio/gpio-ep93xx.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index a55f635585f4..ab798c848215 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -12,13 +12,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include =20 struct ep93xx_gpio_irq_chip { void __iomem *base; @@ -138,7 +138,8 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - int port_mask =3D BIT(irqd_to_hwirq(d)); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + int port_mask =3D BIT(hwirq); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) eic->int_type2 ^=3D port_mask; /* switch edge direction */ @@ -147,26 +148,28 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data = *d) ep93xx_gpio_update_int_params(eic); =20 writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); - gpiochip_disable_irq(gc, irqd_to_hwirq(d)); + gpiochip_disable_irq(gc, hwirq); } =20 static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); =20 - eic->int_unmasked &=3D ~BIT(irqd_to_hwirq(d)); + eic->int_unmasked &=3D ~BIT(hwirq); ep93xx_gpio_update_int_params(eic); - gpiochip_disable_irq(gc, irqd_to_hwirq(d)); + gpiochip_disable_irq(gc, hwirq); } =20 static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); =20 - gpiochip_enable_irq(gc, irqd_to_hwirq(d)); - eic->int_unmasked |=3D BIT(irqd_to_hwirq(d)); + gpiochip_enable_irq(gc, hwirq); + eic->int_unmasked |=3D BIT(hwirq); ep93xx_gpio_update_int_params(eic); } =20 @@ -179,11 +182,11 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - irq_hw_number_t offset =3D irqd_to_hwirq(d); - int port_mask =3D BIT(offset); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + int port_mask =3D BIT(hwirq); irq_flow_handler_t handler; =20 - gc->direction_input(gc, offset); + gc->direction_input(gc, hwirq); =20 switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -209,7 +212,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) case IRQ_TYPE_EDGE_BOTH: eic->int_type1 |=3D port_mask; /* set initial polarity based on current input level */ - if (gc->get(gc, offset)) + if (gc->get(gc, hwirq)) eic->int_type2 &=3D ~port_mask; /* falling */ else eic->int_type2 |=3D port_mask; /* rising */ @@ -285,9 +288,8 @@ static int ep93xx_setup_irqs(struct platform_device *pd= ev, if (girq->num_parents =3D=3D 0) return -EINVAL; =20 - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); + girq->parents =3D devm_kcalloc(dev, girq->num_parents, sizeof(*girq->pare= nts), + GFP_KERNEL); if (!girq->parents) return -ENOMEM; =20 @@ -306,7 +308,7 @@ static int ep93xx_setup_irqs(struct platform_device *pd= ev, girq->parent_handler =3D ep93xx_gpio_f_irq_handler; =20 for (i =3D 0; i < girq->num_parents; i++) { - irq =3D platform_get_irq(pdev, i); + irq =3D platform_get_irq_optional(pdev, i); if (irq < 0) continue; =20 @@ -359,9 +361,15 @@ static int ep93xx_gpio_probe(struct platform_device *p= dev) return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 +static const struct of_device_id ep93xx_gpio_match[] =3D { + { .compatible =3D "cirrus,ep9301-gpio" }, + { /* sentinel */ } +}; + static struct platform_driver ep93xx_gpio_driver =3D { .driver =3D { .name =3D "gpio-ep93xx", + .of_match_table =3D ep93xx_gpio_match, }, .probe =3D ep93xx_gpio_probe, }; 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Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:30 +0300 Subject: [PATCH v11 26/38] ASoC: dt-bindings: ep93xx: Document DMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-26-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=1224; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=IYgRqPiUpJda2whx2paj9O35GPXheF0lc1rCPFeTg9o=; b=sg8u1hWMo9O0MlNoZBTN8U0p95VkegyQUzMza/YXfLuxZJ2bHcLjAeX93obhGl9sFDKXUzCcttwQ UCYGU2DNDrO1VJ/W6/bBstBRAipPe7ceLiOMC3F1dyeguHiWIzeq X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Document DMA support in binding document. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski Reviewed-by: Mark Brown --- .../devicetree/bindings/sound/cirrus,ep9301-i2s.yaml | 12 ++++++++= ++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml= b/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml index 453d493c941f..36a320ddf534 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml @@ -40,6 +40,16 @@ properties: - const: sclk - const: lrclk =20 + dmas: + items: + - description: out DMA channel + - description: in DMA channel + + dma-names: + items: + - const: tx + - const: rx + required: - compatible - '#sound-dai-cells' @@ -61,6 +71,8 @@ examples: <&syscon 30>, <&syscon 31>; clock-names =3D "mclk", "sclk", "lrclk"; + dmas =3D <&dma0 0 1>, <&dma0 0 2>; + dma-names =3D "tx", "rx"; }; =20 ... --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF9371862A6; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; cv=none; b=VURdM64WLSOcH2D5PPBL5GCcMag6YrI0o5WSnEUC79RAw+PnDgS2MMef86UFJtO5voSx4smcP5XyMf/L4b4BcmoahQAfQk3Xx6XR4isDD5y2qEwOoX0WStPGr/fgVdpUr7drqkq5X/k287bSYLBcQ9VIBppwaO0gLZNhYdUzDMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; c=relaxed/simple; bh=yWJGKp7TUnjWkI+yKdb5oOAuziHvtOUn8hbW128UrP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=b7Jxe5FkaxvDdZ/cHRS2RVoPpoAN7BxDmbRSG3gArma5odLh6Kg95zolNCsP8Hvc5Dx6Rt+2DJ1O4uxtdIDgMZTafAq+1XZeFWz6bKnxeh1+1UUr0cwPoULO2eYiUA+fEwZdffB9mMkmZx7OVTrFrwDD8EMizv6VwHucMi984OM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gS7dP7yC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gS7dP7yC" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8954AC4AF18; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032804; bh=yWJGKp7TUnjWkI+yKdb5oOAuziHvtOUn8hbW128UrP4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gS7dP7yCAu1qt8k0UxxyT6U6nBYZcO95GwKeMOmUNaylTzQlnSZfmOPIBsjVUF+V8 ERSeCwTgFIWjbWI8IXC7pjBn3f6gzQRD8JEWlnn1n3oacEPseoyAO//a4nj/DeinJo 2yr6+ShEWuAwXVvo4QPl+x9m2K1fyOpMtZpYzTLqf6gzXtWGOqS1zRnaiKp2yMSOXX yvxCbO5Cm4aQ19x37tuWXWRj/U1R5JFqgFmSHWbaWiGWwoxq1QKVV5szlA1uYohy/u vAi6/5FEd6lG9B/gnC3KIizVWyOo9ylH/asAD9FFMAMITAE0x6nAljYMkQ0httiaR6 tsJo8g+qx+qyw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80427C3DA5A; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:31 +0300 Subject: [PATCH v11 27/38] ASoC: dt-bindings: ep93xx: Document Audio Port support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-27-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=848; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=2DHMH5gyVKrv/Zk+FD8HvqWkgva1cQdPwzXr84HYqOY=; b=30JTnlO2w3TIQrNaFZO3fJQCOsuvpaovwzhYnMarApTP3eJpFy91fhzjTgRON5R/PIFB8EaTubZw JsdVLxP2DMTrFw4VI1uWxw11ptZQgrwHb0CO+bw7KR8xoKUXR4aG X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Document Audio Graph Port support in binding document. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml= b/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml index 36a320ddf534..4693e85aed37 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,ep9301-i2s.yaml @@ -50,6 +50,10 @@ properties: - const: tx - const: rx =20 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - '#sound-dai-cells' --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E172186E4F; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; cv=none; b=itCHPj5McSPdMp8nV/eJEQ8PZFb731QKy6odKG12Jz2soZNgPmTbxfZRjp6XMGfWEEz7kqV6RVgAMUh2d94QfMjLcaHY7M2uoFVRJXTTd7Vxpb2JBX290ZQKfcUmTkVgGyNOqAMvlz46eWZhnWINgXvKQ/vqs/zacX/pHRHLVN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; c=relaxed/simple; bh=tBkZbYGVVOZU5vTFJf/4Hx9sKzgEywOUrQAiC76tePA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BPxZXsF1oSKndPnRtJIcxXZzCaJDqVmHRqkkP7ip0s8MdjAQoDmDlEBFtSxCt8EcQx09oKmaahRO7viImtertVltIe4DfugFRCHD53Hvmb0PL5KLowZr5a5WfpKb9fbpPKbvvQRb8c0Guc5q8155naVPom2q0mgLuczYRDqk76A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WDggX+Tt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WDggX+Tt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 982B3C4AF1C; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721032804; bh=tBkZbYGVVOZU5vTFJf/4Hx9sKzgEywOUrQAiC76tePA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WDggX+TtBwPmhUk1hFUDpRfiqtd766mIn/3ywGz3gzs9+Q/kAg8zDU0/Rne1H6zAd SdeAqk111QGQbwjZgZNh6xauDqiK6syPmwYXpBLhzSCaTswfP5GfC7Txs6M2ujPIJE PF9bQA290ljJHL5hoSg20KKSPawrUijA5KwpS9tJEgYhcucWmCe3Fd4sJlBIpEssz+ wnbFQ1TQ+ayfsCCKW3XH1rKBkegy0x20lPVnDcjB5M5J0Z08DNhJAMhaJ3rpgQ+iCs 2d5Ef5wsH/2KsfWCzwTlPtON21R3zMT/E8YsknTdCzpl8GpGfPz/wdIFhJP8P/u4+d 3uoKk50TtOREg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FFA5C3DA5B; Mon, 15 Jul 2024 08:40:04 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:32 +0300 Subject: [PATCH v11 28/38] ASoC: ep93xx: Drop legacy DMA support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-28-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Alexander Sverdlin , Kuninori Morimoto , Nikita Shubin Cc: linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032799; l=3001; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=SYU0FfCpDAQ8R3Z8Qf0jhP48bWMjlrK6VfAOntLJB4w=; b=LcOcjqItH0H/4lcxXM39N8SahQf4nAfn5o6ncX4TJE69n3SZW4wTsqQc5mpY3Zol55cdxybCTwB3 VbdRGaYqDC++Vj+vU+UoTnnEB+dqwu/Yj4B1xg9DB7ZEfgd8DJAd X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Alexander Sverdlin And rely on OF DMA. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- sound/soc/cirrus/ep93xx-i2s.c | 19 ------------------- sound/soc/cirrus/ep93xx-pcm.c | 19 +------------------ 2 files changed, 1 insertion(+), 37 deletions(-) diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c index 522de4b80293..9e83cdf8a943 100644 --- a/sound/soc/cirrus/ep93xx-i2s.c +++ b/sound/soc/cirrus/ep93xx-i2s.c @@ -24,7 +24,6 @@ #include #include =20 -#include #include =20 #include "ep93xx-pcm.h" @@ -80,19 +79,6 @@ struct ep93xx_i2s_info { struct snd_dmaengine_dai_dma_data dma_params_tx; }; =20 -static struct ep93xx_dma_data ep93xx_i2s_dma_data[] =3D { - [SNDRV_PCM_STREAM_PLAYBACK] =3D { - .name =3D "i2s-pcm-out", - .port =3D EP93XX_DMA_I2S1, - .direction =3D DMA_MEM_TO_DEV, - }, - [SNDRV_PCM_STREAM_CAPTURE] =3D { - .name =3D "i2s-pcm-in", - .port =3D EP93XX_DMA_I2S1, - .direction =3D DMA_DEV_TO_MEM, - }, -}; - static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info, unsigned reg, unsigned val) { @@ -198,11 +184,6 @@ static int ep93xx_i2s_dai_probe(struct snd_soc_dai *da= i) { struct ep93xx_i2s_info *info =3D snd_soc_dai_get_drvdata(dai); =20 - info->dma_params_tx.filter_data =3D - &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK]; - info->dma_params_rx.filter_data =3D - &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE]; - snd_soc_dai_init_dma_data(dai, &info->dma_params_tx, &info->dma_params_rx); =20 diff --git a/sound/soc/cirrus/ep93xx-pcm.c b/sound/soc/cirrus/ep93xx-pcm.c index fa72acd8d334..5ecb4671cbba 100644 --- a/sound/soc/cirrus/ep93xx-pcm.c +++ b/sound/soc/cirrus/ep93xx-pcm.c @@ -18,8 +18,6 @@ #include #include =20 -#include - #include "ep93xx-pcm.h" =20 static const struct snd_pcm_hardware ep93xx_pcm_hardware =3D { @@ -35,30 +33,15 @@ static const struct snd_pcm_hardware ep93xx_pcm_hardwar= e =3D { .fifo_size =3D 32, }; =20 -static bool ep93xx_pcm_dma_filter(struct dma_chan *chan, void *filter_para= m) -{ - struct ep93xx_dma_data *data =3D filter_param; - - if (data->direction =3D=3D ep93xx_dma_chan_direction(chan)) { - chan->private =3D data; - return true; - } - - return false; -} - static const struct snd_dmaengine_pcm_config ep93xx_dmaengine_pcm_config = =3D { .pcm_hardware =3D &ep93xx_pcm_hardware, - .compat_filter_fn =3D ep93xx_pcm_dma_filter, .prealloc_buffer_size =3D 131072, }; =20 int devm_ep93xx_pcm_platform_register(struct device *dev) { return devm_snd_dmaengine_pcm_register(dev, - &ep93xx_dmaengine_pcm_config, - SND_DMAENGINE_PCM_FLAG_NO_DT | - SND_DMAENGINE_PCM_FLAG_COMPAT); + &ep93xx_dmaengine_pcm_config, 0); } EXPORT_SYMBOL_GPL(devm_ep93xx_pcm_platform_register); =20 --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06F011862AD; Mon, 15 Jul 2024 08:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; cv=none; b=gVhtQqSBnEypXwSufAlSP2tzWg7Ke2Z4kkVgSOtaTZU9cy+1YCMoxHa9J8Bhk3ao9iYZtYa16bCNUla+p1ecm9+76x2cZB8GzouMYBqMonuoUff5yc5zPWAhSJ3fVZl/SNWAJcxtS20zeaRPkfCWp2KgeGSfg9aYWYpW8SgjZMY= ARC-Message-Signature: i=1; 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a=ed25519-sha256; t=1721032799; l=12048; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=I+hKQEG3Gbgs42kqFIu1CKMiW24MjJIjQDdolFMCOMc=; b=Rc2ieIZg0PZgf4sag0LEcpewIhEnWzphYYyiFk6URtC2aCpQTRS94qzEPlWKMoEdAtwBk2EAzqSZ lZ1Yv9NCDjqS6IIyWQSWxojkosWZUwvVoKGNE4vaQ1rJ+xa+EL2l X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add support for Cirrus Logic EP93XX SoC's family. Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/cirrus/ep93xx.dtsi | 444 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 444 insertions(+) diff --git a/arch/arm/boot/dts/cirrus/ep93xx.dtsi b/arch/arm/boot/dts/cirru= s/ep93xx.dtsi new file mode 100644 index 000000000000..0dd1eee346ca --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep93xx.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Cirrus Logic systems EP93XX SoC + */ +#include +#include +#include +#include +/ { + soc: soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + syscon: syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", "syscon"; + reg =3D <0x80930000 0x1000>; + + #clock-cells =3D <1>; + clocks =3D <&xtali>; + + spi_default_pins: pins-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + + ac97_default_pins: pins-ac97 { + function =3D "ac97"; + groups =3D "ac97"; + }; + + i2s_on_ssp_pins: pins-i2sonssp { + function =3D "i2s"; + groups =3D "i2s_on_ssp"; + }; + + i2s_on_ac97_pins: pins-i2sonac97 { + function =3D "i2s"; + groups =3D "i2s_on_ac97"; + }; + + gpio1_default_pins: pins-gpio1 { + function =3D "gpio"; + groups =3D "gpio1agrp"; + }; + + pwm1_default_pins: pins-pwm1 { + function =3D "pwm"; + groups =3D "pwm1"; + }; + + gpio2_default_pins: pins-gpio2 { + function =3D "gpio"; + groups =3D "gpio2agrp"; + }; + + gpio3_default_pins: pins-gpio3 { + function =3D "gpio"; + groups =3D "gpio3agrp"; + }; + + keypad_default_pins: pins-keypad { + function =3D "keypad"; + groups =3D "keypadgrp"; + }; + + gpio4_default_pins: pins-gpio4 { + function =3D "gpio"; + groups =3D "gpio4agrp"; + }; + + gpio6_default_pins: pins-gpio6 { + function =3D "gpio"; + groups =3D "gpio6agrp"; + }; + + gpio7_default_pins: pins-gpio7 { + function =3D "gpio"; + groups =3D "gpio7agrp"; + }; + + ide_default_pins: pins-ide { + function =3D "pata"; + groups =3D "idegrp"; + }; + + lcd_on_dram0_pins: pins-rasteronsdram0 { + function =3D "lcd"; + groups =3D "rasteronsdram0grp"; + }; + + lcd_on_dram3_pins: pins-rasteronsdram3 { + function =3D "lcd"; + groups =3D "rasteronsdram3grp"; + }; + }; + + adc: adc@80900000 { + compatible =3D "cirrus,ep9301-adc"; + reg =3D <0x80900000 0x28>; + clocks =3D <&syscon EP93XX_CLK_ADC>; + interrupt-parent =3D <&vic0>; + interrupts =3D <30>; + status =3D "disabled"; + }; + + /* + * The EP93XX expansion bus is a set of up to 7 each up to 16MB + * windows in the 256MB space from 0x50000000 to 0x5fffffff. + * But since we don't require to setup it in any way, we can + * represent it as a simple-bus. + */ + ebi: bus@80080000 { + compatible =3D "simple-bus"; + reg =3D <0x80080000 0x20>; + native-endian; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + }; + + dma0: dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, + <12>, <13>, <14>, <15>, <16>; + #dma-cells =3D <2>; + }; + + dma1: dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + #dma-cells =3D <2>; + }; + + eth0: ethernet@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + mdio0: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gpio0: gpio@80840000 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840000 0x04>, + <0x80840010 0x04>, + <0x80840090 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio1: gpio@80840004 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840004 0x04>, + <0x80840014 0x04>, + <0x808400ac 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio2: gpio@80840008 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840008 0x04>, + <0x80840018 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio2_default_pins>; + }; + + gpio3: gpio@8084000c { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x8084000c 0x04>, + <0x8084001c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio3_default_pins>; + }; + + gpio4: gpio@80840020 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840020 0x04>, + <0x80840024 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio4_default_pins>; + }; + + gpio5: gpio@80840030 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840030 0x04>, + <0x80840034 0x04>, + <0x8084004c 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts-extended =3D <&vic0 19>, <&vic0 20>, + <&vic0 21>, <&vic0 22>, + <&vic1 15>, <&vic1 16>, + <&vic1 17>, <&vic1 18>; + }; + + gpio6: gpio@80840038 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840038 0x04>, + <0x8084003c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio6_default_pins>; + }; + + gpio7: gpio@80840040 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840040 0x04>, + <0x80840044 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio7_default_pins>; + }; + + i2s: i2s@80820000 { + compatible =3D "cirrus,ep9301-i2s"; + reg =3D <0x80820000 0x100>; + #sound-dai-cells =3D <0>; + interrupt-parent =3D <&vic1>; + interrupts =3D <28>; + clocks =3D <&syscon EP93XX_CLK_I2S_MCLK>, + <&syscon EP93XX_CLK_I2S_SCLK>, + <&syscon EP93XX_CLK_I2S_LRCLK>; + clock-names =3D "mclk", "sclk", "lrclk"; + dmas =3D <&dma0 0 1>, <&dma0 0 2>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + ide: ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + status =3D "disabled"; + }; + + vic0: interrupt-controller@800b0000 { + compatible =3D "arm,pl192-vic"; + reg =3D <0x800b0000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <1>; + valid-mask =3D <0x7ffffffc>; + valid-wakeup-mask =3D <0x0>; + }; + + vic1: interrupt-controller@800c0000 { + compatible =3D "arm,pl192-vic"; + reg =3D <0x800c0000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <1>; + valid-mask =3D <0x1fffffff>; + valid-wakeup-mask =3D <0x0>; + }; + + keypad: keypad@800f0000 { + compatible =3D "cirrus,ep9307-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&syscon EP93XX_CLK_KEYPAD>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pwm0: pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910000 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm1: pwm@80910020 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910020 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + #pwm-cells =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1_default_pins>; + status =3D "disabled"; + }; + + rtc0: rtc@80920000 { + compatible =3D "cirrus,ep9301-rtc"; + reg =3D <0x80920000 0x100>; + }; + + spi0: spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + reg =3D <0x808a0000 0x18>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&syscon EP93XX_CLK_SPI>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_default_pins>; + status =3D "disabled"; + }; + + timer: timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; + + uart0: serial@808c0000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x808c0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART1>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "uartclk", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <20>; + status =3D "disabled"; + }; + + uart1: uart@808d0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808d0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART2>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "apb:uart2", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <22>; + status =3D "disabled"; + }; + + uart2: uart@808b0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808b0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART3>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "apb:uart3", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <23>; + status =3D "disabled"; + }; + + usb0: usb@80020000 { + compatible =3D "generic-ohci"; + reg =3D <0x80020000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <24>; + clocks =3D <&syscon EP93XX_CLK_USB>; + status =3D "disabled"; + }; + + watchdog0: watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; + }; + + xtali: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <14745600>; + clock-output-names =3D "xtali"; + }; +}; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AC801862B3; Mon, 15 Jul 2024 08:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; cv=none; b=QI+dcK1FfQTJKFQzS996mf/JNGOFD+MMFQP18vM/fBOmjPsVn1v/9vAva2oD8EHyMYDWPt2lI2hFZvi4T3KQErJlN2obiOv2wTN+dxVICYgddlS0CWVxsZ7KQjvG831Sr/j1ttKXl4PSs9OSkeZl1VSVhpWHT3rfeUjH6qzL1bk= ARC-Message-Signature: i=1; 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a=ed25519-sha256; t=1721032799; l=6186; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=F8g8fhLrok2XoBODc7kkFWBfV9QlTn8N1KFztkjBqBQ=; b=qEXOlNy1uSKGgvb9iKrlw2KX/tknjbDaK3ARQ5movRK5byZnD09O4uWLSFvoHhdCF0mafqHup559 Usr4Rc2BA+YMBgIRb5z+tdQpt/ZwHL6UX/vRg+YAuSdscHL7M3R5 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add device tree file for Technologic Systems ts7250 board and Liebherr bk3 board which have many in common, both are based on ep9302 SoC variant. Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/cirrus/Makefile | 3 + arch/arm/boot/dts/cirrus/ep93xx-bk3.dts | 125 +++++++++++++++++++++++++ arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts | 145 +++++++++++++++++++++++++= ++++ 3 files changed, 273 insertions(+) diff --git a/arch/arm/boot/dts/cirrus/Makefile b/arch/arm/boot/dts/cirrus/M= akefile index e944d3e2129d..211a7e2f2115 100644 --- a/arch/arm/boot/dts/cirrus/Makefile +++ b/arch/arm/boot/dts/cirrus/Makefile @@ -3,3 +3,6 @@ dtb-$(CONFIG_ARCH_CLPS711X) +=3D \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_CLPS711X) +=3D \ ep7211-edb7211.dtb +dtb-$(CONFIG_ARCH_EP93XX) +=3D \ + ep93xx-bk3.dtb \ + ep93xx-ts7250.dtb diff --git a/arch/arm/boot/dts/cirrus/ep93xx-bk3.dts b/arch/arm/boot/dts/ci= rrus/ep93xx-bk3.dts new file mode 100644 index 000000000000..40bc9b2a6ba8 --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep93xx-bk3.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Liebherr controller BK3.1 based on Cirrus EP9302 S= oC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + model =3D "Liebherr controller BK3.1"; + compatible =3D "liebherr,bk3", "cirrus,ep9301"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chosen { + }; + + memory@0 { + device_type =3D "memory"; + /* should be set from ATAGS */ + reg =3D <0x00000000 0x02000000>, + <0x000530c0 0x01fdd000>; + }; + + leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "grled"; + gpios =3D <&gpio4 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + }; + + led-1 { + label =3D "rdled"; + gpios =3D <&gpio4 1 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_FAULT; + }; + }; +}; + +&ebi { + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "System"; + reg =3D <0x00000000 0x01e00000>; + read-only; + }; + + partition@1e00000 { + label =3D "Data"; + reg =3D <0x01e00000 0x05f20000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + }; + }; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&i2s { + dmas =3D <&dma0 0 1>, <&dma0 0 2>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_on_ac97_pins>; + status =3D "okay"; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&syscon 6 163 1>; +}; + +&gpio4 { + gpio-ranges =3D <&syscon 0 97 2>; + status =3D "okay"; +}; + +&gpio6 { + gpio-ranges =3D <&syscon 0 87 2>; + status =3D "okay"; +}; + +&gpio7 { + gpio-ranges =3D <&syscon 2 199 4>; + status =3D "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts b/arch/arm/boot/dts= /cirrus/ep93xx-ts7250.dts new file mode 100644 index 000000000000..9e03f93d9fc8 --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep93xx-ts7250.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Technologic Systems ts7250 board based on Cirrus E= P9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + compatible =3D "technologic,ts7250", "cirrus,ep9301"; + model =3D "TS-7250 SBC"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chosen { + }; + + memory@0 { + device_type =3D "memory"; + /* should be set from ATAGS */ + reg =3D <0x00000000 0x02000000>, + <0x000530c0 0x01fdd000>; + }; + + leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "grled"; + gpios =3D <&gpio4 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + }; + + led-1 { + label =3D "rdled"; + gpios =3D <&gpio4 1 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_FAULT; + }; + }; +}; + +&ebi { + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "TS-BOOTROM"; + reg =3D <0x00000000 0x00020000>; + read-only; + }; + + partition@20000 { + label =3D "Linux"; + reg =3D <0x00020000 0x07d00000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + }; + }; + + rtc@10800000 { + compatible =3D "st,m48t86"; + reg =3D <0x10800000 0x1>, + <0x11700000 0x1>; + }; + + watchdog@23800000 { + compatible =3D "technologic,ts7200-wdt"; + reg =3D <0x23800000 0x01>, + <0x23c00000 0x01>; + timeout-sec =3D <30>; + }; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&syscon 6 163 1>; +}; + +/* ts7250 doesn't have GPIO Port D present */ +&gpio3 { + status =3D "disabled"; +}; + +&gpio4 { + gpio-ranges =3D <&syscon 0 97 2>; +}; + +&gpio6 { + gpio-ranges =3D <&syscon 0 87 2>; +}; + +&gpio7 { + gpio-ranges =3D <&syscon 2 199 4>; +}; + +&spi0 { + cs-gpios =3D <&gpio5 2 GPIO_ACTIVE_HIGH>; + dmas =3D <&dma1 10 2>, <&dma1 10 1>; + dma-names =3D "rx", "tx"; + status =3D "okay"; + + tmp122: temperature-sensor@0 { + compatible =3D "ti,tmp122"; + reg =3D <0>; + spi-max-frequency =3D <2000000>; + }; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; +}; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 117FC1862B6; Mon, 15 Jul 2024 08:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721032805; cv=none; b=HIojMgNME80XR5JUgTL1INPdjVCiGwadh2klkOM1Q1rC2nHpEAU+LgXWyCu7NLsOza4KJiyWbp4CkOSYyWVovix+nsp2Qb6rvO7yuXl1IZ35D/+iYfHrhnaqqidNwHR5nnZQoVDMTAxWrqtLgR/BrRH4CQh6MqbBEYOmpCN3ydQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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a=ed25519-sha256; t=1721032799; l=4425; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=1fX8TbERg73yR+bhzVLpudoqqqV75gQ9Bv/zyZTclIA=; b=VJKCkHYVFhpNK/ss05yuNI7XpmWeK9ad6aHose0NzFLzJLy2JqjpDZAnm9Sk+xedDTl5ifmQlDTV TTg0GslPCIgjAP/8lVVjs3285rhLpNyapJ/RyUvmRo3+Crr5L+VM X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Alexander Sverdlin Add device tree for Cirrus EDB9302. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/cirrus/Makefile | 1 + arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts | 181 ++++++++++++++++++++++++= ++++ 2 files changed, 182 insertions(+) diff --git a/arch/arm/boot/dts/cirrus/Makefile b/arch/arm/boot/dts/cirrus/M= akefile index 211a7e2f2115..e6015983e464 100644 --- a/arch/arm/boot/dts/cirrus/Makefile +++ b/arch/arm/boot/dts/cirrus/Makefile @@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_CLPS711X) +=3D \ dtb-$(CONFIG_ARCH_CLPS711X) +=3D \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_EP93XX) +=3D \ + ep93xx-edb9302.dtb \ ep93xx-bk3.dtb \ ep93xx-ts7250.dtb diff --git a/arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts b/arch/arm/boot/dt= s/cirrus/ep93xx-edb9302.dts new file mode 100644 index 000000000000..0bf10086f969 --- /dev/null +++ b/arch/arm/boot/dts/cirrus/ep93xx-edb9302.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree file for Cirrus Logic EDB9302 board based on EP9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "cirrus,edb9302", "cirrus,ep9301"; + model =3D "cirrus,edb9302"; + + chosen { + }; + + memory@0 { + device_type =3D "memory"; + /* should be set from ATAGS */ + reg =3D <0x0000000 0x800000>, + <0x1000000 0x800000>, + <0x4000000 0x800000>, + <0x5000000 0x800000>; + }; + + sound { + compatible =3D "audio-graph-card2"; + label =3D "EDB93XX"; + links =3D <&i2s_port>; + }; + + leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "grled"; + gpios =3D <&gpio4 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + }; + + led-1 { + label =3D "rdled"; + gpios =3D <&gpio4 1 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_FAULT; + }; + }; +}; + +&adc { + status =3D "okay"; +}; + +&ebi { + flash@60000000 { + compatible =3D "cfi-flash"; + reg =3D <0x60000000 0x1000000>; + bank-width =3D <2>; + }; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&gpio0 { + gpio-ranges =3D <&syscon 0 153 1>, + <&syscon 1 152 1>, + <&syscon 2 151 1>, + <&syscon 3 148 1>, + <&syscon 4 147 1>, + <&syscon 5 146 1>, + <&syscon 6 145 1>, + <&syscon 7 144 1>; +}; + +&gpio1 { + gpio-ranges =3D <&syscon 0 143 1>, + <&syscon 1 142 1>, + <&syscon 2 141 1>, + <&syscon 3 140 1>, + <&syscon 4 165 1>, + <&syscon 5 164 1>, + <&syscon 6 163 1>, + <&syscon 7 160 1>; +}; + +&gpio2 { + gpio-ranges =3D <&syscon 0 115 1>; +}; + +/* edb9302 doesn't have GPIO Port D present */ +&gpio3 { + status =3D "disabled"; +}; + +&gpio4 { + gpio-ranges =3D <&syscon 0 97 2>; +}; + +&gpio5 { + gpio-ranges =3D <&syscon 1 170 1>, + <&syscon 2 169 1>, + <&syscon 3 168 1>; +}; + +&gpio6 { + gpio-ranges =3D <&syscon 0 87 2>; +}; + +&gpio7 { + gpio-ranges =3D <&syscon 2 199 4>; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_on_ac97_pins>; + status =3D "okay"; + i2s_port: port { + i2s_ep: endpoint { + system-clock-direction-out; + frame-master; + bitclock-master; + mclk-fs =3D <256>; + dai-format =3D "i2s"; + convert-channels =3D <2>; + convert-sample-format =3D "s32_le"; + remote-endpoint =3D <&codec_ep>; + }; + }; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&spi0 { + cs-gpios =3D <&gpio0 6 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW>; + dmas =3D <&dma1 10 2>, <&dma1 10 1>; + dma-names =3D "rx", "tx"; + status =3D "okay"; + + cs4271: codec@0 { + compatible =3D "cirrus,cs4271"; + reg =3D <0>; + #sound-dai-cells =3D <0>; + spi-max-frequency =3D <6000000>; + spi-cpol; + spi-cpha; + reset-gpio =3D <&gpio0 1 GPIO_ACTIVE_LOW>; + port { + codec_ep: endpoint { + remote-endpoint =3D <&i2s_ep>; + }; + }; + }; + + at25f1024: eeprom@1 { + compatible =3D "atmel,at25"; + reg =3D <1>; + address-width =3D <8>; + size =3D <0x20000>; + pagesize =3D <256>; + spi-max-frequency =3D <20000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; +}; --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E084186E20 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-32-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Russell King , Hartley Sweeten , Alexander Sverdlin , Arnd Bergmann , Andrew Davis , Nicolas Schier , Dmitry Baryshkov , Masahiro Yamada , Nikita Shubin , Samuel Holland Cc: Helge Deller , Bjorn Andersson , Catalin Marinas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=3110; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=MU0azT5lNnulLeP5AfbO0wMy6289MR0wM0qk0K+/fy8=; b=Caz26YUB6UAbKAbNa4GafIUI4sBsa6EfcADXsOW4TGPTPvgZ/AZ3xbc50JpC0Rfl23AB68IIBn1A B2nabxK6A6Zwr5dSojbsATsATOfpdMSyu2QTuZZ5wZsBiRO4d7j2 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Add compulsory device tree support to the Cirrus ep93xx ARMv4 platform. - select PINCTRL_EP93xx - select COMMON_CLK_EP93XX, as clock driver moved out of platform code - select ARCH_HAS_RESET_CONTROLLER Select ARM_ATAG_DTB_COMPAT to update device tree with information about memory passed from bootloader. We have to leave all MACH options as they are used for board checking before decomp, to turn off watchdog and ethernet DMA. Tested-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/Makefile | 1 - arch/arm/mach-ep93xx/Kconfig | 20 ++++++++++---------- arch/arm/mach-ep93xx/Makefile | 11 ----------- 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 71afdd98ddf2..aafebf145738 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,7 +183,6 @@ machine-$(CONFIG_ARCH_CLPS711X) +=3D clps711x machine-$(CONFIG_ARCH_DAVINCI) +=3D davinci machine-$(CONFIG_ARCH_DIGICOLOR) +=3D digicolor machine-$(CONFIG_ARCH_DOVE) +=3D dove -machine-$(CONFIG_ARCH_EP93XX) +=3D ep93xx machine-$(CONFIG_ARCH_EXYNOS) +=3D exynos machine-$(CONFIG_ARCH_FOOTBRIDGE) +=3D footbridge machine-$(CONFIG_ARCH_GEMINI) +=3D gemini diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 703f3d232a60..812b71dcf60e 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -3,27 +3,27 @@ menuconfig ARCH_EP93XX bool "EP93xx-based" depends on ATAGS depends on ARCH_MULTI_V4T + # CONFIG_ARCH_MULTI_V7 is not set depends on CPU_LITTLE_ENDIAN + select ARCH_HAS_RESET_CONTROLLER select ARCH_SPARSEMEM_ENABLE select ARM_AMBA select ARM_VIC + select ARM_APPENDED_DTB # Old Redboot bootloaders deployed + select ARM_ATAG_DTB_COMPAT # we need this to update dt memory node + select COMMON_CLK_EP93XX + select EP93XX_TIMER select CLKSRC_MMIO select CPU_ARM920T select GPIOLIB + select PINCTRL + select PINCTRL_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. =20 if ARCH_EP93XX =20 -menu "Cirrus EP93xx Implementation Options" - -config EP93XX_SOC_COMMON - bool - default y - select SOC_BUS - select LEDS_GPIO_REGISTER - -comment "EP93xx Platforms" +# menu "EP93xx Platforms" =20 config MACH_BK3 bool "Support Liebherr BK3.1" @@ -103,6 +103,6 @@ config MACH_VISION_EP9307 Say 'Y' here if you want your kernel to support the Vision Engraving Systems EP9307 SoM. =20 -endmenu +# endmenu =20 endif diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile deleted file mode 100644 index 62e37403df14..000000000000 --- a/arch/arm/mach-ep93xx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# -obj-y :=3D core.o clock.o timer-ep93xx.o - -obj-$(CONFIG_EP93XX_DMA) +=3D dma.o - -obj-$(CONFIG_MACH_EDB93XX) +=3D edb93xx.o -obj-$(CONFIG_MACH_TS72XX) +=3D ts72xx.o -obj-$(CONFIG_MACH_VISION_EP9307)+=3D vision_ep9307.o --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2209B186E28; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-33-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Russell King , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Nikita Shubin , Linus Walleij , Andy Shevchenko , Dmitry Torokhov Cc: Damien Le Moal , Stephen Boyd , Sergey Shtylyov , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=4449; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=9tWs5wPLeKECQlcQ9rkIh26LRGvwgfxOpMK+JfxreaE=; b=qRTr7TBUoWCa+2fq+nDOeJXUxuaasbBBBlRoqSicurr/ryj0YAZVf8iLuc+fe0aJkoPgAf9qYf+l X3bZoYBlBT57fTBtb/PA/GT1lb1jmFadTlOE2i7t6k2/eXFBgL2x X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Drop legacy gpio request/free since we are using pinctrl for this now. Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig Acked-by: Thierry Reding Acked-by: Linus Walleij --- arch/arm/mach-ep93xx/core.c | 42 -----------------------------------= ---- drivers/pwm/pwm-ep93xx.c | 18 ----------------- include/linux/soc/cirrus/ep93xx.h | 4 ---- 3 files changed, 64 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index b99c46d22c4d..4ddf1a4cba33 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -577,48 +577,6 @@ void __init ep93xx_register_pwm(int pwm0, int pwm1) platform_device_register(&ep93xx_pwm1_device); } =20 -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) -{ - int err; - - if (pdev->id =3D=3D 0) { - err =3D 0; - } else if (pdev->id =3D=3D 1) { - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO14, - dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); - if (err) - goto fail; - - /* PWM 1 output on EGPIO[14] */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); - } else { - err =3D -ENODEV; - } - - return err; - -fail: - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - return err; -} -EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); - -void ep93xx_pwm_release_gpio(struct platform_device *pdev) -{ - if (pdev->id =3D=3D 1) { - gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - - /* EGPIO[14] used for GPIO */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); - } -} -EXPORT_SYMBOL(ep93xx_pwm_release_gpio); - - /************************************************************************* * EP93xx video peripheral handling *************************************************************************/ diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index 67c3fdbf7ae3..994f89ac43b4 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -27,8 +27,6 @@ =20 #include =20 -#include /* for ep93xx_pwm_{acquire,release}_g= pio() */ - #define EP93XX_PWMx_TERM_COUNT 0x00 #define EP93XX_PWMx_DUTY_CYCLE 0x04 #define EP93XX_PWMx_ENABLE 0x08 @@ -44,20 +42,6 @@ static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pw= m_chip *chip) return pwmchip_get_drvdata(chip); } =20 -static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pw= m) -{ - struct platform_device *pdev =3D to_platform_device(pwmchip_parent(chip)); - - return ep93xx_pwm_acquire_gpio(pdev); -} - -static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct platform_device *pdev =3D to_platform_device(pwmchip_parent(chip)); - - ep93xx_pwm_release_gpio(pdev); -} - static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { @@ -156,8 +140,6 @@ static int ep93xx_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, } =20 static const struct pwm_ops ep93xx_pwm_ops =3D { - .request =3D ep93xx_pwm_request, - .free =3D ep93xx_pwm_free, .apply =3D ep93xx_pwm_apply, }; =20 diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 8942bfaf1545..f6376edc1b33 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -37,8 +37,6 @@ struct ep93xx_regmap_adev { container_of((_adev), struct ep93xx_regmap_adev, adev) =20 #ifdef CONFIG_ARCH_EP93XX -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); -void ep93xx_pwm_release_gpio(struct platform_device *pdev); int ep93xx_ide_acquire_gpio(struct platform_device *pdev); void ep93xx_ide_release_gpio(struct platform_device *pdev); int ep93xx_i2s_acquire(void); @@ -46,8 +44,6 @@ void ep93xx_i2s_release(void); unsigned int ep93xx_chip_revision(void); =20 #else -static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { = return 0; } static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {} static inline int ep93xx_i2s_acquire(void) { return 0; } --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33ABE186E31; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-34-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Hartley Sweeten , Alexander Sverdlin , Russell King , Sergey Shtylyov , Damien Le Moal , Niklas Cassel , Nikita Shubin , Linus Walleij , Stephen Boyd , Andy Shevchenko Cc: Thierry Reding , Dmitry Torokhov , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=5459; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=JKdRtMOxmJOigA+HsuRSo4me4xtHq4Wfii+aJcJbkDg=; b=yDgamXPWTvQcpNmnEwz/juufb6mm2KK8I3JPldrsHvjErlxTP+JSM6hI9QvkwTtRb/fqthxuiVI+ LDJYWZW7AZ2fOWqsaT4wIHgzrlG8VjQsyS4enn/5vKQxLbMZ+X8S X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Drop legacy acquire/release since we are using pinctrl for this now. Signed-off-by: Nikita Shubin Reviewed-by: Sergey Shtylyov Acked-by: Damien Le Moal Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko --- arch/arm/mach-ep93xx/core.c | 72 -----------------------------------= ---- drivers/ata/pata_ep93xx.c | 25 ++++---------- include/linux/soc/cirrus/ep93xx.h | 4 --- 3 files changed, 6 insertions(+), 95 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 4ddf1a4cba33..9c6154bb37b5 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -779,78 +779,6 @@ void __init ep93xx_register_ide(void) platform_device_register(&ep93xx_ide_device); } =20 -int ep93xx_ide_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); - if (err) - goto fail_egpio15; - for (i =3D 2; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_e; - } - for (i =3D 4; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_g; - } - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_h; - } - - /* GPIO ports E[7:2], G[7:4] and H used by IDE */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - return 0; - -fail_gpio_h: - for (--i; i >=3D 0; --i) - gpio_free(EP93XX_GPIO_LINE_H(i)); - i =3D 8; -fail_gpio_g: - for (--i; i >=3D 4; --i) - gpio_free(EP93XX_GPIO_LINE_G(i)); - i =3D 8; -fail_gpio_e: - for (--i; i >=3D 2; --i) - gpio_free(EP93XX_GPIO_LINE_E(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); -fail_egpio15: - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - return err; -} -EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); - -void ep93xx_ide_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 2; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_E(i)); - for (i =3D 4; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_G(i)); - for (i =3D 0; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_H(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - - - /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); -} -EXPORT_SYMBOL(ep93xx_ide_release_gpio); - /************************************************************************* * EP93xx ADC *************************************************************************/ diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c index 13246a92e29f..a8555f630097 100644 --- a/drivers/ata/pata_ep93xx.c +++ b/drivers/ata/pata_ep93xx.c @@ -922,28 +922,18 @@ static int ep93xx_pata_probe(struct platform_device *= pdev) void __iomem *ide_base; int err; =20 - err =3D ep93xx_ide_acquire_gpio(pdev); - if (err) - return err; - /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */ irq =3D platform_get_irq(pdev, 0); - if (irq < 0) { - err =3D irq; - goto err_rel_gpio; - } + if (irq < 0) + return irq; =20 ide_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); - if (IS_ERR(ide_base)) { - err =3D PTR_ERR(ide_base); - goto err_rel_gpio; - } + if (IS_ERR(ide_base)) + return PTR_ERR(ide_base); =20 drv_data =3D devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL); - if (!drv_data) { - err =3D -ENOMEM; - goto err_rel_gpio; - } + if (!drv_data) + return -ENOMEM; =20 drv_data->pdev =3D pdev; drv_data->ide_base =3D ide_base; @@ -1002,8 +992,6 @@ static int ep93xx_pata_probe(struct platform_device *p= dev) =20 err_rel_dma: ep93xx_pata_release_dma(drv_data); -err_rel_gpio: - ep93xx_ide_release_gpio(pdev); return err; } =20 @@ -1015,7 +1003,6 @@ static void ep93xx_pata_remove(struct platform_device= *pdev) ata_host_detach(host); ep93xx_pata_release_dma(drv_data); ep93xx_pata_clear_regs(drv_data->ide_base); - ep93xx_ide_release_gpio(pdev); } =20 static const struct of_device_id ep93xx_pata_of_ids[] =3D { diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index f6376edc1b33..142c33a2d7db 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -37,15 +37,11 @@ struct ep93xx_regmap_adev { container_of((_adev), struct ep93xx_regmap_adev, adev) =20 #ifdef CONFIG_ARCH_EP93XX -int ep93xx_ide_acquire_gpio(struct platform_device *pdev); -void ep93xx_ide_release_gpio(struct platform_device *pdev); int ep93xx_i2s_acquire(void); void ep93xx_i2s_release(void); unsigned int ep93xx_chip_revision(void); =20 #else -static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {} static inline int ep93xx_i2s_acquire(void) { return 0; } static inline void ep93xx_i2s_release(void) {} static inline unsigned int ep93xx_chip_revision(void) { return 0; } --=20 2.43.2 From nobody Thu Dec 18 05:20:32 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 567D6186E48 for ; Mon, 15 Jul 2024 08:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Signed-off-by: Nikita Shubin --- arch/arm/mach-ep93xx/clock.c | 733 ------------------------ arch/arm/mach-ep93xx/core.c | 955 ---------------------------= ---- arch/arm/mach-ep93xx/dma.c | 114 ---- arch/arm/mach-ep93xx/edb93xx.c | 368 ------------ arch/arm/mach-ep93xx/ep93xx-regs.h | 38 -- arch/arm/mach-ep93xx/gpio-ep93xx.h | 111 ---- arch/arm/mach-ep93xx/hardware.h | 25 - arch/arm/mach-ep93xx/irqs.h | 76 --- arch/arm/mach-ep93xx/platform.h | 42 -- arch/arm/mach-ep93xx/soc.h | 212 ------- arch/arm/mach-ep93xx/timer-ep93xx.c | 143 ----- arch/arm/mach-ep93xx/ts72xx.c | 422 -------------- arch/arm/mach-ep93xx/ts72xx.h | 94 --- arch/arm/mach-ep93xx/vision_ep9307.c | 321 ----------- include/linux/platform_data/spi-ep93xx.h | 15 - 15 files changed, 3669 deletions(-) diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c deleted file mode 100644 index 85a496ddc619..000000000000 --- a/arch/arm/mach-ep93xx/clock.c +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/clock.c - * Clock control for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" - -#include - -#include "soc.h" - -static DEFINE_SPINLOCK(clk_lock); - -static char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; -static char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; -static char pclk_divisors[] =3D { 1, 2, 4, 8 }; - -static char adc_divisors[] =3D { 16, 4 }; -static char sclk_divisors[] =3D { 2, 4 }; -static char lrclk_divisors[] =3D { 32, 64, 128 }; - -static const char * const mux_parents[] =3D { - "xtali", - "pll1", - "pll2" -}; - -/* - * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS - */ -static unsigned long calc_pll_rate(unsigned long long rate, u32 config_wor= d) -{ - int i; - - rate *=3D ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ - rate *=3D ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ - do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ - for (i =3D 0; i < ((config_word >> 16) & 3); i++) /* PS */ - rate >>=3D 1; - - return (unsigned long)rate; -} - -struct clk_psc { - struct clk_hw hw; - void __iomem *reg; - u8 bit_idx; - u32 mask; - u8 shift; - u8 width; - char *div; - u8 num_div; - spinlock_t *lock; -}; - -#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) - -static int ep93xx_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D readl(psc->reg); - - return (val & BIT(psc->bit_idx)) ? 1 : 0; -} - -static int ep93xx_clk_enable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val |=3D BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static void ep93xx_clk_disable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); -} - -static const struct clk_ops clk_ep93xx_gate_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, -}; - -static struct clk_hw *ep93xx_clk_register_gate(const char *name, - const char *parent_name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ep93xx_gate_ops; - init.flags =3D CLK_SET_RATE_PARENT; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D (parent_name ? 1 : 0); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->hw.init =3D &init; - psc->lock =3D &clk_lock; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - - return &psc->hw; -} - -static u8 ep93xx_mux_get_parent(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - - if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) - return 0; - - if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) - return 1; - - return 2; -} - -static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (index >=3D ARRAY_SIZE(mux_parents)) - return -EINVAL; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); - - - if (index !=3D 0) { - val |=3D EP93XX_SYSCON_CLKDIV_ESEL; - val |=3D (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; - } - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static bool is_best(unsigned long rate, unsigned long now, - unsigned long best) -{ - return abs(rate - now) < abs(rate - best); -} - -static int ep93xx_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long rate =3D req->rate; - struct clk *best_parent =3D NULL; - unsigned long __parent_rate; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - unsigned long best_parent_rate; - int __div =3D 0, __pdiv =3D 0; - int i; - - /* - * Try the two pll's and the external clock - * Because the valid predividers are 2, 2.5 and 3, we multiply - * all the clocks by 2 to avoid floating point math. - * - * This is based on the algorithm in the ep93xx raster guide: - * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf - * - */ - for (i =3D 0; i < ARRAY_SIZE(mux_parents); i++) { - struct clk *parent =3D clk_get_sys(mux_parents[i], NULL); - - __parent_rate =3D clk_get_rate(parent); - mclk_rate =3D __parent_rate * 2; - - /* Try each predivider value */ - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - best_rate =3D actual_rate; - best_parent_rate =3D __parent_rate; - best_parent =3D parent; - } - } - } - - if (!best_parent) - return -EINVAL; - - req->best_parent_rate =3D best_parent_rate; - req->best_parent_hw =3D __clk_get_hw(best_parent); - req->rate =3D best_rate; - - return 0; -} - -static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long rate =3D 0; - u32 val =3D __raw_readl(psc->reg); - int __pdiv =3D ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); - int __div =3D val & 0x7f; - - if (__div > 0) - rate =3D (parent_rate * 2) / ((__pdiv + 3) * __div); - - return rate; -} - -static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - int pdiv =3D 0, div =3D 0; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - int __div =3D 0, __pdiv =3D 0; - u32 val; - - mclk_rate =3D parent_rate * 2; - - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - pdiv =3D __pdiv - 3; - div =3D __div; - best_rate =3D actual_rate; - } - } - - if (!best_rate) - return -EINVAL; - - val =3D __raw_readl(psc->reg); - - /* Clear old dividers */ - val &=3D ~0x37f; - - /* Set the new pdiv and div bits for the new clock rate */ - val |=3D (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops clk_ddiv_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .get_parent =3D ep93xx_mux_get_parent, - .set_parent =3D ep93xx_mux_set_parent_lock, - .determine_rate =3D ep93xx_mux_determine_rate, - .recalc_rate =3D ep93xx_ddiv_recalc_rate, - .set_rate =3D ep93xx_ddiv_set_rate, -}; - -static struct clk_hw *clk_hw_register_ddiv(const char *name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ddiv_ops; - init.flags =3D 0; - init.parent_names =3D mux_parents; - init.num_parents =3D ARRAY_SIZE(mux_parents); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - u8 index =3D (val & psc->mask) >> psc->shift; - - if (index > psc->num_div) - return 0; - - return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); -} - -static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long best =3D 0, now, maxdiv; - int i; - - maxdiv =3D psc->div[psc->num_div - 1]; - - for (i =3D 0; i < psc->num_div; i++) { - if ((rate * psc->div[i]) =3D=3D *parent_rate) - return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - now =3D DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - if (is_best(rate, now, best)) - best =3D now; - } - - if (!best) - best =3D DIV_ROUND_UP_ULL(*parent_rate, maxdiv); - - return best; -} - -static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg) & ~psc->mask; - int i; - - for (i =3D 0; i < psc->num_div; i++) - if (rate =3D=3D parent_rate / psc->div[i]) { - val |=3D i << psc->shift; - break; - } - - if (i =3D=3D psc->num_div) - return -EINVAL; - - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops ep93xx_div_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .recalc_rate =3D ep93xx_div_recalc_rate, - .round_rate =3D ep93xx_div_round_rate, - .set_rate =3D ep93xx_div_set_rate, -}; - -static struct clk_hw *clk_hw_register_div(const char *name, - const char *parent_name, - void __iomem *reg, - u8 enable_bit, - u8 shift, - u8 width, - char *clk_divisors, - u8 num_div) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &ep93xx_div_ops; - init.flags =3D 0; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D 1; - - psc->reg =3D reg; - psc->bit_idx =3D enable_bit; - psc->mask =3D GENMASK(shift + width - 1, shift); - psc->shift =3D shift; - psc->div =3D clk_divisors; - psc->num_div =3D num_div; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -struct ep93xx_gate { - unsigned int bit; - const char *dev_id; - const char *con_id; -}; - -static struct ep93xx_gate ep93xx_uarts[] =3D { - {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, - {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, - {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, -}; - -static void __init ep93xx_uart_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - u32 value; - unsigned int clk_uart_div; - - value =3D __raw_readl(EP93XX_SYSCON_PWRCNT); - if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) - clk_uart_div =3D 1; - else - clk_uart_div =3D 2; - - hw =3D clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart= _div); - - /* parenting uart gate clocks to uart clock */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { - hw =3D ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, - "uart", - EP93XX_SYSCON_DEVCFG, - ep93xx_uarts[i].bit); - - clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id); - } -} - -static struct ep93xx_gate ep93xx_dmas[] =3D { - {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, -}; - -static void __init ep93xx_dma_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - int ret; - - for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { - hw =3D clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, - "hclk", 0, - EP93XX_SYSCON_PWRCNT, - ep93xx_dmas[i].bit, - 0, - &clk_lock); - - ret =3D clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); - if (ret) - pr_err("%s: failed to register lookup %s\n", - __func__, ep93xx_dmas[i].con_id); - } -} - -static int __init ep93xx_clock_init(void) -{ - u32 value; - struct clk_hw *hw; - unsigned long clk_pll1_rate; - unsigned long clk_f_rate; - unsigned long clk_h_rate; - unsigned long clk_p_rate; - unsigned long clk_pll2_rate; - unsigned int clk_f_div; - unsigned int clk_h_div; - unsigned int clk_p_div; - unsigned int clk_usb_div; - unsigned long clk_spi_div; - - hw =3D clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_= RATE); - clk_hw_register_clkdev(hw, NULL, "xtali"); - - /* Determine the bootloader configured pll1 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET1); - if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) - clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; - else - clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - - hw =3D clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll1"); - - /* Initialize the pll1 derived clocks */ - clk_f_div =3D fclk_divisors[(value >> 25) & 0x7]; - clk_h_div =3D hclk_divisors[(value >> 20) & 0x7]; - clk_p_div =3D pclk_divisors[(value >> 18) & 0x3]; - - hw =3D clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div= ); - clk_f_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div= ); - clk_h_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div= ); - clk_p_rate =3D clk_get_rate(hw->clk); - - clk_hw_register_clkdev(hw, "apb_pclk", NULL); - - ep93xx_dma_clock_init(); - - /* Determine the bootloader configured pll2 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET2); - if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) - clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; - else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) - clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - else - clk_pll2_rate =3D 0; - - hw =3D clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll2"); - - /* Initialize the pll2 derived clocks */ - /* - * These four bits set the divide ratio between the PLL2 - * output and the USB clock. - * 0000 - Divide by 1 - * 0001 - Divide by 2 - * 0010 - Divide by 3 - * 0011 - Divide by 4 - * 0100 - Divide by 5 - * 0101 - Divide by 6 - * 0110 - Divide by 7 - * 0111 - Divide by 8 - * 1000 - Divide by 9 - * 1001 - Divide by 10 - * 1010 - Divide by 11 - * 1011 - Divide by 12 - * 1100 - Divide by 13 - * 1101 - Divide by 14 - * 1110 - Divide by 15 - * 1111 - Divide by 1 - * On power-on-reset these bits are reset to 0000b. - */ - clk_usb_div =3D (((value >> 28) & 0xf) + 1); - hw =3D clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_us= b_div); - hw =3D clk_hw_register_gate(NULL, "ohci-platform", - "usb_clk", 0, - EP93XX_SYSCON_PWRCNT, - EP93XX_SYSCON_PWRCNT_USH_EN, - 0, - &clk_lock); - clk_hw_register_clkdev(hw, NULL, "ohci-platform"); - - /* - * EP93xx SSP clock rate was doubled in version E2. For more information - * see: - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - clk_spi_div =3D 1; - if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) - clk_spi_div =3D 2; - hw =3D clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, = clk_spi_div); - clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); - - /* pwm clock */ - hw =3D clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); - clk_hw_register_clkdev(hw, "pwm_clk", NULL); - - pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", - clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); - pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", - clk_f_rate / 1000000, clk_h_rate / 1000000, - clk_p_rate / 1000000); - - ep93xx_uart_clock_init(); - - /* touchscreen/adc clock */ - hw =3D clk_hw_register_div("ep93xx-adc", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, - EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); - - /* keypad clock */ - hw =3D clk_hw_register_div("ep93xx-keypad", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_KEN, - EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); - - /* On reset PDIV and VDIV is set to zero, while PDIV zero - * means clock disable, VDIV shouldn't be zero. - * So i set both dividers to minimum. - */ - /* ENA - Enable CLK divider. */ - /* PDIV - 00 - Disable clock */ - /* VDIV - at least 2 */ - /* Check and enable video clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_VIDCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); - - /* check and enable i2s clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); - - /* video clk */ - hw =3D clk_hw_register_ddiv("ep93xx-fb", - EP93XX_SYSCON_VIDCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); - - /* i2s clk */ - hw =3D clk_hw_register_ddiv("mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); - - /* i2s sclk */ -#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 -#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 - hw =3D clk_hw_register_div("sclk", - "mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_SDIV_SHIFT, - EP93XX_I2SCLKDIV_SDIV_WIDTH, - sclk_divisors, - ARRAY_SIZE(sclk_divisors)); - - clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); - - /* i2s lrclk */ -#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 -#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3 - hw =3D clk_hw_register_div("lrclk", - "sclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_LRDIV32_SHIFT, - EP93XX_I2SCLKDIV_LRDIV32_WIDTH, - lrclk_divisors, - ARRAY_SIZE(lrclk_divisors)); - - clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); - - return 0; -} -postcore_initcall(ep93xx_clock_init); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c deleted file mode 100644 index 9c6154bb37b5..000000000000 --- a/arch/arm/mach-ep93xx/core.c +++ /dev/null @@ -1,955 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/core.c - * Core routines for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2007 Herbert Valerio Riedel - * - * Thanks go to Michael Burian and Ray Lehtiniemi for their key - * role in the ep93xx linux community. - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include -#include -#include -#include - -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" -#include "irqs.h" - -/************************************************************************* - * Static I/O mappings that are needed for all EP93xx platforms - *************************************************************************/ -static struct map_desc ep93xx_io_desc[] __initdata =3D { - { - .virtual =3D EP93XX_AHB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_AHB_PHYS_BASE), - .length =3D EP93XX_AHB_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D EP93XX_APB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_APB_PHYS_BASE), - .length =3D EP93XX_APB_SIZE, - .type =3D MT_DEVICE, - }, -}; - -void __init ep93xx_map_io(void) -{ - iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); -} - -/************************************************************************* - * EP93xx IRQ handling - *************************************************************************/ -void __init ep93xx_init_irq(void) -{ - vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0= ); - vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0= ); -} - - -/************************************************************************* - * EP93xx System Controller Software Locked register handling - *************************************************************************/ - -/* - * syscon_swlock prevents anything else from writing to the syscon - * block while a software locked register is being written. - */ -static DEFINE_SPINLOCK(syscon_swlock); - -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) -{ - unsigned long flags; - - spin_lock_irqsave(&syscon_swlock, flags); - - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, reg); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s) -{ - unsigned long flags; - unsigned int val; - - spin_lock_irqsave(&syscon_swlock, flags); - - val =3D __raw_readl(EP93XX_SYSCON_DEVCFG); - val &=3D ~clear_bits; - val |=3D set_bits; - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, EP93XX_SYSCON_DEVCFG); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -/** - * ep93xx_chip_revision() - returns the EP93xx chip revision - * - * See "platform.h" for more information. - */ -unsigned int ep93xx_chip_revision(void) -{ - unsigned int v; - - v =3D __raw_readl(EP93XX_SYSCON_SYSCFG); - v &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; - v >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; - return v; -} -EXPORT_SYMBOL_GPL(ep93xx_chip_revision); - -/************************************************************************* - * EP93xx GPIO - *************************************************************************/ -/* port A */ -static struct resource ep93xx_a_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_a_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), - .resource =3D ep93xx_a_gpio_resources, -}; - -/* port B */ -static struct resource ep93xx_b_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_b_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), - .resource =3D ep93xx_b_gpio_resources, -}; - -/* port C */ -static struct resource ep93xx_c_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), -}; - -static struct platform_device ep93xx_c_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 2, - .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), - .resource =3D ep93xx_c_gpio_resources, -}; - -/* port D */ -static struct resource ep93xx_d_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_d_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 3, - .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), - .resource =3D ep93xx_d_gpio_resources, -}; - -/* port E */ -static struct resource ep93xx_e_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), -}; - -static struct platform_device ep93xx_e_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 4, - .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), - .resource =3D ep93xx_e_gpio_resources, -}; - -/* port F */ -static struct resource ep93xx_f_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), -}; - -static struct platform_device ep93xx_f_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 5, - .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), - .resource =3D ep93xx_f_gpio_resources, -}; - -/* port G */ -static struct resource ep93xx_g_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_g_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 6, - .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), - .resource =3D ep93xx_g_gpio_resources, -}; - -static struct platform_device *ep93xx_gpio_device[] __initdata =3D { - &ep93xx_a_gpio, - &ep93xx_b_gpio, - &ep93xx_c_gpio, - &ep93xx_d_gpio, - &ep93xx_e_gpio, - &ep93xx_f_gpio, - &ep93xx_g_gpio, -}; - -/************************************************************************* - * EP93xx peripheral handling - *************************************************************************/ -#define EP93XX_UART_MCR_OFFSET (0x0100) - -static void ep93xx_uart_set_mctrl(struct amba_device *dev, - void __iomem *base, unsigned int mctrl) -{ - unsigned int mcr; - - mcr =3D 0; - if (mctrl & TIOCM_RTS) - mcr |=3D 2; - if (mctrl & TIOCM_DTR) - mcr |=3D 1; - - __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); -} - -static struct amba_pl010_data ep93xx_uart_data =3D { - .set_mctrl =3D ep93xx_uart_set_mctrl, -}; - -static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_B= ASE, - { IRQ_EP93XX_UART1 }, &ep93xx_uart_data); - -static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_B= ASE, - { IRQ_EP93XX_UART2 }, NULL); - -static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_B= ASE, - { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); - -static struct resource ep93xx_rtc_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), -}; - -static struct platform_device ep93xx_rtc_device =3D { - .name =3D "ep93xx-rtc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_rtc_resource), - .resource =3D ep93xx_rtc_resource, -}; - -/************************************************************************* - * EP93xx OHCI USB Host - *************************************************************************/ - -static struct clk *ep93xx_ohci_host_clock; - -static int ep93xx_ohci_power_on(struct platform_device *pdev) -{ - if (!ep93xx_ohci_host_clock) { - ep93xx_ohci_host_clock =3D devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(ep93xx_ohci_host_clock)) - return PTR_ERR(ep93xx_ohci_host_clock); - } - - return clk_prepare_enable(ep93xx_ohci_host_clock); -} - -static void ep93xx_ohci_power_off(struct platform_device *pdev) -{ - clk_disable(ep93xx_ohci_host_clock); -} - -static struct usb_ohci_pdata ep93xx_ohci_pdata =3D { - .power_on =3D ep93xx_ohci_power_on, - .power_off =3D ep93xx_ohci_power_off, - .power_suspend =3D ep93xx_ohci_power_off, -}; - -static struct resource ep93xx_ohci_resources[] =3D { - DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), - DEFINE_RES_IRQ(IRQ_EP93XX_USB), -}; - -static u64 ep93xx_ohci_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_ohci_device =3D { - .name =3D "ohci-platform", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ohci_resources), - .resource =3D ep93xx_ohci_resources, - .dev =3D { - .dma_mask =3D &ep93xx_ohci_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .platform_data =3D &ep93xx_ohci_pdata, - }, -}; - -/************************************************************************* - * EP93xx physmap'ed flash - *************************************************************************/ -static struct physmap_flash_data ep93xx_flash_data; - -static struct resource ep93xx_flash_resource =3D { - .flags =3D IORESOURCE_MEM, -}; - -static struct platform_device ep93xx_flash =3D { - .name =3D "physmap-flash", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_flash_data, - }, - .num_resources =3D 1, - .resource =3D &ep93xx_flash_resource, -}; - -/** - * ep93xx_register_flash() - Register the external flash device. - * @width: bank width in octets - * @start: resource start address - * @size: resource size - */ -void __init ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - ep93xx_flash_data.width =3D width; - - ep93xx_flash_resource.start =3D start; - ep93xx_flash_resource.end =3D start + size - 1; - - platform_device_register(&ep93xx_flash); -} - - -/************************************************************************* - * EP93xx ethernet peripheral handling - *************************************************************************/ -static struct ep93xx_eth_data ep93xx_eth_data; - -static struct resource ep93xx_eth_resource[] =3D { - DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), - DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), -}; - -static u64 ep93xx_eth_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_eth_device =3D { - .name =3D "ep93xx-eth", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_eth_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_eth_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_eth_resource), - .resource =3D ep93xx_eth_resource, -}; - -/** - * ep93xx_register_eth - Register the built-in ethernet platform device. - * @data: platform specific ethernet configuration (__initdata) - * @copy_addr: flag indicating that the MAC address should be copied - * from the IndAd registers (as programmed by the bootloader) - */ -void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_add= r) -{ - if (copy_addr) - memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); - - ep93xx_eth_data =3D *data; - platform_device_register(&ep93xx_eth_device); -} - - -/************************************************************************* - * EP93xx i2c peripheral handling - *************************************************************************/ - -/* All EP93xx devices use the same two GPIO pins for I2C bit-banging */ -static struct gpiod_lookup_table ep93xx_i2c_gpiod_table =3D { - .dev_id =3D "i2c-gpio.0", - .table =3D { - /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - { } - }, -}; - -static struct platform_device ep93xx_i2c_device =3D { - .name =3D "i2c-gpio", - .id =3D 0, - .dev =3D { - .platform_data =3D NULL, - }, -}; - -/** - * ep93xx_register_i2c - Register the i2c platform device. - * @devices: platform specific i2c bus device information (__initdata) - * @num: the number of devices on the i2c bus - */ -void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) -{ - /* - * FIXME: this just sets the two pins as non-opendrain, as no - * platforms tries to do that anyway. Flag the applicable lines - * as open drain in the GPIO_LOOKUP above and the driver or - * gpiolib will handle open drain/open drain emulation as need - * be. Right now i2c-gpio emulates open drain which is not - * optimal. - */ - __raw_writel((0 << 1) | (0 << 0), - EP93XX_GPIO_EEDRIVE); - - i2c_register_board_info(0, devices, num); - gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table); - platform_device_register(&ep93xx_i2c_device); -} - -/************************************************************************* - * EP93xx SPI peripheral handling - *************************************************************************/ -static struct ep93xx_spi_info ep93xx_spi_master_data; - -static struct resource ep93xx_spi_resources[] =3D { - DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), - DEFINE_RES_IRQ(IRQ_EP93XX_SSP), -}; - -static u64 ep93xx_spi_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_spi_device =3D { - .name =3D "ep93xx-spi", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_spi_master_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_spi_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_spi_resources), - .resource =3D ep93xx_spi_resources, -}; - -/** - * ep93xx_register_spi() - registers spi platform device - * @info: ep93xx board specific spi master info (__initdata) - * @devices: SPI devices to register (__initdata) - * @num: number of SPI devices to register - * - * This function registers platform device for the EP93xx SPI controller a= nd - * also makes sure that SPI pins are muxed so that I2S is not using those = pins. - */ -void __init ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num) -{ - /* - * When SPI is used, we need to make sure that I2S is muxed off from - * SPI pins. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); - - ep93xx_spi_master_data =3D *info; - spi_register_board_info(devices, num); - platform_device_register(&ep93xx_spi_device); -} - -/************************************************************************* - * EP93xx LEDs - *************************************************************************/ -static const struct gpio_led ep93xx_led_pins[] __initconst =3D { - { - .name =3D "platform:grled", - }, { - .name =3D "platform:rdled", - }, -}; - -static const struct gpio_led_platform_data ep93xx_led_data __initconst =3D= { - .num_leds =3D ARRAY_SIZE(ep93xx_led_pins), - .leds =3D ep93xx_led_pins, -}; - -static struct gpiod_lookup_table ep93xx_leds_gpio_table =3D { - .dev_id =3D "leds-gpio", - .table =3D { - /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), - { } - }, -}; - -/************************************************************************* - * EP93xx pwm peripheral handling - *************************************************************************/ -static struct resource ep93xx_pwm0_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), -}; - -static struct platform_device ep93xx_pwm0_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm0_resource), - .resource =3D ep93xx_pwm0_resource, -}; - -static struct resource ep93xx_pwm1_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), -}; - -static struct platform_device ep93xx_pwm1_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm1_resource), - .resource =3D ep93xx_pwm1_resource, -}; - -void __init ep93xx_register_pwm(int pwm0, int pwm1) -{ - if (pwm0) - platform_device_register(&ep93xx_pwm0_device); - - /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ - if (pwm1) - platform_device_register(&ep93xx_pwm1_device); -} - -/************************************************************************* - * EP93xx video peripheral handling - *************************************************************************/ -static struct ep93xxfb_mach_info ep93xxfb_data; - -static struct resource ep93xx_fb_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), -}; - -static struct platform_device ep93xx_fb_device =3D { - .name =3D "ep93xx-fb", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xxfb_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_fb_device.dev.coherent_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_fb_resource), - .resource =3D ep93xx_fb_resource, -}; - -/* The backlight use a single register in the framebuffer's register space= */ -#define EP93XX_RASTER_REG_BRIGHTNESS 0x20 - -static struct resource ep93xx_bl_resources[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + - EP93XX_RASTER_REG_BRIGHTNESS, 0x04), -}; - -static struct platform_device ep93xx_bl_device =3D { - .name =3D "ep93xx-bl", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_bl_resources), - .resource =3D ep93xx_bl_resources, -}; - -/** - * ep93xx_register_fb - Register the framebuffer platform device. - * @data: platform specific framebuffer configuration (__initdata) - */ -void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) -{ - ep93xxfb_data =3D *data; - platform_device_register(&ep93xx_fb_device); - platform_device_register(&ep93xx_bl_device); -} - - -/************************************************************************* - * EP93xx matrix keypad peripheral handling - *************************************************************************/ -static struct ep93xx_keypad_platform_data ep93xx_keypad_data; - -static struct resource ep93xx_keypad_resource[] =3D { - DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), - DEFINE_RES_IRQ(IRQ_EP93XX_KEY), -}; - -static struct platform_device ep93xx_keypad_device =3D { - .name =3D "ep93xx-keypad", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_keypad_data, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_keypad_resource), - .resource =3D ep93xx_keypad_resource, -}; - -/** - * ep93xx_register_keypad - Register the keypad platform device. - * @data: platform specific keypad configuration (__initdata) - */ -void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *dat= a) -{ - ep93xx_keypad_data =3D *data; - platform_device_register(&ep93xx_keypad_device); -} - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ(IRQ_EP93XX_SAI), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -static struct platform_device ep93xx_pcm_device =3D { - .name =3D "ep93xx-pcm-audio", - .id =3D -1, -}; - -void __init ep93xx_register_i2s(void) -{ - platform_device_register(&ep93xx_i2s_device); - platform_device_register(&ep93xx_pcm_device); -} - -#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ - EP93XX_SYSCON_DEVCFG_I2SONAC97) - -#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ - EP93XX_SYSCON_I2SCLKDIV_SPOL) - -int ep93xx_i2s_acquire(void) -{ - unsigned val; - - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97, - EP93XX_SYSCON_DEVCFG_I2S_MASK); - - /* - * This is potentially racy with the clock api for i2s_mclk, sclk and=20 - * lrclk. Since the i2s driver is the only user of those clocks we - * rely on it to prevent parallel use of this function and the=20 - * clock api for the i2s clocks. - */ - val =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - val &=3D ~EP93XX_I2SCLKDIV_MASK; - val |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; - ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); - - return 0; -} -EXPORT_SYMBOL(ep93xx_i2s_acquire); - -void ep93xx_i2s_release(void) -{ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); -} -EXPORT_SYMBOL(ep93xx_i2s_release); - -/************************************************************************* - * EP93xx AC97 audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_ac97_resources[] =3D { - DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), - DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), -}; - -static struct platform_device ep93xx_ac97_device =3D { - .name =3D "ep93xx-ac97", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ac97_resources), - .resource =3D ep93xx_ac97_resources, -}; - -void __init ep93xx_register_ac97(void) -{ - /* - * Make sure that the AC97 pins are not used by I2S. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - - platform_device_register(&ep93xx_ac97_device); - platform_device_register(&ep93xx_pcm_device); -} - -/************************************************************************* - * EP93xx Watchdog - *************************************************************************/ -static struct resource ep93xx_wdt_resources[] =3D { - DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08), -}; - -static struct platform_device ep93xx_wdt_device =3D { - .name =3D "ep93xx-wdt", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_wdt_resources), - .resource =3D ep93xx_wdt_resources, -}; - -/************************************************************************* - * EP93xx IDE - *************************************************************************/ -static struct resource ep93xx_ide_resources[] =3D { - DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), - DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), -}; - -static struct platform_device ep93xx_ide_device =3D { - .name =3D "ep93xx-ide", - .id =3D -1, - .dev =3D { - .dma_mask =3D &ep93xx_ide_device.dev.coherent_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, - .num_resources =3D ARRAY_SIZE(ep93xx_ide_resources), - .resource =3D ep93xx_ide_resources, -}; - -void __init ep93xx_register_ide(void) -{ - platform_device_register(&ep93xx_ide_device); -} - -/************************************************************************* - * EP93xx ADC - *************************************************************************/ -static struct resource ep93xx_adc_resources[] =3D { - DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28), - DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH), -}; - -static struct platform_device ep93xx_adc_device =3D { - .name =3D "ep93xx-adc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_adc_resources), - .resource =3D ep93xx_adc_resources, -}; - -void __init ep93xx_register_adc(void) -{ - /* Power up ADC, deactivate Touch Screen Controller */ - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN, - EP93XX_SYSCON_DEVCFG_ADCPD); - - platform_device_register(&ep93xx_adc_device); -} - -/************************************************************************* - * EP93xx Security peripheral - *************************************************************************/ - -/* - * The Maverick Key is 256 bits of micro fuses blown at the factory during - * manufacturing to uniquely identify a part. - * - * See: http://arm.cirrus.com/forum/viewtopic.php?t=3D486&highlight=3Dmave= rick+key - */ -#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x)) -#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400) -#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410) -#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440) -#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450) -#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460) -#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500) -#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504) -#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520) -#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524) -#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700) -#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704) -#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708) -#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c) - -static char ep93xx_soc_id[33]; - -static const char __init *ep93xx_get_soc_id(void) -{ - unsigned int id, id2, id3, id4, id5; - - if (__raw_readl(EP93XX_SECURITY_UNIQVAL) !=3D 1) - return "bad Hamming code"; - - id =3D __raw_readl(EP93XX_SECURITY_UNIQID); - id2 =3D __raw_readl(EP93XX_SECURITY_UNIQID2); - id3 =3D __raw_readl(EP93XX_SECURITY_UNIQID3); - id4 =3D __raw_readl(EP93XX_SECURITY_UNIQID4); - id5 =3D __raw_readl(EP93XX_SECURITY_UNIQID5); - - if (id !=3D id2) - return "invalid"; - - /* Toss the unique ID into the entropy pool */ - add_device_randomness(&id2, 4); - add_device_randomness(&id3, 4); - add_device_randomness(&id4, 4); - add_device_randomness(&id5, 4); - - snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id), - "%08x%08x%08x%08x", id2, id3, id4, id5); - - return ep93xx_soc_id; -} - -static const char __init *ep93xx_get_soc_rev(void) -{ - int rev =3D ep93xx_chip_revision(); - - switch (rev) { - case EP93XX_CHIP_REV_D0: - return "D0"; - case EP93XX_CHIP_REV_D1: - return "D1"; - case EP93XX_CHIP_REV_E0: - return "E0"; - case EP93XX_CHIP_REV_E1: - return "E1"; - case EP93XX_CHIP_REV_E2: - return "E2"; - default: - return "unknown"; - } -} - -static const char __init *ep93xx_get_machine_name(void) -{ - return kasprintf(GFP_KERNEL,"%s", machine_desc->name); -} - -static struct device __init *ep93xx_init_soc(void) -{ - struct soc_device_attribute *soc_dev_attr; - struct soc_device *soc_dev; - - soc_dev_attr =3D kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return NULL; - - soc_dev_attr->machine =3D ep93xx_get_machine_name(); - soc_dev_attr->family =3D "Cirrus Logic EP93xx"; - soc_dev_attr->revision =3D ep93xx_get_soc_rev(); - soc_dev_attr->soc_id =3D ep93xx_get_soc_id(); - - soc_dev =3D soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->machine); - kfree(soc_dev_attr); - return NULL; - } - - return soc_device_to_device(soc_dev); -} - -struct device __init *ep93xx_init_devices(void) -{ - struct device *parent; - unsigned int i; - - /* Disallow access to MaverickCrunch initially */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); - - /* Default all ports to GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK | - EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - - parent =3D ep93xx_init_soc(); - - /* Get the GPIO working early, other devices need it */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) - platform_device_register(ep93xx_gpio_device[i]); - - amba_device_register(&uart1_device, &iomem_resource); - amba_device_register(&uart2_device, &iomem_resource); - amba_device_register(&uart3_device, &iomem_resource); - - platform_device_register(&ep93xx_rtc_device); - platform_device_register(&ep93xx_ohci_device); - platform_device_register(&ep93xx_wdt_device); - - gpiod_add_lookup_table(&ep93xx_leds_gpio_table); - gpio_led_register_device(-1, &ep93xx_led_data); - - return parent; -} - -void ep93xx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); - - while (1) - ; -} diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c deleted file mode 100644 index 74515acab8ef..000000000000 --- a/arch/arm/mach-ep93xx/dma.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/dma.c - * - * Platform support code for the EP93xx dmaengine driver. - * - * Copyright (C) 2011 Mika Westerberg - * - * This work is based on the original dma-m2p implementation with - * following copyrights: - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2006 Applied Data Systems - * Copyright (C) 2009 Ryan Mallon - */ - -#include -#include -#include -#include -#include -#include - -#include -#include "hardware.h" - -#include "soc.h" - -#define DMA_CHANNEL(_name, _base, _irq) \ - { .name =3D (_name), .base =3D (_base), .irq =3D (_irq) } - -/* - * DMA M2P channels. - * - * On the EP93xx chip the following peripherals my be allocated to the 10 - * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive). - * - * I2S contains 3 Tx and 3 Rx DMA Channels - * AAC contains 3 Tx and 3 Rx DMA Channels - * UART1 contains 1 Tx and 1 Rx DMA Channels - * UART2 contains 1 Tx and 1 Rx DMA Channels - * UART3 contains 1 Tx and 1 Rx DMA Channels - * IrDA contains 1 Tx and 1 Rx DMA Channels - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] =3D { - DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0), - DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1), - DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2), - DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3), - DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4), - DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5), - DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6), - DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7), - DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8), - DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data =3D { - .channels =3D ep93xx_dma_m2p_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2p_channels), -}; - -static u64 ep93xx_dma_m2p_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2p_device =3D { - .name =3D "ep93xx-dma-m2p", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2p_data, - .dma_mask =3D &ep93xx_dma_m2p_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -/* - * DMA M2M channels. - * - * There are 2 M2M channels which support memcpy/memset and in addition si= mple - * hardware requests from/to SSP and IDE. We do not implement an external - * hardware requests. - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] =3D { - DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0), - DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data =3D { - .channels =3D ep93xx_dma_m2m_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2m_channels), -}; - -static u64 ep93xx_dma_m2m_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2m_device =3D { - .name =3D "ep93xx-dma-m2m", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2m_data, - .dma_mask =3D &ep93xx_dma_m2m_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -static int __init ep93xx_dma_init(void) -{ - platform_device_register(&ep93xx_dma_m2p_device); - platform_device_register(&ep93xx_dma_m2m_device); - return 0; -} -arch_initcall(ep93xx_dma_init); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c deleted file mode 100644 index 356b0460c7ed..000000000000 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/edb93xx.c - * Cirrus Logic EDB93xx Development Board support. - * - * EDB93XX, EDB9301, EDB9307A - * Copyright (C) 2008-2009 H Hartley Sweeten - * - * EDB9302 - * Copyright (C) 2006 George Kashperko - * - * EDB9302A, EDB9315, EDB9315A - * Copyright (C) 2006 Lennert Buytenhek - * - * EDB9307 - * Copyright (C) 2007 Herbert Valerio Riedel - * - * EDB9312 - * Copyright (C) 2006 Infosys Technologies Limited - * Toufeeq Hussain - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -static void __init edb93xx_register_flash(void) -{ - if (machine_is_edb9307() || machine_is_edb9312() || - machine_is_edb9315()) { - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - } else { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } -} - -static struct ep93xx_eth_data __initdata edb93xx_eth_data =3D { - .phy_id =3D 1, -}; - - -/************************************************************************* - * EDB93xx i2c peripheral handling - *************************************************************************/ - -static struct i2c_board_info __initdata edb93xxa_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - }, -}; - -static struct i2c_board_info __initdata edb93xx_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static void __init edb93xx_register_i2c(void) -{ - if (machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()) { - ep93xx_register_i2c(edb93xxa_i2c_board_info, - ARRAY_SIZE(edb93xxa_i2c_board_info)); - } else if (machine_is_edb9302() || machine_is_edb9307() - || machine_is_edb9312() || machine_is_edb9315()) { - ep93xx_register_i2c(edb93xx_i2c_board_info, - ARRAY_SIZE(edb93xx_i2c_board_info)); - } -} - - -/************************************************************************* - * EDB93xx SPI peripheral handling - *************************************************************************/ -static struct cs4271_platform_data edb93xx_cs4271_data =3D { - /* Intentionally left blank */ -}; - -static struct spi_board_info edb93xx_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &edb93xx_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info edb93xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static struct gpiod_lookup_table edb93xx_cs4272_edb9301_gpio_table =3D { - .dev_id =3D "spi0.0", /* CS0 on SPI0 */ - .table =3D { - GPIO_LOOKUP("A", 1, "reset", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct gpiod_lookup_table edb93xx_cs4272_edb9302_gpio_table =3D { - .dev_id =3D "spi0.0", /* CS0 on SPI0 */ - .table =3D { - GPIO_LOOKUP("H", 2, "reset", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct gpiod_lookup_table edb93xx_cs4272_edb9315_gpio_table =3D { - .dev_id =3D "spi0.0", /* CS0 on SPI0 */ - .table =3D { - GPIO_LOOKUP("B", 6, "reset", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static void __init edb93xx_register_spi(void) -{ - if (machine_is_edb9301() || machine_is_edb9302()) - gpiod_add_lookup_table(&edb93xx_cs4272_edb9301_gpio_table); - else if (machine_is_edb9302a() || machine_is_edb9307a()) - gpiod_add_lookup_table(&edb93xx_cs4272_edb9302_gpio_table); - else if (machine_is_edb9315a()) - gpiod_add_lookup_table(&edb93xx_cs4272_edb9315_gpio_table); - - gpiod_add_lookup_table(&edb93xx_spi_cs_gpio_table); - ep93xx_register_spi(&edb93xx_spi_info, edb93xx_spi_board_info, - ARRAY_SIZE(edb93xx_spi_board_info)); -} - - -/************************************************************************* - * EDB93xx I2S - *************************************************************************/ -static struct platform_device edb93xx_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static int __init edb93xx_has_audio(void) -{ - return (machine_is_edb9301() || machine_is_edb9302() || - machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()); -} - -static void __init edb93xx_register_i2s(void) -{ - if (edb93xx_has_audio()) { - ep93xx_register_i2s(); - platform_device_register(&edb93xx_audio_device); - } -} - - -/************************************************************************* - * EDB93xx pwm - *************************************************************************/ -static void __init edb93xx_register_pwm(void) -{ - if (machine_is_edb9301() || - machine_is_edb9302() || machine_is_edb9302a()) { - /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */ - ep93xx_register_pwm(0, 1); - } else if (machine_is_edb9307() || machine_is_edb9307a()) { - /* EP9307 only has pwm.0 (PWMOUT) */ - ep93xx_register_pwm(1, 0); - } else { - /* EP9312 and EP9315 have both */ - ep93xx_register_pwm(1, 1); - } -} - - -/************************************************************************* - * EDB93xx framebuffer - *************************************************************************/ -static struct ep93xxfb_mach_info __initdata edb93xxfb_info =3D { - .flags =3D 0, -}; - -static int __init edb93xx_has_fb(void) -{ - /* These platforms have an ep93xx with video capability */ - return machine_is_edb9307() || machine_is_edb9307a() || - machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_fb(void) -{ - if (!edb93xx_has_fb()) - return; - - if (machine_is_edb9307a() || machine_is_edb9315a()) - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN0; - else - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN3; - - ep93xx_register_fb(&edb93xxfb_info); -} - - -/************************************************************************* - * EDB93xx IDE - *************************************************************************/ -static int __init edb93xx_has_ide(void) -{ - /* - * Although EDB9312 and EDB9315 do have IDE capability, they have - * INTRQ line wired as pull-up, which makes using IDE interface - * problematic. - */ - return machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_ide(void) -{ - if (!edb93xx_has_ide()) - return; - - ep93xx_register_ide(); -} - - -static void __init edb93xx_init_machine(void) -{ - ep93xx_init_devices(); - edb93xx_register_flash(); - ep93xx_register_eth(&edb93xx_eth_data, 1); - edb93xx_register_i2c(); - edb93xx_register_spi(); - edb93xx_register_i2s(); - edb93xx_register_pwm(); - edb93xx_register_fb(); - edb93xx_register_ide(); - ep93xx_register_adc(); -} - - -#ifdef CONFIG_MACH_EDB9301 -MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302 -MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") - /* Maintainer: George Kashperko */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302A -MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307 -MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") - /* Maintainer: Herbert Valerio Riedel */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307A -MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9312 -MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") - /* Maintainer: Toufeeq Hussain */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315 -MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315A -MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ep93xx/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93= xx-regs.h deleted file mode 100644 index 8fa3646de0a4..000000000000 --- a/arch/arm/mach-ep93xx/ep93xx-regs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_EP93XX_REGS_H -#define __ASM_ARCH_EP93XX_REGS_H - -/* - * EP93xx linux memory map: - * - * virt phys size - * fe800000 5M per-platform mappings - * fed00000 80800000 2M APB - * fef00000 80000000 1M AHB - */ - -#define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 -#define EP93XX_AHB_SIZE 0x00100000 - -#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) -#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) - -#define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 -#define EP93XX_APB_SIZE 0x00200000 - -#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) -#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) - -/* APB UARTs */ -#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) -#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) - -#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) -#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) - -#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) -#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) - -#endif diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio= -ep93xx.h deleted file mode 100644 index 7b46eb7e5507..000000000000 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Include file for the EP93XX GPIO controller machine specifics */ - -#ifndef __GPIO_EP93XX_H -#define __GPIO_EP93XX_H - -#include "ep93xx-regs.h" - -#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) -#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) -#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) -#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) -#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) -#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) - -/* GPIO port A. */ -#define EP93XX_GPIO_LINE_A(x) ((x) + 0) -#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) -#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) -#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) -#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) -#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) -#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) -#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) -#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) - -/* GPIO port B. */ -#define EP93XX_GPIO_LINE_B(x) ((x) + 8) -#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) -#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) -#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) -#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) -#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) -#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) -#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) -#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) - -/* GPIO port C. */ -#define EP93XX_GPIO_LINE_C(x) ((x) + 40) -#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) -#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) -#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) -#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) -#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) -#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) -#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) -#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) - -/* GPIO port D. */ -#define EP93XX_GPIO_LINE_D(x) ((x) + 24) -#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) -#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) -#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) -#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) -#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) -#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) -#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) -#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) - -/* GPIO port E. */ -#define EP93XX_GPIO_LINE_E(x) ((x) + 32) -#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) -#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) -#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) -#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) -#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) -#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) -#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) -#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) - -/* GPIO port F. */ -#define EP93XX_GPIO_LINE_F(x) ((x) + 16) -#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) -#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) -#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) -#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) -#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) -#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) -#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) -#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) - -/* GPIO port G. */ -#define EP93XX_GPIO_LINE_G(x) ((x) + 48) -#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) -#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) -#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) -#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) -#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) -#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) -#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) -#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) - -/* GPIO port H. */ -#define EP93XX_GPIO_LINE_H(x) ((x) + 56) -#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) -#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) -#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) -#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) -#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) -#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) -#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) -#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) - -/* maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) - -/* maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) - -#endif /* __GPIO_EP93XX_H */ diff --git a/arch/arm/mach-ep93xx/hardware.h b/arch/arm/mach-ep93xx/hardwar= e.h deleted file mode 100644 index e7d850e04782..000000000000 --- a/arch/arm/mach-ep93xx/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/hardware.h - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "platform.h" - -/* - * The EP93xx has two external crystal oscillators. To generate the - * required high-frequency clocks, the processor uses two phase-locked- - * loops (PLLs) to multiply the incoming external clock signal to much - * higher frequencies that are then divided down by programmable dividers - * to produce the needed clocks. The PLLs operate independently of one - * another. - */ -#define EP93XX_EXT_CLK_RATE 14745600 -#define EP93XX_EXT_RTC_RATE 32768 - -#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) -#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) - -#endif diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h deleted file mode 100644 index 353201b90c66..000000000000 --- a/arch/arm/mach-ep93xx/irqs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_EP93XX_VIC0 1 - -#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) -#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) -#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) -#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) -#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) -#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) -#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) -#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) -#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) -#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) -#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) -#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) -#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) -#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) -#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) -#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) -#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) -#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) -#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) -#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) -#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) -#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) -#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) -#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) -#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) -#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) -#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) -#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) -#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) -#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc - -#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) - -#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) -#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) -#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) -#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) -#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) -#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) -#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) -#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) -#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) -#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) -#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) -#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) -#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) -#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) -#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) -#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) -#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) -#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) -#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) -#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) -#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) -#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) -#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) -#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) -#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) -#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) -#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) -#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) -#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) -#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff - -#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) - -#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) -#define EP93XX_BOARD_IRQS 32 - -#endif diff --git a/arch/arm/mach-ep93xx/platform.h b/arch/arm/mach-ep93xx/platfor= m.h deleted file mode 100644 index 5fb1b919133f..000000000000 --- a/arch/arm/mach-ep93xx/platform.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/platform.h - */ - -#ifndef __ASSEMBLY__ - -#include -#include - -struct device; -struct i2c_board_info; -struct spi_board_info; -struct platform_device; -struct ep93xxfb_mach_info; -struct ep93xx_keypad_platform_data; -struct ep93xx_spi_info; - -void ep93xx_map_io(void); -void ep93xx_init_irq(void); - -void ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size); - -void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); -void ep93xx_register_i2c(struct i2c_board_info *devices, int num); -void ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num); -void ep93xx_register_fb(struct ep93xxfb_mach_info *data); -void ep93xx_register_pwm(int pwm0, int pwm1); -void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data); -void ep93xx_register_i2s(void); -void ep93xx_register_ac97(void); -void ep93xx_register_ide(void); -void ep93xx_register_adc(void); - -struct device *ep93xx_init_devices(void); -extern void ep93xx_timer_init(void); - -void ep93xx_restart(enum reboot_mode, const char *); - -#endif diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h deleted file mode 100644 index 3245ebbd5069..000000000000 --- a/arch/arm/mach-ep93xx/soc.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ep93xx/soc.h - * - * Copyright (C) 2012 Open Kernel Labs - * Copyright (C) 2012 Ryan Mallon - */ - -#ifndef _EP93XX_SOC_H -#define _EP93XX_SOC_H - -#include "ep93xx-regs.h" -#include "irqs.h" - -/* - * EP93xx Physical Memory Map: - * - * The ASDO pin is sampled at system reset to select a synchronous or - * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up) - * the synchronous boot mode is selected. When ASDO is "0" (i.e - * pulled-down) the asynchronous boot mode is selected. - * - * In synchronous boot mode nSDCE3 is decoded starting at physical address - * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous - * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3 - * decoded at 0xf0000000. - * - * There is known errata for the EP93xx dealing with External Memory - * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design - * Guidelines" for more information. This document can be found at: - * - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - -#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin =3D 0 */ -#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin =3D 1 */ -#define EP93XX_CS1_PHYS_BASE 0x10000000 -#define EP93XX_CS2_PHYS_BASE 0x20000000 -#define EP93XX_CS3_PHYS_BASE 0x30000000 -#define EP93XX_PCMCIA_PHYS_BASE 0x40000000 -#define EP93XX_CS6_PHYS_BASE 0x60000000 -#define EP93XX_CS7_PHYS_BASE 0x70000000 -#define EP93XX_SDCE0_PHYS_BASE 0xc0000000 -#define EP93XX_SDCE1_PHYS_BASE 0xd0000000 -#define EP93XX_SDCE2_PHYS_BASE 0xe0000000 -#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin =3D 0 */ -#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin =3D 1 */ - -/* AHB peripherals */ -#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) - -#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000) -#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) - -#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000) -#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) - -#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000) -#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) - -#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) - -#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) - -#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) - -#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) - -#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000) -#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) - -#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) - -#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) - -/* APB peripherals */ -#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) - -#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000) -#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) - -#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) - -#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) -#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) - -#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) -#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) - -#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) - -#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000) -#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) - -#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000) -#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) -#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) - -#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000) -#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) - -#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000) -#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) - -#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000) -#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) - -/* System controller */ -#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000) -#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) -#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) -#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) -#define EP93XX_SYSCON_PWRCNT_USH_EN 28 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 -#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) -#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) -#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23) -#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19) -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18) -#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29) -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28) -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27) -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26) -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25) -#define EP93XX_SYSCON_DEVCFG_U3EN 24 -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) -#define EP93XX_SYSCON_DEVCFG_U2EN 20 -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) -#define EP93XX_SYSCON_DEVCFG_U1EN 18 -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17) -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13) -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12) -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11) -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10) -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9) -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8) -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7) -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6) -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4) -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3) -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2) -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) -#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) -#define EP93XX_SYSCON_CLKDIV_ENABLE 15 -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) -#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 -#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) -#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) -#define EP93XX_I2SCLKDIV_SDIV (1 << 16) -#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) -#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) -#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) -#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) -#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) -#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) -#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) -#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8) -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7) -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6) -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5) -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4) -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3) -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1) -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0) -#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) - -/* EP93xx System Controller software locked register write */ -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); - -static inline void ep93xx_devcfg_set_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(bits, 0x00); -} - -static inline void ep93xx_devcfg_clear_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(0x00, bits); -} - -#endif /* _EP93XX_SOC_H */ diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/tim= er-ep93xx.c deleted file mode 100644 index a9efa7bc2fa1..000000000000 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "soc.h" -#include "platform.h" - -/************************************************************************* - * Timer handling for EP93xx - ************************************************************************* - * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and - * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate - * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, - * is free-running, and can't generate interrupts. - * - * The 508 kHz timers are ideal for use for the timer interrupt, as the - * most common values of HZ divide 508 kHz nicely. We pick the 32 bit - * timer (timer 3) to get as long sleep intervals as possible when using - * CONFIG_NO_HZ. - * - * The higher clock rate of timer 4 makes it a better choice than the - * other timers for use as clock source and for sched_clock(), providing - * a stable 40 bit time base. - ************************************************************************* - */ -#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) -#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) -#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) -#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) -#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) -#define EP93XX_TIMER123_CONTROL_MODE (1 << 6) -#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) -#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) -#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) -#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) -#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) -#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) -#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) -#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) -#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) -#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) -#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) -#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) -#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) - -#define EP93XX_TIMER123_RATE 508469 -#define EP93XX_TIMER4_RATE 983040 - -static u64 notrace ep93xx_read_sched_clock(void) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return ret; -} - -static u64 ep93xx_clocksource_read(struct clocksource *c) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return (u64) ret; -} - -static int ep93xx_clkevt_set_next_event(unsigned long next, - struct clock_event_device *evt) -{ - /* Default mode: periodic, off, 508 kHz */ - u32 tmode =3D EP93XX_TIMER123_CONTROL_MODE | - EP93XX_TIMER123_CONTROL_CLKSEL; - - /* Clear timer */ - writel(tmode, EP93XX_TIMER3_CONTROL); - - /* Set next event */ - writel(next, EP93XX_TIMER3_LOAD); - writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER3_CONTROL); - return 0; -} - - -static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) -{ - /* Disable timer */ - writel(0, EP93XX_TIMER3_CONTROL); - - return 0; -} - -static struct clock_event_device ep93xx_clockevent =3D { - .name =3D "timer1", - .features =3D CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown =3D ep93xx_clkevt_shutdown, - .set_state_oneshot =3D ep93xx_clkevt_shutdown, - .tick_resume =3D ep93xx_clkevt_shutdown, - .set_next_event =3D ep93xx_clkevt_set_next_event, - .rating =3D 300, -}; - -static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt =3D dev_id; - - /* Writing any value clears the timer interrupt */ - writel(1, EP93XX_TIMER3_CLEAR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -void __init ep93xx_timer_init(void) -{ - int irq =3D IRQ_EP93XX_TIMER3; - unsigned long flags =3D IRQF_TIMER | IRQF_IRQPOLL; - - /* Enable and register clocksource and sched_clock on timer 4 */ - writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); - clocksource_mmio_init(NULL, "timer4", - EP93XX_TIMER4_RATE, 200, 40, - ep93xx_clocksource_read); - sched_clock_register(ep93xx_read_sched_clock, 40, - EP93XX_TIMER4_RATE); - - /* Set up clockevent on timer 3 */ - if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", - &ep93xx_clockevent)) - pr_err("Failed to request irq %d (ep93xx timer)\n", irq); - clockevents_config_and_register(&ep93xx_clockevent, - EP93XX_TIMER123_RATE, - 1, - 0xffffffffU); -} diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c deleted file mode 100644 index 0bbdf587c685..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/ts72xx.c - * Technologic Systems TS72xx SBC support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gpio-ep93xx.h" -#include "hardware.h" - -#include -#include -#include - -#include "soc.h" -#include "ts72xx.h" - -/************************************************************************* - * IO map - *************************************************************************/ -static struct map_desc ts72xx_io_desc[] __initdata =3D { - { - .virtual =3D (unsigned long)TS72XX_MODEL_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), - .length =3D TS72XX_MODEL_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), - .length =3D TS72XX_OPTIONS_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), - .length =3D TS72XX_OPTIONS2_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_CPLDVER_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_CPLDVER_PHYS_BASE), - .length =3D TS72XX_CPLDVER_SIZE, - .type =3D MT_DEVICE, - } -}; - -static void __init ts72xx_map_io(void) -{ - ep93xx_map_io(); - iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); -} - - -/************************************************************************* - * NAND flash - *************************************************************************/ -#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ -#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ - -static void ts72xx_nand_hwcontrol(struct nand_chip *chip, - int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - unsigned char bits; - - addr +=3D (1 << TS72XX_NAND_CONTROL_ADDR_LINE); - - bits =3D __raw_readb(addr) & ~0x07; - bits |=3D (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ - bits |=3D (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ - bits |=3D (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ - - __raw_writeb(bits, addr); - } - - if (cmd !=3D NAND_CMD_NONE) - __raw_writeb(cmd, chip->legacy.IO_ADDR_W); -} - -static int ts72xx_nand_device_ready(struct nand_chip *chip) -{ - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - - addr +=3D (1 << TS72XX_NAND_BUSY_ADDR_LINE); - - return !!(__raw_readb(addr) & 0x20); -} - -#define TS72XX_BOOTROM_PART_SIZE (SZ_16K) -#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M) - -static struct mtd_partition ts72xx_nand_parts[] =3D { - { - .name =3D "TS-BOOTROM", - .offset =3D 0, - .size =3D TS72XX_BOOTROM_PART_SIZE, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, { - .name =3D "Linux", - .offset =3D MTDPART_OFS_RETAIN, - .size =3D TS72XX_REDBOOT_PART_SIZE, - /* leave so much for last partition */ - }, { - .name =3D "RedBoot", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, -}; - -static struct platform_nand_data ts72xx_nand_data =3D { - .chip =3D { - .nr_chips =3D 1, - .chip_offset =3D 0, - .chip_delay =3D 15, - }, - .ctrl =3D { - .cmd_ctrl =3D ts72xx_nand_hwcontrol, - .dev_ready =3D ts72xx_nand_device_ready, - }, -}; - -static struct resource ts72xx_nand_resource[] =3D { - { - .start =3D 0, /* filled in later */ - .end =3D 0, /* filled in later */ - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts72xx_nand_flash =3D { - .name =3D "gen_nand", - .id =3D -1, - .dev.platform_data =3D &ts72xx_nand_data, - .resource =3D ts72xx_nand_resource, - .num_resources =3D ARRAY_SIZE(ts72xx_nand_resource), -}; - -static void __init ts72xx_register_flash(struct mtd_partition *parts, int = n, - resource_size_t start) -{ - /* - * TS7200 has NOR flash all other TS72xx board have NAND flash. - */ - if (board_is_ts7200()) { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } else { - ts72xx_nand_resource[0].start =3D start; - ts72xx_nand_resource[0].end =3D start + SZ_16M - 1; - - ts72xx_nand_data.chip.partitions =3D parts; - ts72xx_nand_data.chip.nr_partitions =3D n; - - platform_device_register(&ts72xx_nand_flash); - } -} - -/************************************************************************* - * RTC M48T86 - *************************************************************************/ -#define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000) -#define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000) - -static struct resource ts72xx_rtc_resources[] =3D { - DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_rtc_device =3D { - .name =3D "rtc-m48t86", - .id =3D -1, - .resource =3D ts72xx_rtc_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_rtc_resources), -}; - -/************************************************************************* - * Watchdog (in CPLD) - *************************************************************************/ -#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) -#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) - -static struct resource ts72xx_wdt_resources[] =3D { - DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_wdt_device =3D { - .name =3D "ts72xx-wdt", - .id =3D -1, - .resource =3D ts72xx_wdt_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_wdt_resources), -}; - -/************************************************************************* - * ETH - *************************************************************************/ -static struct ep93xx_eth_data __initdata ts72xx_eth_data =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -#define BK3_EN_SDCARD_PHYS_BASE 0x12400000 -#define BK3_EN_SDCARD_PWR 0x0 -#define BK3_DIS_SDCARD_PWR 0x0C -static void bk3_mmc_spi_setpower(struct device *dev, unsigned int vdd) -{ - void __iomem *pwr_sd =3D ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K); - - if (!pwr_sd) { - pr_err("Failed to enable SD card power!"); - return; - } - - pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__, - !!vdd ? "ON" : "OFF", vdd); - - if (!!vdd) - __raw_writeb(BK3_EN_SDCARD_PWR, pwr_sd); - else - __raw_writeb(BK3_DIS_SDCARD_PWR, pwr_sd); - - iounmap(pwr_sd); -} - -static struct mmc_spi_platform_data bk3_spi_mmc_data =3D { - .detect_delay =3D 500, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps =3D MMC_CAP_NONREMOVABLE, - .setpower =3D bk3_mmc_spi_setpower, -}; - -/************************************************************************* - * SPI Bus - SD card access - *************************************************************************/ -static struct spi_board_info bk3_spi_board_info[] __initdata =3D { - { - .modalias =3D "mmc_spi", - .platform_data =3D &bk3_spi_mmc_data, - .max_speed_hz =3D 7.4E6, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_0, - }, -}; - -/* - * This is a stub -> the FGPIO[3] pin is not connected on the schematic - * The all work is performed automatically by !SPI_FRAME (SFRM1) and - * goes through CPLD - */ -static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info bk3_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * TS72XX support code - *************************************************************************/ -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - -/* Relative to EP93XX_CS1_PHYS_BASE */ -#define TS73XX_FPGA_LOADER_BASE 0x03c00000 - -static struct resource ts73xx_fpga_resources[] =3D { - { - .start =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE, - .end =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts73xx_fpga_device =3D { - .name =3D "ts73xx-fpga-mgr", - .id =3D -1, - .resource =3D ts73xx_fpga_resources, - .num_resources =3D ARRAY_SIZE(ts73xx_fpga_resources), -}; - -#endif - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info ts72xx_spi_devices[] __initdata =3D { - { - .modalias =3D "tmp122", - .max_speed_hz =3D 2 * 1000 * 1000, - .bus_num =3D 0, - .chip_select =3D 0, - }, -}; - -static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - /* DIO_17 */ - GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info ts72xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static void __init ts72xx_init_machine(void) -{ - ep93xx_init_devices(); - ts72xx_register_flash(ts72xx_nand_parts, ARRAY_SIZE(ts72xx_nand_parts), - is_ts9420_installed() ? - EP93XX_CS7_PHYS_BASE : EP93XX_CS6_PHYS_BASE); - platform_device_register(&ts72xx_rtc_device); - platform_device_register(&ts72xx_wdt_device); - - ep93xx_register_eth(&ts72xx_eth_data, 1); -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - if (board_is_ts7300()) - platform_device_register(&ts73xx_fpga_device); -#endif - gpiod_add_lookup_table(&ts72xx_spi_cs_gpio_table); - ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, - ARRAY_SIZE(ts72xx_spi_devices)); -} - -MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D ts72xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ_NAMED(IRQ_EP93XX_SAI, "spilink i2s slave"), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-spilink-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -/************************************************************************* - * BK3 support code - *************************************************************************/ -static struct mtd_partition bk3_nand_parts[] =3D { - { - .name =3D "System", - .offset =3D 0x00000000, - .size =3D 0x01e00000, - }, { - .name =3D "Data", - .offset =3D 0x01e00000, - .size =3D 0x05f20000 - }, { - .name =3D "RedBoot", - .offset =3D 0x07d20000, - .size =3D 0x002e0000, - .mask_flags =3D MTD_WRITEABLE, /* force RO */ - }, -}; - -static void __init bk3_init_machine(void) -{ - ep93xx_init_devices(); - - ts72xx_register_flash(bk3_nand_parts, ARRAY_SIZE(bk3_nand_parts), - EP93XX_CS6_PHYS_BASE); - - ep93xx_register_eth(&ts72xx_eth_data, 1); - - gpiod_add_lookup_table(&bk3_spi_cs_gpio_table); - ep93xx_register_spi(&bk3_spi_master, bk3_spi_board_info, - ARRAY_SIZE(bk3_spi_board_info)); - - /* Configure ep93xx's I2S to use AC97 pins */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - platform_device_register(&ep93xx_i2s_device); -} - -MACHINE_START(BK3, "Liebherr controller BK3.1") - /* Maintainer: Lukasz Majewski */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D bk3_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h deleted file mode 100644 index 00b4941d29c9..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ts72xx.h - */ - -/* - * TS72xx memory map: - * - * virt phys size - * febff000 22000000 4K model number register (bits 0-2) - * febfe000 22400000 4K options register - * febfd000 22800000 4K options register #2 - * febfc000 23400000 4K CPLD version register - */ - -#ifndef __TS72XX_H_ -#define __TS72XX_H_ - -#define TS72XX_MODEL_PHYS_BASE 0x22000000 -#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) -#define TS72XX_MODEL_SIZE 0x00001000 - -#define TS72XX_MODEL_TS7200 0x00 -#define TS72XX_MODEL_TS7250 0x01 -#define TS72XX_MODEL_TS7260 0x02 -#define TS72XX_MODEL_TS7300 0x03 -#define TS72XX_MODEL_TS7400 0x04 -#define TS72XX_MODEL_MASK 0x07 - - -#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 -#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) -#define TS72XX_OPTIONS_SIZE 0x00001000 - -#define TS72XX_OPTIONS_COM2_RS485 0x02 -#define TS72XX_OPTIONS_MAX197 0x01 - - -#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 -#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) -#define TS72XX_OPTIONS2_SIZE 0x00001000 - -#define TS72XX_OPTIONS2_TS9420 0x04 -#define TS72XX_OPTIONS2_TS9420_BOOT 0x02 - -#define TS72XX_CPLDVER_PHYS_BASE 0x23400000 -#define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000) -#define TS72XX_CPLDVER_SIZE 0x00001000 - -#ifndef __ASSEMBLY__ - -static inline int ts72xx_model(void) -{ - return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK; -} - -static inline int board_is_ts7200(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7200; -} - -static inline int board_is_ts7250(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7250; -} - -static inline int board_is_ts7260(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7260; -} - -static inline int board_is_ts7300(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7300; -} - -static inline int board_is_ts7400(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7400; -} - -static inline int is_max197_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) & - TS72XX_OPTIONS_MAX197); -} - -static inline int is_ts9420_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & - TS72XX_OPTIONS2_TS9420); -} -#endif -#endif /* __TS72XX_H_ */ diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c deleted file mode 100644 index b3087b8eed3f..000000000000 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/vision_ep9307.c - * Vision Engraving Systems EP9307 SoM support. - * - * Copyright (C) 2008-2011 Vision Engraving Systems - * H Hartley Sweeten - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include -#include - -#include "soc.h" - -/************************************************************************* - * Static I/O mappings for the FPGA - *************************************************************************/ -#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE -#define VISION_VIRT_BASE 0xfebff000 - -static struct map_desc vision_io_desc[] __initdata =3D { - { - .virtual =3D VISION_VIRT_BASE, - .pfn =3D __phys_to_pfn(VISION_PHYS_BASE), - .length =3D SZ_4K, - .type =3D MT_DEVICE, - }, -}; - -static void __init vision_map_io(void) -{ - ep93xx_map_io(); - - iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc)); -} - -/************************************************************************* - * Ethernet - *************************************************************************/ -static struct ep93xx_eth_data vision_eth_data __initdata =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * Framebuffer - *************************************************************************/ -#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1 - -static int vision_lcd_setup(struct platform_device *pdev) -{ - int err; - - err =3D gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH, - dev_name(&pdev->dev)); - if (err) - return err; - - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS | - EP93XX_SYSCON_DEVCFG_RASONP3 | - EP93XX_SYSCON_DEVCFG_EXVC); - - return 0; -} - -static void vision_lcd_teardown(struct platform_device *pdev) -{ - gpio_free(VISION_LCD_ENABLE); -} - -static void vision_lcd_blank(int blank_mode, struct fb_info *info) -{ - if (blank_mode) - gpio_set_value(VISION_LCD_ENABLE, 0); - else - gpio_set_value(VISION_LCD_ENABLE, 1); -} - -static struct ep93xxfb_mach_info ep93xxfb_info __initdata =3D { - .flags =3D EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, - .setup =3D vision_lcd_setup, - .teardown =3D vision_lcd_teardown, - .blank =3D vision_lcd_blank, -}; - - -/************************************************************************* - * GPIO Expanders - *************************************************************************/ -#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1) -#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16) -#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16) -#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16) - -static struct pca953x_platform_data pca953x_74_gpio_data =3D { - .gpio_base =3D PCA9539_74_GPIO_BASE, - .irq_base =3D EP93XX_BOARD_IRQ(0), -}; - -static struct pca953x_platform_data pca953x_75_gpio_data =3D { - .gpio_base =3D PCA9539_75_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_76_gpio_data =3D { - .gpio_base =3D PCA9539_76_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_77_gpio_data =3D { - .gpio_base =3D PCA9539_77_GPIO_BASE, - .irq_base =3D -1, -}; - -/************************************************************************* - * I2C Bus - *************************************************************************/ - -static struct i2c_board_info vision_i2c_info[] __initdata =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - .irq =3D IRQ_EP93XX_EXT1, - }, { - I2C_BOARD_INFO("pca9539", 0x74), - .platform_data =3D &pca953x_74_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x75), - .platform_data =3D &pca953x_75_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x76), - .platform_data =3D &pca953x_76_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x77), - .platform_data =3D &pca953x_77_gpio_data, - }, -}; - -/************************************************************************* - * SPI CS4271 Audio Codec - *************************************************************************/ -static struct cs4271_platform_data vision_cs4271_data =3D { - /* Intentionally left blank */ -}; - -/************************************************************************* - * SPI Flash - *************************************************************************/ -static struct mtd_partition vision_spi_flash_partitions[] =3D { - { - .name =3D "SPI bootstrap", - .offset =3D 0, - .size =3D SZ_4K, - }, { - .name =3D "Bootstrap config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D SZ_4K, - }, { - .name =3D "System config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data vision_spi_flash_data =3D { - .name =3D "SPI Flash", - .parts =3D vision_spi_flash_partitions, - .nr_parts =3D ARRAY_SIZE(vision_spi_flash_partitions), -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -static struct mmc_spi_platform_data vision_spi_mmc_data =3D { - .detect_delay =3D 100, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps2 =3D MMC_CAP2_RO_ACTIVE_HIGH, -}; - -static struct gpiod_lookup_table vision_spi_mmc_gpio_table =3D { - .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ - .table =3D { - /* Card detect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), - /* Write protect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info vision_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &vision_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "sst25l", - .platform_data =3D &vision_spi_flash_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 1, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "mmc_spi", - .platform_data =3D &vision_spi_mmc_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 2, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table vision_spi_cs4271_gpio_table =3D { - .dev_id =3D "spi0.0", /* cs4271 @ CS0 */ - .table =3D { - /* RESET */ - GPIO_LOOKUP_IDX("H", 2, NULL, 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info vision_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * I2S Audio - *************************************************************************/ -static struct platform_device vision_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static void __init vision_register_i2s(void) -{ - ep93xx_register_i2s(); - platform_device_register(&vision_audio_device); -} - -/************************************************************************* - * Machine Initialization - *************************************************************************/ -static void __init vision_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M); - ep93xx_register_eth(&vision_eth_data, 1); - ep93xx_register_fb(&ep93xxfb_info); - ep93xx_register_pwm(1, 0); - - /* - * Request the gpio expander's interrupt gpio line now to prevent - * the kernel from doing a WARN in gpiolib:gpio_ensure_requested(). - */ - if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN, - "pca9539:74")) - pr_warn("cannot request interrupt gpio for pca9539:74\n"); - - vision_i2c_info[1].irq =3D gpio_to_irq(EP93XX_GPIO_LINE_F(7)); - - ep93xx_register_i2c(vision_i2c_info, - ARRAY_SIZE(vision_i2c_info)); - gpiod_add_lookup_table(&vision_spi_cs4271_gpio_table); - gpiod_add_lookup_table(&vision_spi_mmc_gpio_table); - gpiod_add_lookup_table(&vision_spi_cs_gpio_table); - ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, - ARRAY_SIZE(vision_spi_board_info)); - vision_register_i2s(); -} - -MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, - .map_io =3D vision_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D vision_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END diff --git a/include/linux/platform_data/spi-ep93xx.h b/include/linux/platf= orm_data/spi-ep93xx.h deleted file mode 100644 index b439f2a896e0..000000000000 --- a/include/linux/platform_data/spi-ep93xx.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_EP93XX_SPI_H -#define __ASM_MACH_EP93XX_SPI_H - -struct spi_device; - -/** - * struct ep93xx_spi_info - EP93xx specific SPI descriptor - * @use_dma: use DMA for the transfers - */ -struct ep93xx_spi_info { - bool use_dma; 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Mon, 15 Jul 2024 08:40:05 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:40 +0300 Subject: [PATCH v11 36/38] ARM: ep93xx: soc: drop defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-36-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Nikita Shubin , Linus Walleij , Sergey Shtylyov , Damien Le Moal , Dmitry Torokhov Cc: Stephen Boyd , Andy Shevchenko , linux-kernel@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=3028; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=u3BDqN+H6aRDKVd8/5dcTI5HxRCeHm2XLxf66dN+WRE=; b=L7s9kq1rV0SIT1C2Nf09QyQHffDJr3iZZALqn4PJyxyBgdIoJ+Vbgzn9HSoRsy1AOZ+pUYO8Wj85 +OJfWk3ABUdjFq8o3gwjfIg0imOfa5wFpK0GaWB+3+bAp2+cyFJ3 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Remove unnecessary defines, as we dropped board files. Signed-off-by: Nikita Shubin --- include/linux/platform_data/eth-ep93xx.h | 10 --------- include/linux/platform_data/keypad-ep93xx.h | 32 -------------------------= ---- include/linux/soc/cirrus/ep93xx.h | 13 ------------ 3 files changed, 55 deletions(-) diff --git a/include/linux/platform_data/eth-ep93xx.h b/include/linux/platf= orm_data/eth-ep93xx.h deleted file mode 100644 index 8eef637a804d..000000000000 --- a/include/linux/platform_data/eth-ep93xx.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_PLATFORM_DATA_ETH_EP93XX -#define _LINUX_PLATFORM_DATA_ETH_EP93XX - -struct ep93xx_eth_data { - unsigned char dev_addr[6]; - unsigned char phy_id; -}; - -#endif diff --git a/include/linux/platform_data/keypad-ep93xx.h b/include/linux/pl= atform_data/keypad-ep93xx.h deleted file mode 100644 index 3054fced8509..000000000000 --- a/include/linux/platform_data/keypad-ep93xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __KEYPAD_EP93XX_H -#define __KEYPAD_EP93XX_H - -struct matrix_keymap_data; - -/* flags for the ep93xx_keypad driver */ -#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ -#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ -#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */ -#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */ -#define EP93XX_KEYPAD_AUTOREPEAT (1<<4) /* enable key autorepeat */ - -/** - * struct ep93xx_keypad_platform_data - platform specific device structure - * @keymap_data: pointer to &matrix_keymap_data - * @debounce: debounce start count; terminal count is 0xff - * @prescale: row/column counter pre-scaler load value - * @flags: see above - */ -struct ep93xx_keypad_platform_data { - struct matrix_keymap_data *keymap_data; - unsigned int debounce; - unsigned int prescale; - unsigned int flags; - unsigned int clk_rate; -}; - -#define EP93XX_MATRIX_ROWS (8) -#define EP93XX_MATRIX_COLS (8) - -#endif /* __KEYPAD_EP93XX_H */ diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 142c33a2d7db..3e6cf2b25a97 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -2,7 +2,6 @@ #ifndef _SOC_EP93XX_H #define _SOC_EP93XX_H =20 -struct platform_device; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-37-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Nikita Shubin , Alexander Sverdlin , Linus Walleij , Charles Keepax , Kuninori Morimoto Cc: Takashi Iwai , linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=4982; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=ZGsaIwYTR1JNVHlGFBAmmmELz25300Pi752QNOzmkk0=; b=9O+F+17wxRLJz2yWUJ08D8BQgW2oaPsPcOcr2seEKHtGgzECvpK/2w4CQHfmtWdkimrzrvmVNhYe dh/psCZWCM6xZspB68g9mW8H2vIh2NuyCghRDLQinO8a+qo4olf5 X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Alexander Sverdlin Can be replaced with "simple-audio-card" for the rates up to 50kHz, refer to commit "ARM: dts: ep93xx: Add EDB9302 DT". Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Acked-by: Mark Brown --- sound/soc/cirrus/Kconfig | 9 ---- sound/soc/cirrus/Makefile | 4 -- sound/soc/cirrus/edb93xx.c | 116 -----------------------------------------= ---- 3 files changed, 129 deletions(-) diff --git a/sound/soc/cirrus/Kconfig b/sound/soc/cirrus/Kconfig index 38a83c4dcc2d..97def4e53fbc 100644 --- a/sound/soc/cirrus/Kconfig +++ b/sound/soc/cirrus/Kconfig @@ -31,12 +31,3 @@ config SND_EP93XX_SOC_I2S_WATCHDOG =20 endif # if SND_EP93XX_SOC_I2S =20 -config SND_EP93XX_SOC_EDB93XX - tristate "SoC Audio support for Cirrus Logic EDB93xx boards" - depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB930= 2A || MACH_EDB9307A || MACH_EDB9315A) - select SND_EP93XX_SOC_I2S - select SND_SOC_CS4271_I2C if I2C - select SND_SOC_CS4271_SPI if SPI_MASTER - help - Say Y or M here if you want to add support for I2S audio on the - Cirrus Logic EDB93xx boards. diff --git a/sound/soc/cirrus/Makefile b/sound/soc/cirrus/Makefile index ad606b293715..61d8cf64e859 100644 --- a/sound/soc/cirrus/Makefile +++ b/sound/soc/cirrus/Makefile @@ -6,7 +6,3 @@ snd-soc-ep93xx-i2s-y :=3D ep93xx-i2s.o obj-$(CONFIG_SND_EP93XX_SOC) +=3D snd-soc-ep93xx.o obj-$(CONFIG_SND_EP93XX_SOC_I2S) +=3D snd-soc-ep93xx-i2s.o =20 -# EP93XX Machine Support -snd-soc-edb93xx-y :=3D edb93xx.o - -obj-$(CONFIG_SND_EP93XX_SOC_EDB93XX) +=3D snd-soc-edb93xx.o diff --git a/sound/soc/cirrus/edb93xx.c b/sound/soc/cirrus/edb93xx.c deleted file mode 100644 index 8bb67d7d2b4b..000000000000 --- a/sound/soc/cirrus/edb93xx.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * SoC audio for EDB93xx - * - * Copyright (c) 2010 Alexander Sverdlin - * - * This driver support CS4271 codec being master or slave, working - * in control port mode, connected either via SPI or I2C. - * The data format accepted is I2S or left-justified. - * DAPM support not implemented. - */ - -#include -#include -#include -#include -#include -#include -#include - -static int edb93xx_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd =3D snd_soc_substream_to_rtd(substream); - struct snd_soc_dai *codec_dai =3D snd_soc_rtd_to_codec(rtd, 0); - struct snd_soc_dai *cpu_dai =3D snd_soc_rtd_to_cpu(rtd, 0); - int err; - unsigned int mclk_rate; - unsigned int rate =3D params_rate(params); - - /* - * According to CS4271 datasheet we use MCLK/LRCK=3D256 for - * rates below 50kHz and 128 for higher sample rates - */ - if (rate < 50000) - mclk_rate =3D rate * 64 * 4; - else - mclk_rate =3D rate * 64 * 2; - - err =3D snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, - SND_SOC_CLOCK_IN); - if (err) - return err; - - return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, - SND_SOC_CLOCK_OUT); -} - -static const struct snd_soc_ops edb93xx_ops =3D { - .hw_params =3D edb93xx_hw_params, -}; - -SND_SOC_DAILINK_DEFS(hifi, - DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-i2s")), - DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "cs4271-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-i2s"))); - -static struct snd_soc_dai_link edb93xx_dai =3D { - .name =3D "CS4271", - .stream_name =3D "CS4271 HiFi", - .dai_fmt =3D SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBC_CFC, - .ops =3D &edb93xx_ops, - SND_SOC_DAILINK_REG(hifi), -}; - -static struct snd_soc_card snd_soc_edb93xx =3D { - .name =3D "EDB93XX", - .owner =3D THIS_MODULE, - .dai_link =3D &edb93xx_dai, - .num_links =3D 1, -}; - -static int edb93xx_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D &snd_soc_edb93xx; - int ret; - - ret =3D ep93xx_i2s_acquire(); - if (ret) - return ret; - - card->dev =3D &pdev->dev; - - ret =3D snd_soc_register_card(card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - ep93xx_i2s_release(); - } - - return ret; -} - -static void edb93xx_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D platform_get_drvdata(pdev); - - snd_soc_unregister_card(card); - ep93xx_i2s_release(); -} - -static struct platform_driver edb93xx_driver =3D { - .driver =3D { - .name =3D "edb93xx-audio", - }, - .probe =3D edb93xx_probe, - .remove_new =3D edb93xx_remove, -}; - -module_platform_driver(edb93xx_driver); - -MODULE_AUTHOR("Alexander Sverdlin "); -MODULE_DESCRIPTION("ALSA SoC EDB93xx"); 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Mon, 15 Jul 2024 08:40:05 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Mon, 15 Jul 2024 11:38:42 +0300 Subject: [PATCH v11 38/38] dmaengine: cirrus: remove platform code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240715-ep93xx-v11-38-4e924efda795@maquefel.me> References: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> In-Reply-To: <20240715-ep93xx-v11-0-4e924efda795@maquefel.me> To: Vinod Koul , Nikita Shubin , Alexander Sverdlin Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1721032800; l=6076; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=qbQ0k1cwlr7iv0JKjGQW+rzyy6spZcOEIpiufkU6/UM=; b=WMPqh1SifiYBS+sJ0DL54/q99WbOs4Le3kfFcKidpOt9cYcsyAdMSSBp3iiVGliA8eIQACJHzVhy zEvvtsjzDmu9h8asVynI1LQl2jcf5itdK8xgiPs4J09Sh7dYiylm X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: nikita.shubin@maquefel.me From: Nikita Shubin Remove DMA platform header, from now on we use device tree for DMA clients. Acked-by: Vinod Koul Signed-off-by: Nikita Shubin --- drivers/dma/ep93xx_dma.c | 48 ++++++++++++++- include/linux/platform_data/dma-ep93xx.h | 100 ---------------------------= ---- 2 files changed, 46 insertions(+), 102 deletions(-) diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index 17c8e2badee2..43c4241af7f5 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -25,8 +26,6 @@ #include #include =20 -#include - #include "dmaengine.h" =20 /* M2P registers */ @@ -106,6 +105,26 @@ #define DMA_MAX_CHAN_BYTES 0xffff #define DMA_MAX_CHAN_DESCRIPTORS 32 =20 +/* + * M2P channels. + * + * Note that these values are also directly used for setting the PPALLOC + * register. + */ +#define EP93XX_DMA_I2S1 0 +#define EP93XX_DMA_I2S2 1 +#define EP93XX_DMA_AAC1 2 +#define EP93XX_DMA_AAC2 3 +#define EP93XX_DMA_AAC3 4 +#define EP93XX_DMA_I2S3 5 +#define EP93XX_DMA_UART1 6 +#define EP93XX_DMA_UART2 7 +#define EP93XX_DMA_UART3 8 +#define EP93XX_DMA_IRDA 9 +/* M2M channels */ +#define EP93XX_DMA_SSP 10 +#define EP93XX_DMA_IDE 11 + enum ep93xx_dma_type { M2P_DMA, M2M_DMA, @@ -242,6 +261,31 @@ static struct ep93xx_dma_chan *to_ep93xx_dma_chan(stru= ct dma_chan *chan) return container_of(chan, struct ep93xx_dma_chan, chan); } =20 +static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) +{ + if (device_is_compatible(chan->device->dev, "cirrus,ep9301-dma-m2p")) + return true; + + return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); +} + +/* + * ep93xx_dma_chan_direction - returns direction the channel can be used + * + * This function can be used in filter functions to find out whether the + * channel supports given DMA direction. Only M2P channels have such + * limitation, for M2M channels the direction is configurable. + */ +static inline enum dma_transfer_direction +ep93xx_dma_chan_direction(struct dma_chan *chan) +{ + if (!ep93xx_dma_chan_is_m2p(chan)) + return DMA_TRANS_NONE; + + /* even channels are for TX, odd for RX */ + return (chan->chan_id % 2 =3D=3D 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; +} + /** * ep93xx_dma_set_active - set new active descriptor chain * @edmac: channel diff --git a/include/linux/platform_data/dma-ep93xx.h b/include/linux/platf= orm_data/dma-ep93xx.h deleted file mode 100644 index 9ec5cdd5a1eb..000000000000 --- a/include/linux/platform_data/dma-ep93xx.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -#include -#include -#include -#include -#include -#include - -/* - * M2P channels. - * - * Note that these values are also directly used for setting the PPALLOC - * register. - */ -#define EP93XX_DMA_I2S1 0 -#define EP93XX_DMA_I2S2 1 -#define EP93XX_DMA_AAC1 2 -#define EP93XX_DMA_AAC2 3 -#define EP93XX_DMA_AAC3 4 -#define EP93XX_DMA_I2S3 5 -#define EP93XX_DMA_UART1 6 -#define EP93XX_DMA_UART2 7 -#define EP93XX_DMA_UART3 8 -#define EP93XX_DMA_IRDA 9 -/* M2M channels */ -#define EP93XX_DMA_SSP 10 -#define EP93XX_DMA_IDE 11 - -/** - * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine - * @port: peripheral which is requesting the channel - * @direction: TX/RX channel - * @name: optional name for the channel, this is displayed in /proc/interr= upts - * - * This information is passed as private channel parameter in a filter - * function. Note that this is only needed for slave/cyclic channels. For - * memcpy channels %NULL data should be passed. - */ -struct ep93xx_dma_data { - int port; - enum dma_transfer_direction direction; - const char *name; -}; - -/** - * struct ep93xx_dma_chan_data - platform specific data for a DMA channel - * @name: name of the channel, used for getting the right clock for the ch= annel - * @base: mapped registers - * @irq: interrupt number used by this channel - */ -struct ep93xx_dma_chan_data { - const char *name; - void __iomem *base; - int irq; -}; - -/** - * struct ep93xx_dma_platform_data - platform data for the dmaengine driver - * @channels: array of channels which are passed to the driver - * @num_channels: number of channels in the array - * - * This structure is passed to the DMA engine driver via platform data. For - * M2P channels, contract is that even channels are for TX and odd for RX. - * There is no requirement for the M2M channels. - */ -struct ep93xx_dma_platform_data { - struct ep93xx_dma_chan_data *channels; - size_t num_channels; -}; - -static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) -{ - if (device_is_compatible(chan->device->dev, "cirrus,ep9301-dma-m2p")) - return true; - - return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); -} - -/** - * ep93xx_dma_chan_direction - returns direction the channel can be used - * @chan: channel - * - * This function can be used in filter functions to find out whether the - * channel supports given DMA direction. Only M2P channels have such - * limitation, for M2M channels the direction is configurable. - */ -static inline enum dma_transfer_direction -ep93xx_dma_chan_direction(struct dma_chan *chan) -{ - if (!ep93xx_dma_chan_is_m2p(chan)) - return DMA_TRANS_NONE; - - /* even channels are for TX, odd for RX */ - return (chan->chan_id % 2 =3D=3D 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; -} - -#endif /* __ASM_ARCH_DMA_H */ --=20 2.43.2