From nobody Wed Dec 17 13:56:02 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FCAA1891DC; Mon, 15 Jul 2024 11:14:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721042092; cv=none; b=DVK1qpM/6NLRb27xt2o0uBc+Uq1wmhPooO4h01ypq7oC0rB67QH+hsQ+ysZcZxInKXTgHOWDX/5Ow3HXGCSEoH+4O+90TQO6VVHKGAS8WDwY0b1dkz0iklkJuZKnbLNqGOHSflEz6DfYl5k2/+/Q6K7GdxeEMHBQ2SBV/dDOrgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721042092; c=relaxed/simple; bh=BEQ52OycMXhuGlXXvUjM+j81jFqhZR2hcVcYZWfDbOw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S7LP9bViJM5z+btP+u372mZwIl0G7VcvIWwM/5MusMYoXijO0mKYssv1fFtP9wU6nBn+ppBspMjGNNtS5slTEZBWdVV0e1BWyueDViJFmn6lmI+HpH/vms7XMBql5apY5+9aHWWdmlQcY3Iv9GNjv6oaq8j18KHJvCKI3Ob2zpI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Se13DQqE; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Se13DQqE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1721042090; x=1752578090; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BEQ52OycMXhuGlXXvUjM+j81jFqhZR2hcVcYZWfDbOw=; b=Se13DQqEFfr8qhEJopu3cfWNk/v5EL1H+Z4pQ+ywI5YaXGpw5yPue9Xw 7WtsZ4ed3NvRkmSICChA8rTulPK/8q3wKkeLKVDKru71x63uwR8M1zuh0 DBqjwo1cLvlNd6kAIcwDJvZ7L7bEqIyKzf26ujuNGDLyRgGM00D734g1f 7+PiZX7qglJz9uFfRLpzAVQG8WDgmg3faD1mBN832SNSAIo1cEea/QgSI Xd3/rCiTNlFT6MdSiR6dMDsBdy4i2m7el9fC2LbYl8Z2EPf44QgqxyKgj tNGHO2V9K+eZe+kfwCsgSMqKOrboLtJfv+nouTumSVf4R9JqaxoQR8QuH w==; X-CSE-ConnectionGUID: M47IHorFQcORQBAq4muecw== X-CSE-MsgGUID: BEBq5ILYTtKHb08hHg+Ncw== X-IronPort-AV: E=Sophos;i="6.09,210,1716274800"; d="scan'208";a="196643523" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 15 Jul 2024 04:14:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 15 Jul 2024 04:14:45 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 15 Jul 2024 04:14:43 -0700 From: Conor Dooley To: CC: , , Steve Wilkins , Daire McNamara , Mark Brown , Subject: [PATCH v1 6/6] spi: microchip-core: add support for word sizes of 1 to 32 bits Date: Mon, 15 Jul 2024 12:13:57 +0100 Message-ID: <20240715-cogwheel-uniquely-0d4ef518b809@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240715-retail-magnolia-bbd49a657a89@wendy> References: <20240715-retail-magnolia-bbd49a657a89@wendy> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4283; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=SLr+fKyui42+8hroU8IV8E1Sye2BojjF+ZVhjk0+kHU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlTWYqDbgutmLqi6aSjewlv1DSumFrbAyrXf+u1nNJ0kFOb yu/bUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIl84mRkWFOy1d3wvV/T+XWBLaZ7Y4 tLrh78wfK3TDVd/JBUi4IHEyPDvqaY/dcvNv4Pv7ny22/lsF7mqQn3nqxacnLFe6tP3l18XAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Steve Wilkins The current implementation only supports a word size of 8 bits, which limits the devices it can be used with. Add support for any word size between 1 and 32 bits, as supported by the hardware. Signed-off-by: Steve Wilkins Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core.c | 53 +++++++++++++++++++------------- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-c= ore.c index 9f37603ccf10a..856bcbf0292d4 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -111,7 +111,7 @@ struct mchp_corespi { int irq; int tx_len; int rx_len; - int pending; + int n_bytes; }; =20 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int= reg) @@ -135,20 +135,23 @@ static inline void mchp_corespi_disable(struct mchp_c= orespi *spi) =20 static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi) { - u8 data; - int fifo_max, i =3D 0; + while (spi->rx_len >=3D spi->n_bytes && !(mchp_corespi_read(spi, REG_STAT= US) & STATUS_RXFIFO_EMPTY)) { + u32 data =3D mchp_corespi_read(spi, REG_RX_DATA); =20 - fifo_max =3D min(spi->rx_len, FIFO_DEPTH); + spi->rx_len -=3D spi->n_bytes; =20 - while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RX= FIFO_EMPTY)) { - data =3D mchp_corespi_read(spi, REG_RX_DATA); + if (!spi->rx_buf) + continue; =20 - if (spi->rx_buf) - *spi->rx_buf++ =3D data; - i++; + if (spi->n_bytes =3D=3D 4) + *((u32 *)spi->rx_buf) =3D data; + else if (spi->n_bytes =3D=3D 2) + *((u16 *)spi->rx_buf) =3D data; + else + *spi->rx_buf =3D data; + + spi->rx_buf +=3D spi->n_bytes; } - spi->rx_len -=3D i; - spi->pending -=3D i; } =20 static void mchp_corespi_enable_ints(struct mchp_corespi *spi) @@ -210,20 +213,28 @@ static inline void mchp_corespi_set_xfer_size(struct = mchp_corespi *spi, int len) =20 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi) { - u8 byte; int fifo_max, i =3D 0; =20 - fifo_max =3D min(spi->tx_len, FIFO_DEPTH); + fifo_max =3D DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes); mchp_corespi_set_xfer_size(spi, fifo_max); =20 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TX= FIFO_FULL)) { - byte =3D spi->tx_buf ? *spi->tx_buf++ : 0xaa; - mchp_corespi_write(spi, REG_TX_DATA, byte); + u32 word; + + if (spi->n_bytes =3D=3D 4) + word =3D spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa; + else if (spi->n_bytes =3D=3D 2) + word =3D spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa; + else + word =3D spi->tx_buf ? *spi->tx_buf : 0xaa; + + mchp_corespi_write(spi, REG_TX_DATA, word); + if (spi->tx_buf) + spi->tx_buf +=3D spi->n_bytes; i++; } =20 - spi->tx_len -=3D i; - spi->pending +=3D i; + spi->tx_len -=3D i * spi->n_bytes; } =20 static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, in= t bt) @@ -490,10 +501,9 @@ static int mchp_corespi_transfer_one(struct spi_contro= ller *host, spi->rx_buf =3D xfer->rx_buf; spi->tx_len =3D xfer->len; spi->rx_len =3D xfer->len; - spi->pending =3D 0; + spi->n_bytes =3D roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BIT= S_PER_BYTE)); =20 - mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH) - ? FIFO_DEPTH : spi->tx_len); + mchp_corespi_set_framesize(spi, xfer->bits_per_word); =20 mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORS= T); =20 @@ -511,7 +521,6 @@ static int mchp_corespi_prepare_message(struct spi_cont= roller *host, struct spi_device *spi_dev =3D msg->spi; struct mchp_corespi *spi =3D spi_controller_get_devdata(host); =20 - mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE); mchp_corespi_set_mode(spi, spi_dev->mode); =20 return 0; @@ -538,7 +547,7 @@ static int mchp_corespi_probe(struct platform_device *p= dev) host->num_chipselect =3D num_cs; host->mode_bits =3D SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; host->setup =3D mchp_corespi_setup; - host->bits_per_word_mask =3D SPI_BPW_MASK(8); + host->bits_per_word_mask =3D SPI_BPW_RANGE_MASK(1, 32); host->transfer_one =3D mchp_corespi_transfer_one; host->prepare_message =3D mchp_corespi_prepare_message; host->set_cs =3D mchp_corespi_set_cs; --=20 2.43.2