From nobody Thu Feb 12 02:44:52 2026 Received: from mail-il1-f172.google.com (mail-il1-f172.google.com [209.85.166.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E44C146A6D for ; Sat, 13 Jul 2024 22:35:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910124; cv=none; b=ToOlApTNyNPFe7opgnUY1sxfUANdoPt9N/p3EZop6bC0BxaZB98JrPdB4YrWH3DpsRRIV4ibpgNuf7GRWMgh0JaDvgrnePAkzhWcT/1oIuyMSlWebx72KGfKV3DWJII827KZY7KgowvMexU64+fPos0UrC1zDlhdPxlExmg8OrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910124; c=relaxed/simple; bh=v53LsPjL4NbtXyTKg2jMCfMm9WLoShyCu0Vc0CFSrgY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ueO+gZ0wk3sCTeMA14tTd+faocr+2jTd4ypTNLz9IRCBMPbQy+v31LFqnKR+rVOyEVKcU72TV2p34QgQQuIRFG+cIFXGJ+6POosALwwwmoWFajuHF1iAVAzfkBY1OMpkvXAMaMOjjUJ106D1dRDQHfZtMwBC/C4v6iBgU0bM2zA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com; spf=none smtp.mailfrom=pdp7.com; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b=T4i+RL37; arc=none smtp.client-ip=209.85.166.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=pdp7.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b="T4i+RL37" Received: by mail-il1-f172.google.com with SMTP id e9e14a558f8ab-380eb36f5ceso13207685ab.0 for ; Sat, 13 Jul 2024 15:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pdp7-com.20230601.gappssmtp.com; s=20230601; t=1720910122; x=1721514922; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Z9djOW17Hq6Bkvn3DcF8Wpe8/RB5nd3f1kRECjv6cq8=; b=T4i+RL37YaqiPkPsV9qj5B6/CLcVoHp5YrkGWcemAN+l3jef0HpELAior7an8rsxPT TpQ7k28eZmtY2SmoSFfs4S0x2X2lr0tmVB24wwG2BO0Jqfuogzu6gou+Xufc+fSRT6FY am2Wx95thhGHJ3jbCFRr1PD3zPS7vN9PYvt/GRfvX81vozke5ke7mj4OvYQutN9vIayc JUkxLRsEELFnWNqLTHYla/Kou99lZQ+ACM0++cILxQ4dwM3jlJ8t2HauFoUJdcnho+QM k/wd0p5JREoXlBwDHagjoszzHL67NFKLltopTbynZdW/FyXoKrxchbXb8c5l7jNy0tg9 Qu9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720910122; x=1721514922; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z9djOW17Hq6Bkvn3DcF8Wpe8/RB5nd3f1kRECjv6cq8=; b=ZFjx+nFGQf3uy92Mam5P6P3clTZZeHCjbXAxXs7b2fGtoMKFSFl0On57tXNsO9VrMl UyOSY09pyeV13INwkI67tPf/W8Pragjz2Riv9H7RpLAaLAaVZV4HworWeJRI7c4f0J9L k8IlrB4FvjA6jFeLUtiOx6q54VanbDBHIZSiviVM937/IsyYyQTkD2lqDjOvwiiYjxvI WfnI9jyoNoAnC637zNMx17NiFYmIh03N6Y28pRzVcnzacKkqzwfNK76rH47D5Bzm0C8g kkC6a7xh+vvJMRgDId08lPIl/JtBPtLp+KEfTuy2LM0NxbdduxKoac0TOiy7LejLvSDv NbiQ== X-Forwarded-Encrypted: i=1; AJvYcCXURDgMZfi3HJ3TKGLEwcfrERh4JP0kMk8cpztDnywfabpMUBx/TtYuD6nBr7G9HVv8S/DAHcyoA/JmDJEkw3tdvOE0SGtCnnbThFQf X-Gm-Message-State: AOJu0YyUiVoduEzJ7fhYTHoXx80r6ou4Kefr895yUbsH3s0osp7IkuIs Avtz4eTsd8Xvs2+Yc058xPfVgQkCIRcNdUwxgMTBTTc9pOwWD1Ry6qY9qrAJeNM= X-Google-Smtp-Source: AGHT+IGNoMVxgXKi4Huov/Am3Ivchl0iprmp4ADpiiyaxEKkK4U/SDRcp1yh3lV7jZtqlVQMYQIEhg== X-Received: by 2002:a05:6e02:1aaa:b0:37a:a9f0:f263 with SMTP id e9e14a558f8ab-38a5910a9dbmr198272225ab.20.1720910122467; Sat, 13 Jul 2024 15:35:22 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:d7fc:57d0:ada6:13b7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc4d9d8sm14640025ad.264.2024.07.13.15.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jul 2024 15:35:22 -0700 (PDT) From: Drew Fustini Date: Sat, 13 Jul 2024 15:35:10 -0700 Subject: [PATCH RFC net-next 1/4] dt-bindings: net: snps,dwmac: allow dwmac-3.70a to set pbl properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240713-thead-dwmac-v1-1-81f04480cd31@tenstorrent.com> References: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> In-Reply-To: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720910119; l=1130; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=L968+RrYNmrkLCbknalApiDQwXty2dLJdHRIixXyCag=; b=L3rqLpVjtvL21xgmZs17aB0F6yoEoEFcG/yalWgNg23k2p7NGXFOeub8Bz4u6U8EICTfuR3s6 7Lx5UJrPN2QAxVkpjpSt/mOQiqvngcDggj0buGRWYjAWtMSM++8boGB X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= From: Jisheng Zhang snps dwmac 3.70a also supports setting pbl related properties, such as "snps,pbl", "snps,txpbl", "snps,rxpbl" and "snps,no-pbl-x8". Signed-off-by: Jisheng Zhang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230827091710.1483-2-jszhang@kernel.org Signed-off-by: Emil Renner Berthing Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 21cc27e75f50..0ad3bf5dafa7 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -584,6 +584,7 @@ allOf: - qcom,sa8775p-ethqos - qcom,sc8280xp-ethqos - snps,dwmac-3.50a + - snps,dwmac-3.70a - snps,dwmac-4.10a - snps,dwmac-4.20a - snps,dwmac-5.20 --=20 2.34.1 From nobody Thu Feb 12 02:44:52 2026 Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB15E14E2C0 for ; Sat, 13 Jul 2024 22:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910126; cv=none; b=Qflso1A6YRYZpnghqrINbkVB5rCkAJjW5xZmaDcHS0ZUXgGM86Jrkf0vRZqhjwemk5WkUPq5wkOomCOnA9soDwTny5Rq/1VXIw4og0JFOyVNpvVKic85ltYcxOWac5/i8LoLHi3KHY7cSvU7kNRPDbp5dMIXVNYenxA1HtHsUxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910126; c=relaxed/simple; bh=zCLySV5EiWp6xCmHvjwHnXYPPFGzjEkiFSbsL+beAvY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gtBAhYiwBUU6FKSYLRFhhKqz+o5QcWCk6yQqsGF+zWyxcvOePYGBFMzCXMGh0PBkKM19qxp/OIPa/y4lxXzXK7e7Lbbgvjk70Sv1BUn074V9goDFI/9c2cWDZRi7jcQKymR+z+NGaTO35f7KmnwkW6ZoSGPtpaMm9ria14NiE4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com; spf=none smtp.mailfrom=pdp7.com; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b=VQWcCCCG; arc=none smtp.client-ip=209.85.167.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=pdp7.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b="VQWcCCCG" Received: by mail-oi1-f180.google.com with SMTP id 5614622812f47-3d9c487b2b5so1899199b6e.3 for ; Sat, 13 Jul 2024 15:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pdp7-com.20230601.gappssmtp.com; s=20230601; t=1720910124; x=1721514924; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=alTBG+u/YLjKyTy47XAD1gqzMa09sOqVoRaB/kIbg6M=; b=VQWcCCCGe85V0eos3nAAwlsMOcZe7ohy5/MpR8gktKpRrRTX6hVgQtB/mQ4HXZu9+S kr6danvovbxyHEfNhd+A1ovmD3scVFPB6IECR3nPLmEwGOs/ZYJLuwN7Zyuqe94Ata8a C2iuFJ5F+7mHkpEOXZF+BvRDOgVihX8FzoJlsJgPrwtwQmsUXfk5RKhsZCTbUV8ikhF5 UN5t7ElLR1y2AUSrXIgfcQpdoH4t/DlaX5a6JbdRoCOShN5w5onfDG9QcCr2lm/wiqyL Lx9L/98h9lTPyC/3pZR3hGInZ484Axj9haHo/fG58aTku5ZRZdJ4BxdSGCbfovMFkQmc Zgqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720910124; x=1721514924; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=alTBG+u/YLjKyTy47XAD1gqzMa09sOqVoRaB/kIbg6M=; b=qrjYdEYy1TKI5aaJC/0YTVSWk/EOAN87LnhU6pcLvBl4af5z3Rzdovhl3YG08k9qxc 1haIWcv/SzlOC0RjxlUt11CZ/Jbo2TNCyXW0uRsu3vXdsaNuY//j5Nej3T1YriogjMKj r1fpgfhru43HNyhVdGzQtZqXbALBQ8zsZ9k6n+VYeq+fmsbBpxdYjZw5BAF2DVGpU0e4 zJKukT+fCNzn2bxuzp/ujydVqfJIcF6oc2b+YIJm9yc2QJbpGaLiys4Em/vb8TgtCFyY O9LKAi+oUodQBkSj2oLtDxvIohUernWeaLtg/6U+fy85YvexsfgSuyREwH5umReFj/TR I4Sg== X-Forwarded-Encrypted: i=1; AJvYcCXKavD7FOkzpQKDXXZNMMQdvxiypkWENO+RcBfmn+TJeFUofvvCYCvLit3RJh4NeIJEMKPgiYkTo1aBkh+hSj3zDxxO9k/OzGJsPqbI X-Gm-Message-State: AOJu0YzKiqflFWl4ha3Frbhof8ONxlUCUiunL8A5nMcwv2t8wF5lElnS 9g31gTJR8w/sYxYu5Brd8j4z81SwDdbNUehlaX5PT9g1x2FFTZZLytj2AWSo2+c= X-Google-Smtp-Source: AGHT+IEYT0gC2VTZYS2sf8gfKkEAnenEHDXxurHyzMbwt0lUKt7Uw0JJq9+GvaJQa3SRamrYdVWDxQ== X-Received: by 2002:a54:4887:0:b0:3da:a6ce:f02c with SMTP id 5614622812f47-3daa6cef4c8mr8226788b6e.20.1720910123980; Sat, 13 Jul 2024 15:35:23 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:d7fc:57d0:ada6:13b7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc4d9d8sm14640025ad.264.2024.07.13.15.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jul 2024 15:35:23 -0700 (PDT) From: Drew Fustini Date: Sat, 13 Jul 2024 15:35:11 -0700 Subject: [PATCH RFC net-next 2/4] dt-bindings: net: add T-HEAD dwmac support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240713-thead-dwmac-v1-2-81f04480cd31@tenstorrent.com> References: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> In-Reply-To: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720910119; l=3679; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=Y0E8nHMS0ChuTKJIO/9LY9pitgmvEOTz6OdEh2EGJdM=; b=CnXpDka3RYSnvNevDmDeEY3cdh4Cuclhx83gpRYciYZPaW7Lncl7HiKfGGZ+vf+vL/6bKiiAg NqzeNosEJGHCjNVVRAFPPUyhZ9vKonMP2wKOgI5NMbo4mgJUTSUKo60 X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= From: Jisheng Zhang Add documentation to describe T-HEAD dwmac. Signed-off-by: Jisheng Zhang Link: https://lore.kernel.org/r/20230827091710.1483-3-jszhang@kernel.org Signed-off-by: Emil Renner Berthing [drew: change apb registers from syscon to second reg of gmac node] Signed-off-by: Drew Fustini --- .../devicetree/bindings/net/snps,dwmac.yaml | 1 + .../devicetree/bindings/net/thead,dwmac.yaml | 81 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 3 files changed, 83 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index 0ad3bf5dafa7..d417f0e2d9c6 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -97,6 +97,7 @@ properties: - snps,dwxgmac-2.10 - starfive,jh7100-dwmac - starfive,jh7110-dwmac + - thead,th1520-dwmac =20 reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/net/thead,dwmac.yaml b/Docum= entation/devicetree/bindings/net/thead,dwmac.yaml new file mode 100644 index 000000000000..5618ede47925 --- /dev/null +++ b/Documentation/devicetree/bindings/net/thead,dwmac.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/thead,dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD DWMAC Ethernet controller + +maintainers: + - Jisheng Zhang + +select: + properties: + compatible: + contains: + enum: + - thead,th1520-dwmac + required: + - compatible + +properties: + compatible: + items: + - enum: + - thead,th1520-dwmac + - const: snps,dwmac-3.70a + + reg: + minItems: 2 + maxItems: 2 + items: + - description: DesignWare GMAC IP core registers + - description: GMAC APB registers + + reg-names: + minItems: 2 + maxItems: 2 + items: + - const: dwmac + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + gmac0: ethernet@e7070000 { + compatible =3D "thead,th1520-dwmac", "snps,dwmac-3.70a"; + reg =3D <0xe7070000 0x2000>, <0xec003000 0x1000>; + reg-names =3D "dwmac", "apb"; + clocks =3D <&clk 1>, <&clk 2>; + clock-names =3D "stmmaceth", "pclk"; + interrupts =3D <66>; + interrupt-names =3D "macirq"; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,pbl =3D <32>; + phy-handle =3D <&phy0>; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e1736969189b..c724c2c4e06c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19319,6 +19319,7 @@ M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml +F: Documentation/devicetree/bindings/net/thead,dwmac.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h --=20 2.34.1 From nobody Thu Feb 12 02:44:52 2026 Received: from mail-oi1-f170.google.com (mail-oi1-f170.google.com [209.85.167.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F50716CD3C for ; Sat, 13 Jul 2024 22:35:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910129; cv=none; b=mto9bqTRyhAgrnCZIe+FJFpaQxtH2DYhZBWujTkEMVR9OH9sca6EHK+v+yv/ZZZWRb+3qGnrzKXCaqM07jMOm8tN9PTN0ZVY60bAWKXnHZt0ZweBAAwU3V+NYxLmlu43hHHLtGs6pAC4buqqo5UCg82pEqaEiFfmxsj48gh6GzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910129; c=relaxed/simple; bh=tdE5R90K36VC2kxTvGtxPVa23iCMoWWcby052N0PlRw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FhWdJTighPd+a5KlYFTOUPGv/9Ah60ONf6pGAiSahgcI6fjssJJoR+9/6kfDmFDe54PRmxn89FZnWyCx+QCKdx2wuNP8pg3xgVEej4lx2CXhvB+QNvHwhQ2TbRT126bmdFG8PIUjntzToslVoDdIXREseRskEgRFtdpJIf+4pTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com; spf=none smtp.mailfrom=pdp7.com; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b=GAsE3pfg; arc=none smtp.client-ip=209.85.167.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=pdp7.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b="GAsE3pfg" Received: by mail-oi1-f170.google.com with SMTP id 5614622812f47-3c9cc681ee4so1697281b6e.0 for ; Sat, 13 Jul 2024 15:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pdp7-com.20230601.gappssmtp.com; s=20230601; t=1720910125; x=1721514925; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KxcXi7NdNekPLYVDwNRh//Z2yxL04R6rwZHieCVOn5A=; b=GAsE3pfgrx4oHrqhNONQ0R5HHSM7yCdConBLw3IbUslbSUZTqGbjcgdaLD2UE/FCC/ obOw/yi/W5iY9ruJsYyemQ9ROIh2KBElRpO1+03IfWQHcE+D7OsaPYSNw175+cYU2T2d bmEik3em5y7d0aApFYKRy4ATAvkBKVA1yIxzY3EuNRjrGL/0DYllmginVzSLmNi7SLuU 64nGZgAJSveGv1k2U3lMrzQBg9TUcyVqTb7oUrnj88/IwFcwDzT5f4TV0EoRrUMN9Q+h 70btlmkkptbTPwdHCc+cHFNgKcG70nV1WhVO0AaIimXGaHk9/SrtyzRFBRbTSQFCXM9Z M++A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720910125; x=1721514925; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxcXi7NdNekPLYVDwNRh//Z2yxL04R6rwZHieCVOn5A=; b=C/KaLqp+hDadqw+KR+idn+dkKasZCexo0yFesYAvf+heg3klaPIsyjcG3Ucg1w9f19 RCDlTX0lf6zDzvKGC7uHpEzyOREqfD3bENXlDsHrrv9SItAt4+mxJ6zMVvShqIpef355 6mRasnCqL7+0zbS4+fqeTkWZgoYLkHXPx2X0M88YSmHPzxm2R4V39RU6Q/m0QdazMYfX 8/l5mNwAvbmEVR/7fVrK3ZYsDooq+fuHot59VWwejv3fyU4sgm8QiMstf7fGljl5pxm7 Ifivsh9eoFGS/4OVgSHfBodq9w2EP48ueHzpAn6Q0nUgMfqa55hDIBRb+E9+tDQJaMBR /dDQ== X-Forwarded-Encrypted: i=1; AJvYcCUQZyqK70WlwS2+9eWZyXWvqxenbTrS02l/91BPUanjPHGUUzFt5vXhH1isu9AGTGevM4qpuQoKxmINkAfmkc+A3CLGvTyeyu8w7iRG X-Gm-Message-State: AOJu0YyJUTgEVLcZGiPu4leDj4uPnH5lgBIkVkuz4x5WYp4ozwuc5Xei HKn/VBQMnC7wXMJWYjIXi6gVVk1drRSV/6/Zj67gZAB05VmVDzNxRYwXGE1AOTM= X-Google-Smtp-Source: AGHT+IGC6e6E4K6/IAZSwMYQqIInqL2PX4aVPcqzv6ekRwJScTIvLtBEafckxBXBT3eQrxK7SURAkA== X-Received: by 2002:a05:6808:189b:b0:3d9:2b15:65d4 with SMTP id 5614622812f47-3d93c01937bmr17474047b6e.21.1720910125460; Sat, 13 Jul 2024 15:35:25 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:d7fc:57d0:ada6:13b7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc4d9d8sm14640025ad.264.2024.07.13.15.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jul 2024 15:35:25 -0700 (PDT) From: Drew Fustini Date: Sat, 13 Jul 2024 15:35:12 -0700 Subject: [PATCH RFC net-next 3/4] net: stmmac: add glue layer for T-HEAD TH1520 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240713-thead-dwmac-v1-3-81f04480cd31@tenstorrent.com> References: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> In-Reply-To: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720910119; l=11652; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=E3AC2G47Ix6UzDcEHy3fI7MDOIXOWOddF4EcXRil+6w=; b=elEsSv8/lccNPQbHia9lGD4uvQZFjLjPAAphiARVOcr+eKdlEEgWdBPpp39/Auusjasbg4+s1 9JtIZk8LXAaBw1etvRt+vQzUzhAp5o0eCfKGACDGRlsrJg9dG6kCW/e X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= From: Jisheng Zhang Add dwmac glue driver to support the dwmac on the T-HEAD TH1520 SoC. Signed-off-by: Jisheng Zhang Link: https://lore.kernel.org/r/20230827091710.1483-4-jszhang@kernel.org [esmil: rename plat->interface -> plat->mac_interface, use devm_stmmac_probe_config_dt()] Signed-off-by: Emil Renner Berthing [drew: change apb registers from syscon to second reg of gmac node] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c | 300 ++++++++++++++++++= ++++ 4 files changed, 313 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c724c2c4e06c..11fc14e406c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19322,6 +19322,7 @@ F: Documentation/devicetree/bindings/clock/thead,th= 1520-clk-ap.yaml F: Documentation/devicetree/bindings/net/thead,dwmac.yaml F: arch/riscv/boot/dts/thead/ F: drivers/clk/thead/clk-th1520-ap.c +F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: drivers/pinctrl/pinctrl-th1520.c =20 diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 05cc07b8f48c..82030adaf16e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -228,6 +228,17 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_THEAD + tristate "T-HEAD dwmac support" + depends on OF && (ARCH_THEAD || COMPILE_TEST) + select MFD_SYSCON + help + Support for ethernet controllers on T-HEAD RISC-V SoCs + + This selects the T-HEAD platform specific glue layer support for + the stmmac device driver. This driver is used for T-HEAD TH1520 + ethernet controller. + config DWMAC_IMX8 tristate "NXP IMX8 DWMAC support" default ARCH_MXC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..d065634c6223 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o obj-$(CONFIG_DWMAC_LOONGSON1) +=3D dwmac-loongson1.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-thead.c new file mode 100644 index 000000000000..809e75dc51d5 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * T-HEAD DWMAC platform driver + * + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define GMAC_CLK_EN 0x00 +#define GMAC_TX_CLK_EN BIT(1) +#define GMAC_TX_CLK_N_EN BIT(2) +#define GMAC_TX_CLK_OUT_EN BIT(3) +#define GMAC_RX_CLK_EN BIT(4) +#define GMAC_RX_CLK_N_EN BIT(5) +#define GMAC_EPHY_REF_CLK_EN BIT(6) +#define GMAC_RXCLK_DELAY_CTRL 0x04 +#define GMAC_RXCLK_BYPASS BIT(15) +#define GMAC_RXCLK_INVERT BIT(14) +#define GMAC_RXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_RXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_TXCLK_DELAY_CTRL 0x08 +#define GMAC_TXCLK_BYPASS BIT(15) +#define GMAC_TXCLK_INVERT BIT(14) +#define GMAC_TXCLK_DELAY_MASK GENMASK(4, 0) +#define GMAC_TXCLK_DELAY_VAL(x) FIELD_PREP(GMAC_RXCLK_DELAY_MASK, (x)) +#define GMAC_PLLCLK_DIV 0x0c +#define GMAC_PLLCLK_DIV_EN BIT(31) +#define GMAC_PLLCLK_DIV_MASK GENMASK(7, 0) +#define GMAC_PLLCLK_DIV_NUM(x) FIELD_PREP(GMAC_PLLCLK_DIV_MASK, (x)) +#define GMAC_GTXCLK_SEL 0x18 +#define GMAC_GTXCLK_SEL_PLL BIT(0) +#define GMAC_INTF_CTRL 0x1c +#define PHY_INTF_MASK BIT(0) +#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1) +#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0) +#define GMAC_TXCLK_OEN 0x20 +#define TXCLK_DIR_MASK BIT(0) +#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0) +#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1) + +#define GMAC_GMII_RGMII_RATE 125000000 +#define GMAC_MII_RATE 25000000 + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +struct thead_dwmac { + struct plat_stmmacenet_data *plat; + struct regmap *apb_regmap; + struct device *dev; + u32 rx_delay; + u32 tx_delay; +}; + +static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 phyif; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + phyif =3D PHY_INTF_MII_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + phyif =3D PHY_INTF_RGMII; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + regmap_write(dwmac->apb_regmap, GMAC_INTF_CTRL, phyif); + + return 0; +} + +static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 txclk_dir; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + txclk_dir =3D TXCLK_DIR_INPUT; + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + txclk_dir =3D TXCLK_DIR_OUTPUT; + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + }; + + regmap_write(dwmac->apb_regmap, GMAC_TXCLK_OEN, txclk_dir); + + return 0; +} + +static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned= int mode) +{ + struct thead_dwmac *dwmac =3D priv; + struct plat_stmmacenet_data *plat =3D dwmac->plat; + unsigned long rate; + u32 div; + + switch (plat->mac_interface) { + /* For MII, rxc/txc is provided by phy */ + case PHY_INTERFACE_MODE_MII: + return; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + rate =3D clk_get_rate(plat->stmmac_clk); + if (!rate || rate % GMAC_GMII_RGMII_RATE !=3D 0 || + rate % GMAC_MII_RATE !=3D 0) { + dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate); + return; + } + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, GMAC_PLLCLK_DIV_E= N, 0); + + switch (speed) { + case SPEED_1000: + div =3D rate / GMAC_GMII_RGMII_RATE; + break; + case SPEED_100: + div =3D rate / GMAC_MII_RATE; + break; + case SPEED_10: + div =3D rate * 10 / GMAC_MII_RATE; + break; + default: + dev_err(dwmac->dev, "invalid speed %u\n", speed); + return; + } + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_MASK, GMAC_PLLCLK_DIV_NUM(div)); + + regmap_update_bits(dwmac->apb_regmap, GMAC_PLLCLK_DIV, + GMAC_PLLCLK_DIV_EN, GMAC_PLLCLK_DIV_EN); + break; + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return; + } +} + +static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + u32 reg; + + switch (plat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + reg =3D GMAC_RX_CLK_EN | GMAC_TX_CLK_EN; + break; + + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* use pll */ + regmap_write(dwmac->apb_regmap, GMAC_GTXCLK_SEL, GMAC_GTXCLK_SEL_PLL); + + reg =3D GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN | + GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN; + break; + + default: + dev_err(dwmac->dev, "unsupported phy interface %d\n", + plat->mac_interface); + return -EINVAL; + } + + regmap_write(dwmac->apb_regmap, GMAC_CLK_EN, reg); + + return 0; +} + +static int thead_dwmac_init(struct platform_device *pdev, + struct plat_stmmacenet_data *plat) +{ + struct thead_dwmac *dwmac =3D plat->bsp_priv; + int ret; + + ret =3D thead_dwmac_set_phy_if(plat); + if (ret) + return ret; + + ret =3D thead_dwmac_set_txclk_dir(plat); + if (ret) + return ret; + + regmap_write(dwmac->apb_regmap, GMAC_RXCLK_DELAY_CTRL, + GMAC_RXCLK_DELAY_VAL(dwmac->rx_delay)); + regmap_write(dwmac->apb_regmap, GMAC_TXCLK_DELAY_CTRL, + GMAC_TXCLK_DELAY_VAL(dwmac->tx_delay)); + + thead_dwmac_fix_speed(dwmac, SPEED_1000, 0); + + return thead_dwmac_enable_clk(plat); +} + +static int thead_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat; + struct stmmac_resources stmmac_res; + struct thead_dwmac *dwmac; + struct device_node *np =3D pdev->dev.of_node; + u32 delay_ps; + int ret; + void __iomem *apb; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to get resources\n"); + + plat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac =3D devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay_ps)) + dwmac->rx_delay =3D delay_ps; + if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay_ps)) + dwmac->tx_delay =3D delay_ps; + + apb =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(apb), + "Failed to remap gmac apb registers\n"); + + dwmac->apb_regmap =3D devm_regmap_init_mmio(&pdev->dev, apb, ®map_conf= ig); + if (IS_ERR(dwmac->apb_regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->apb_regmap), + "Failed to access gmac apb registers\n"); + + dwmac->dev =3D &pdev->dev; + dwmac->plat =3D plat; + plat->bsp_priv =3D dwmac; + plat->fix_mac_speed =3D thead_dwmac_fix_speed; + + ret =3D thead_dwmac_init(pdev, plat); + if (ret) + return ret; + + return stmmac_dvr_probe(&pdev->dev, plat, &stmmac_res); +} + +static const struct of_device_id thead_dwmac_match[] =3D { + { .compatible =3D "thead,th1520-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, thead_dwmac_match); + +static struct platform_driver thead_dwmac_driver =3D { + .probe =3D thead_dwmac_probe, + .remove_new =3D stmmac_pltfr_remove, + .driver =3D { + .name =3D "thead-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D thead_dwmac_match, + }, +}; +module_platform_driver(thead_dwmac_driver); + +MODULE_AUTHOR("T-HEAD"); +MODULE_AUTHOR("Jisheng Zhang "); +MODULE_DESCRIPTION("T-HEAD dwmac platform driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Thu Feb 12 02:44:52 2026 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B851214EC5E for ; Sat, 13 Jul 2024 22:35:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910129; cv=none; b=TnPNcRINrGHnc7Qul3Epvl7ET5eurMaKpMSqhSSdoSujPv+Cl5E1oo+anGPYa3chBDTgKYNyEqP1UUjEuAYxcBzDIptN2wCHKz3rdjV3IHC2SDExqul768aXo18efQm0sPeWKrzfkWmeMHVfXs3FQHrFQBa/w5EulcHh5omCuDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720910129; c=relaxed/simple; bh=Q5Q8qlpa5kCEcYBj1kgWUIre0E1iungJE/D6o8c2PKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c9LhRaHJujcvln5CRHcEWQzpx55UR28vVP/ABBNIB1CRF+C6Iq85t/4YH3XnAZ4+p7NjYTsuOiEFOmSnYk1Yv+VOOhHSbPro8DBi/z/T9iXuluqB8r1D79+RaELGyks5yyZd/3Psg/mv4havYIYDaJsIsiMhPzwWks6dQFeVbCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com; spf=none smtp.mailfrom=pdp7.com; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b=tCFpbXf4; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pdp7.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=pdp7.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pdp7-com.20230601.gappssmtp.com header.i=@pdp7-com.20230601.gappssmtp.com header.b="tCFpbXf4" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1fb05b0be01so22109245ad.2 for ; Sat, 13 Jul 2024 15:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pdp7-com.20230601.gappssmtp.com; s=20230601; t=1720910127; x=1721514927; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fMe9w4Sl4nYm2juZuyLgqok6sq0vOd/dm0cLXM37PB8=; b=tCFpbXf4Mg2ZUEn5qNqW5Gcn9XYK3MZVTAW5DKMnR2dz3ApxxCdJaY7F1HlWbjCmoc mwKJP/Xql4O/VEMXRYLtD4bpUk8NLV+nZHGMZgASmPJqQpHX+2hMAZ+PA3OG0wXnb4Je H+coo1inIfGwA/OnHsbbMaFWiaJ/9diRtlbP7eAtdUGfgqBXfGX315kEyVQVn200RWsK efo9I0KxtLtl1aipJXjnYfMzqvs7H2ZvocelSTuHqSMIYTyiwrqfdZmorS7HRXgCePfF WPMibRpXDJ2km00ahj8NFnRk4ibrVx2sgmgq57CzvnYHc4l1Q+rKusys3bthTRnkst/w jzXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720910127; x=1721514927; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fMe9w4Sl4nYm2juZuyLgqok6sq0vOd/dm0cLXM37PB8=; b=mfaDHQ7eZ7b0/iKslD2AX4hUXWVOGCKDDPleB3hCwX4bSDvT6M/DU4lmlCxI2BuPHt hpch3IMdBxCegpkBlM0Z5uo6VwVoBcpFy673AdwfBqhawcQ6iuQMvgNFGSI48krFIjyC 8l3XrZkfMh96B9j1PPUHwUH8VCbkJ1KasO030psdEhetSfb5wfXeaOOQjNlVKyi+tnHz zNMrQPCxQDBLt3v+OMUa3ookC0pTyxlph6/c9hhterF1vq6bv25KVgi/jzY+4xz2Wo1E Xg7RQU9BxBPvCiK+5JvOCFYxi5PGAhJ+COrMHdttxhadaHw/vmvsJVsoIxZWu6FBQyFT YgHg== X-Forwarded-Encrypted: i=1; AJvYcCVqvc3AKxRmvHu3apLSAY/WHiwlvl+UzAdH6e8otKIalgITJ7R2OPbLFZCQTW9MuvWv2twC5LIyCFsv1VNzFYYbAEDDd/zQbm1wFcI0 X-Gm-Message-State: AOJu0YxqG+Li9JS50m34hrK2s8JLgZdI3LTJYMJhzes1RIgauhLWUBVa R6HYKoU/5a+xDYt7CHmI9eppZVAelPRn/08KSGaZk8RVreYsk/JIdnDcltBR4bE= X-Google-Smtp-Source: AGHT+IGObIZ643TT2wBhyhU7VKoiLnFm1jB2Pr2MWhe0lodyFncsHzDT94Hk/HfjPv+LynUfQ7XAoQ== X-Received: by 2002:a17:902:f541:b0:1fb:1faa:96af with SMTP id d9443c01a7336-1fbb6ee18d5mr128941985ad.43.1720910126825; Sat, 13 Jul 2024 15:35:26 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:d7fc:57d0:ada6:13b7]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fc0bc4d9d8sm14640025ad.264.2024.07.13.15.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jul 2024 15:35:26 -0700 (PDT) From: Drew Fustini Date: Sat, 13 Jul 2024 15:35:13 -0700 Subject: [PATCH RFC net-next 4/4] riscv: dts: thead: Add TH1520 ethernet nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240713-thead-dwmac-v1-4-81f04480cd31@tenstorrent.com> References: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> In-Reply-To: <20240713-thead-dwmac-v1-0-81f04480cd31@tenstorrent.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Jisheng Zhang , Maxime Coquelin , Emil Renner Berthing , Drew Fustini , Guo Ren , Fu Wei , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720910119; l=9168; i=dfustini@tenstorrent.com; s=20230430; h=from:subject:message-id; bh=pgJZ1RvKmdYSrnUvyessF+9Y4MQGDYFqOhd3RpDVmoA=; b=Rg/C5Qgi/ty5j4VgYT6Mazq4CfBfpa3p/eKX8d+sJCxiFC4gifdbfADVvkecRYSbGYXkr6qCK fqVq2+Ay3AtD/sz+7kxXZ+5CH5iC7ILOF7vxN7fEhW+yjrA8jrwN89b X-Developer-Key: i=dfustini@tenstorrent.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= From: Emil Renner Berthing Signed-off-by: Emil Renner Berthing [drew: change apb registers from syscon to second reg of gmac node] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 89 ++++++++++++++ .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 131 +++++++++++++++++= ++++ arch/riscv/boot/dts/thead/th1520.dtsi | 55 ++++++++- 3 files changed, 273 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/risc= v/boot/dts/thead/th1520-beaglev-ahead.dts index e9f573c7e67c..59b84a318e03 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -15,6 +15,7 @@ / { compatible =3D "beagle,beaglev-ahead", "thead,th1520"; =20 aliases { + ethernet0 =3D &gmac0; gpio0 =3D &gpio0; gpio1 =3D &gpio1; gpio2 =3D &gpio2; @@ -111,6 +112,23 @@ &sdio0 { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpio3 21 GPIO_ACTIVE_LOW>; + }; +}; + &padctrl_aosys { led_pins: led-0 { led-pins { @@ -130,6 +148,77 @@ led-pins { }; =20 &padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + + phy-reset-pins { + pins =3D "GMAC0_COL"; /* GPIO3_21 */ + bias-disable; + drive-strength =3D <3>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + phy-interrupt-pins { + pins =3D "GMAC0_CRS"; /* GPIO3_22 */ + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <1>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins =3D "UART0_TXD"; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index b5ab80fcd4c3..8a5012f3f3ee 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -11,6 +11,11 @@ / { model =3D "Sipeed Lichee Module 4A"; compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; =20 + aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + memory@0 { device_type =3D "memory"; reg =3D <0x0 0x00000000 0x2 0x00000000>; @@ -29,6 +34,12 @@ &dmac0 { status =3D "okay"; }; =20 +&aogpio { + gpio-line-names =3D "", "", "", + "GPIO00", + "GPIO04"; +}; + &aonsys_clk { clock-frequency =3D <73728000>; }; @@ -62,6 +73,22 @@ &dmac0 { status =3D "okay"; }; =20 +&gmac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_pins>, <&mdio0_pins>; + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + +&gmac1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_pins>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; +}; + &gpio0 { gpio-line-names =3D "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -94,3 +121,107 @@ &gpio3 { "GPIO09", "GPIO10"; }; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + }; + + phy1: ethernet-phy@2 { + reg =3D <2>; + }; +}; + +&padctrl0_apsys { + gmac0_pins: gmac0-0 { + tx-pins { + pins =3D "GMAC0_TX_CLK", + "GMAC0_TXEN", + "GMAC0_TXD0", + "GMAC0_TXD1", + "GMAC0_TXD2", + "GMAC0_TXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GMAC0_RX_CLK", + "GMAC0_RXDV", + "GMAC0_RXD0", + "GMAC0_RXD1", + "GMAC0_RXD2", + "GMAC0_RXD3"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + gmac1_pins: gmac1-0 { + tx-pins { + pins =3D "GPIO2_18", /* GMAC1_TX_CLK */ + "GPIO2_20", /* GMAC1_TXEN */ + "GPIO2_21", /* GMAC1_TXD0 */ + "GPIO2_22", /* GMAC1_TXD1 */ + "GPIO2_23", /* GMAC1_TXD2 */ + "GPIO2_24"; /* GMAC1_TXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <25>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + rx-pins { + pins =3D "GPIO2_19", /* GMAC1_RX_CLK */ + "GPIO2_25", /* GMAC1_RXDV */ + "GPIO2_30", /* GMAC1_RXD0 */ + "GPIO2_31", /* GMAC1_RXD1 */ + "GPIO3_0", /* GMAC1_RXD2 */ + "GPIO3_1"; /* GMAC1_RXD3 */ + function =3D "gmac1"; + bias-disable; + drive-strength =3D <1>; + input-enable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + mdio0_pins: mdio0-0 { + mdc-pins { + pins =3D "GMAC0_MDC"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + + mdio-pins { + pins =3D "GMAC0_MDIO"; + function =3D "gmac0"; + bias-disable; + drive-strength =3D <13>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; +}; + +&sdio0 { + bus-width =3D <4>; + max-frequency =3D <198000000>; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 34b3e10bab09..21f9f81e5322 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -153,6 +153,12 @@ uart_sclk: uart-sclk-clock { #clock-cells =3D <0>; }; =20 + stmmac_axi_config: stmmac-axi-config { + snps,wr_osr_lmt =3D <15>; + snps,rd_osr_lmt =3D <15>; + snps,blen =3D <0 0 64 32 0 0 0>; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; @@ -201,6 +207,50 @@ uart0: serial@ffe7014000 { status =3D "disabled"; }; =20 + gmac1: ethernet@ffe7060000 { + compatible =3D "thead,th1520-dwmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gmac0: ethernet@ffe7070000 { + compatible =3D "thead,th1520-dwmac", "snps,dwmac-3.70a"; + reg =3D <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; + reg-names =3D "dwmac", "apb"; + interrupts =3D <66 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "macirq"; + clocks =3D <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC_AXI>; + clock-names =3D "stmmaceth", "pclk"; + snps,pbl =3D <32>; + snps,fixed-burst; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <32>; + snps,axi-config =3D <&stmmac_axi_config>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + emmc: mmc@ffe7080000 { compatible =3D "thead,th1520-dwcmshc"; reg =3D <0xff 0xe7080000 0x0 0x10000>; @@ -293,7 +343,7 @@ gpio3: gpio-controller@0 { padctrl1_apsys: pinctrl@ffe7f3c000 { compatible =3D "thead,th1520-group2-pinctrl"; reg =3D <0xff 0xe7f3c000 0x0 0x1000>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; }; =20 gpio@ffec005000 { @@ -339,7 +389,8 @@ gpio1: gpio-controller@0 { padctrl0_apsys: pinctrl@ffec007000 { compatible =3D "thead,th1520-group3-pinctrl"; reg =3D <0xff 0xec007000 0x0 0x1000>; - clocks =3D <&apb_clk>; + clocks =3D <&clk CLK_PERI_APB_PCLK>; + }; =20 uart2: serial@ffec010000 { --=20 2.34.1