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From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
To: linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
kvm-riscv@lists.infradead.org,
kvm@vger.kernel.org
Cc: greentime.hu@sifive.com,
vincent.chen@sifive.com,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
Conor Dooley <conor@kernel.org>,
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Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
devicetree@vger.kernel.org
Subject: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
Date: Fri, 12 Jul 2024 16:38:46 +0800
Message-Id: <20240712083850.4242-3-yongxuan.wang@sifive.com>
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Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
property.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu=
mentation/devicetree/bindings/riscv/extensions.yaml
index 468c646247aa..e91a6f4ede38 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -153,6 +153,34 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
=20
+ - const: svade
+ description: |
+ The standard Svade supervisor-level extension for SW-managed P=
TE A/D
+ bit updates as ratified in the 20240213 version of the privile=
ged
+ ISA specification.
+
+ Both Svade and Svadu extensions control the hardware behavior =
when
+ the PTE A/D bits need to be set. The default behavior for the =
four
+ possible combinations of these extensions in the device tree a=
re:
+ 1) Neither Svade nor Svadu present in DT =3D> It is technically
+ unknown whether the platform uses Svade or Svadu. Supervisor
+ software should be prepared to handle either hardware updat=
ing
+ of the PTE A/D bits or page faults when they need updated.
+ 2) Only Svade present in DT =3D> Supervisor must assume Svade =
to be
+ always enabled.
+ 3) Only Svadu present in DT =3D> Supervisor must assume Svadu =
to be
+ always enabled.
+ 4) Both Svade and Svadu present in DT =3D> Supervisor must ass=
ume
+ Svadu turned-off at boot time. To use Svadu, supervisor must
+ explicitly enable it using the SBI FWFT extension.
+
+ - const: svadu
+ description: |
+ The standard Svadu supervisor-level extension for hardware upd=
ating
+ of PTE A/D bits as ratified at commit c1abccf ("Merge pull req=
uest
+ #25 from ved-rivos/ratified") of riscv-svadu. Please refer to =
Svade
+ dt-binding description for more details.
+
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grain=
ed
--=20
2.17.1