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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:07 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Ortiz , Daniel Henrique Barboza , Samuel Holland , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Leonardo Bras , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Jisheng Zhang Subject: [PATCH v7 1/4] RISC-V: Add Svade and Svadu Extensions Support Date: Fri, 12 Jul 2024 16:38:45 +0800 Message-Id: <20240712083850.4242-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- arch/riscv/kernel/cpufeature.c | 32 ++++++++++++++++++++++++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0525ee2d63c7..3d705e28ff85 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -36,6 +36,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..35d7aa49785d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADE 75 +#define RISCV_ISA_EXT_SVADU 76 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index aad8b8ca51f1..ec0cdacd7da0 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include =20 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_S= HIFT) =20 @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } =20 #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include =20 static __always_inline bool has_svnapot(void) { @@ -624,6 +624,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _p= rot) return __pgprot(prot); } =20 +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bit= s need to be set. By + * default the M-mode firmware enables the hardware updating scheme when o= nly Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5ef48cb20ee1..b2c3fe945e89 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), @@ -554,6 +556,21 @@ static void __init riscv_fill_hwcap_from_isa_string(un= signed long *isa2hwcap) clear_bit(RISCV_ISA_EXT_v, isainfo->isa); } =20 + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extens= ion. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't @@ -619,6 +636,21 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) =20 of_node_put(cpu_node); =20 + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extens= ion. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" harts should have same isa. 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:12 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Date: Fri, 12 Jul 2024 16:38:46 +0800 Message-Id: <20240712083850.4242-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang Acked-by: Conor Dooley Reviewed-by: Alexandre Ghiti Reviewed-by: Samuel Holland --- .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..e91a6f4ede38 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,34 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. =20 + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed P= TE A/D + bit updates as ratified in the 20240213 version of the privile= ged + ISA specification. + + Both Svade and Svadu extensions control the hardware behavior = when + the PTE A/D bits need to be set. The default behavior for the = four + possible combinations of these extensions in the device tree a= re: + 1) Neither Svade nor Svadu present in DT =3D> It is technically + unknown whether the platform uses Svade or Svadu. Supervisor + software should be prepared to handle either hardware updat= ing + of the PTE A/D bits or page faults when they need updated. + 2) Only Svade present in DT =3D> Supervisor must assume Svade = to be + always enabled. + 3) Only Svadu present in DT =3D> Supervisor must assume Svadu = to be + always enabled. + 4) Both Svade and Svadu present in DT =3D> Supervisor must ass= ume + Svadu turned-off at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware upd= ating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull req= uest + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to = Svade + dt-binding description for more details. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grain= ed --=20 2.17.1 From nobody Fri Apr 11 18:34:53 2025 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B21C9142900 for ; Fri, 12 Jul 2024 08:39:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773559; cv=none; b=psh9Oi0yHXdbcdlWm2xKXUhl6TG5YTENwRrdJq+2XFnRsFEqL466IhFAP9ABzu9BRYe6oe5rGh54CkFiBYj0iqynDoYJwRF21cm1BfFMYVbKwbplkNNUwRKxNrzDFx580KscxsHJwMLQrH6Hws2gRrAUGtRC9UslQj+ryIf0arM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773559; c=relaxed/simple; bh=pqlexpUvH8SdD7gCfl41+7ECvKrO2BeW1xpubtVDq1Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Oh4YmqMobTSd1ebp7SDPLLEYDbSnSvALj091OXNg4VTajGhTcvX5VTlwOPny909HZEfliggZSMiPFr8CwgJ3Cg0mEo5AqkSaT6DpI7wy7/Rf6DMYHE+aJSqIDUXiJAI5VlQNOHhGFfZkz5N6CqJ+PBzav9y1YwzVzdao3Bndl1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=Z1M10y4R; arc=none smtp.client-ip=209.85.210.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Z1M10y4R" Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-70b4a8a5587so1462471b3a.2 for ; Fri, 12 Jul 2024 01:39:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1720773557; x=1721378357; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=qOZOdNqYBv8WGomeUEUfCET+0Nz9/2nmPAIIjSAFF/o=; b=Z1M10y4RcHm0MwYKLUt5M0nzBG5peIUs1FecTfR6DN/uf4J/cgrGJxuImRSAPzHhUK 6TGfbq10+U1Yx65ofoKCof9tCYFto9r1vAhtl7XA02swfv3BFI/kWMf9yMda3400qW5m 12jTIM1ixOV4wmG8TDdZY7UnQYfp/Lw5etSGaSvOAjMcYGxjFz07pBIJxohknJ3ON1kd ZvM/O4awuKALbPMhcmJ6ZdMdrowuXBPPPahAvCsSIocdj74YIizOEuAnHpN+P8b0gbMJ A2K/NQLvqa1aDPJGcvikBppmavYquFgGB6C8v2uJOdOJRNtfkYUyR7cHT62ofgaNADYu +a7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720773557; x=1721378357; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qOZOdNqYBv8WGomeUEUfCET+0Nz9/2nmPAIIjSAFF/o=; b=OZ+F0JmxtTQl5DHpHJ8itH/sYz8Q0dynsAGj/KXvj+a8pRDNV0CUtOAixbqdqF2ixq 366cbvIhQ3OWhqZqsgM14x9UgwVhPqqUllJr2Gst6MFs0l7AER8t5BMwycNQ5Eq/blOw YCS2qwjXmq1NA+RYuO3ttoiShFDcnF8uXV3W5ZopZfmmBWSRaBCN5lJZ1N45lAL1N2rf xDWpWOkzrRWDUfDyo7bZrVJ1xJ6gigEka+RVLeuQ5y9Fb2l/tfXVLKnYjBEDP/8Zb0ed xdXwTUiiOrQboErGpNXnzSAVfl7xhtFZZU/qukLHPb76pljDqTOBLxTfFb+lBba+CARg vH6g== X-Gm-Message-State: AOJu0YxqCoIZqk/JDY78lCd3DoEgD6QeFRNDRsdOzHRePCGxESCFC+Bd Iue9lR1Zragoe3fNGA/g403dEBnxoEK/gnyjAUaBJjh4/ifW8GUZVwOwvtMLt4A+hpUCHnBJvkU 5RRLf29yMfV3xDmId7xiHSIq/tkRdo3ZbiSFCVl+FfC4L1w13l1pYIW9RqwxG/gkt14/XduOKAi R6LgLB/+jD28iRbNBfczD8WhVDK5MN4ryU9KI2ScNJFnW3UqGQSWKBoQ== X-Google-Smtp-Source: AGHT+IFUgJGXqGz1rR6VQacB/sQPEJI/kBTqgZjcalyfvrrbdgNBckvS4WIfC6u8yM9C/ItjyrZEtw== X-Received: by 2002:a05:6a00:3392:b0:706:348a:528a with SMTP id d2e1a72fcca58-70b4355854fmr11327085b3a.10.1720773556295; Fri, 12 Jul 2024 01:39:16 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:16 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v7 3/4] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Date: Fri, 12 Jul 2024 16:38:47 +0800 Message-Id: <20240712083850.4242-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM and the Svade extension is allowed to disabledonly when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones Reviewed-by: Samuel Holland --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_onereg.c | 15 +++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e878e7cc3978..a5e0c35d7e9a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF, + KVM_RISCV_ISA_EXT_SVADE, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 17e21df36cc1..64a15af459e0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -540,6 +540,9 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu= *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |=3D ENVCFG_CBZE; =20 + if (riscv_isa_extension_available(isa, SVADU)) + cfg->henvcfg |=3D ENVCFG_ADUE; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { cfg->hstateen0 |=3D SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 62874fbca29f..474fdeafe9fe 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) @@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -105,6 +108,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned= long ext) return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SVADU: + /* + * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. + * Guest OS can use Svadu only when host os enable Svadu. + */ + return arch_has_hw_pte_young(); default: break; } @@ -167,6 +176,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigne= d long ext) /* Extensions which can be disabled using Smstateen */ case KVM_RISCV_ISA_EXT_SSAIA: return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN); + case KVM_RISCV_ISA_EXT_SVADE: + /* + * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. + * Svade is not allowed to disable when the platform use Svade. + */ + return arch_has_hw_pte_young(); default: break; } --=20 2.17.1 From nobody Fri Apr 11 18:34:53 2025 Received: from mail-oi1-f170.google.com (mail-oi1-f170.google.com [209.85.167.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B793514D714 for ; Fri, 12 Jul 2024 08:39:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720773563; cv=none; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b438c7099sm6894194b3a.84.2024.07.12.01.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 01:39:20 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org Subject: [PATCH v7 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Date: Fri, 12 Jul 2024 16:38:48 +0800 Message-Id: <20240712083850.4242-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240712083850.4242-1-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Update the get-reg-list test to test the Svade and Svadu Extensions are available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 222198dd6d04..1d32351ad55e 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVPBMT: @@ -411,6 +413,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -935,6 +939,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -991,6 +997,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_smstateen, &config_sscofpmf, &config_sstc, + &config_svade, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt, --=20 2.17.1