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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a871f0esm363750466b.194.2024.07.12.10.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 10:09:44 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 12 Jul 2024 18:09:43 +0100 Subject: [PATCH v4 1/2] clk: samsung: gs101: allow earlycon to work unconditionally Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240712-gs101-non-essential-clocks-2-v4-1-310aee0de46e@linaro.org> References: <20240712-gs101-non-essential-clocks-2-v4-0-310aee0de46e@linaro.org> In-Reply-To: <20240712-gs101-non-essential-clocks-2-v4-0-310aee0de46e@linaro.org> To: Peter Griffin , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Tudor Ambarus , Sam Protsenko Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 earlycon depends on the bootloader setup UART clocks being retained. This patch adds some logic to detect these clocks if earlycon is enabled, to bump their usage count during init and release them again at the end of init. This helps with cases where the UART clocks (or their parents) get disabled during loading of other drivers (e.g. i2c) causing earlycon to stop to work sometime into the boot, halting the whole system. The general idea is based on similar code in the i.MX clock driver, but since our clocks are coming from various different clock units, we have to run this code multiple times until all required UART clocks have probed. Signed-off-by: Andr=C3=A9 Draszik --- drivers/clk/samsung/clk-gs101.c | 100 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 85098c61c15e..429690757923 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -8,8 +8,13 @@ =20 #include #include +#include +#include +#include #include +#include #include +#include =20 #include =20 @@ -4381,6 +4386,99 @@ static const struct samsung_cmu_info peric1_cmu_info= __initconst =3D { =20 /* ---- platform_driver --------------------------------------------------= --- */ =20 +static struct { + struct mutex lock; + + bool bump_refs; + + struct clk **clks; + size_t n_clks; +} gs101_stdout_clks __initdata =3D { + .lock =3D __MUTEX_INITIALIZER(gs101_stdout_clks.lock), +}; + +static int __init gs101_keep_uart_clocks_param(char *str) +{ + gs101_stdout_clks.bump_refs =3D true; + return 0; +} +early_param("earlycon", gs101_keep_uart_clocks_param); + +static void __init gs101_bump_uart_clock_references(void) +{ + size_t n_clks; + + /* We only support device trees - do nothing if not available. */ + if (!IS_ENABLED(CONFIG_OF)) + return; + + n_clks =3D of_clk_get_parent_count(of_stdout); + if (!n_clks || !of_stdout) + return; + + mutex_lock(&gs101_stdout_clks.lock); + + /* + * We only need to run this code if required to do so, and if we have + * not succeeded previously, which will be the case if not all required + * clocks were ready yet during previous attempts. + */ + if (!gs101_stdout_clks.bump_refs) + goto out_unlock; + + if (!gs101_stdout_clks.clks) { + gs101_stdout_clks.n_clks =3D n_clks; + + gs101_stdout_clks.clks =3D kcalloc(gs101_stdout_clks.n_clks, + sizeof(*gs101_stdout_clks.clks), + GFP_KERNEL); + if (!gs101_stdout_clks.clks) + goto out_unlock; + } + + /* assume that this time we'll be able to grab all required clocks */ + gs101_stdout_clks.bump_refs =3D false; + for (size_t i =3D 0; i < n_clks; ++i) { + struct clk *clk; + + /* we might have grabbed this clock in a previous attempt */ + if (gs101_stdout_clks.clks[i]) + continue; + + clk =3D of_clk_get(of_stdout, i); + if (IS_ERR(clk)) { + /* + * clock might not have probed yet so we'll have to try + * again next time + */ + gs101_stdout_clks.bump_refs =3D true; + continue; + } + + if (clk_prepare_enable(clk)) { + clk_put(clk); + continue; + } + gs101_stdout_clks.clks[i] =3D clk; + } + +out_unlock: + mutex_unlock(&gs101_stdout_clks.lock); +} + +static int __init gs101_drop_extra_uart_clock_references(void) +{ + for (size_t i =3D 0; i < gs101_stdout_clks.n_clks; ++i) { + clk_disable_unprepare(gs101_stdout_clks.clks[i]); + clk_put(gs101_stdout_clks.clks[i]); + } + + kfree(gs101_stdout_clks.clks); + + return 0; +} +late_initcall_sync(gs101_drop_extra_uart_clock_references); + static int __init gs101_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -4389,6 +4487,8 @@ static int __init gs101_cmu_probe(struct platform_dev= ice *pdev) info =3D of_device_get_match_data(dev); exynos_arm64_register_cmu(dev, dev->of_node, info); =20 + gs101_bump_uart_clock_references(); + return 0; } =20 --=20 2.45.2.993.g49e7a77208-goog From nobody Wed Dec 17 08:52:58 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29450178CC3 for ; Fri, 12 Jul 2024 17:09:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720804189; cv=none; b=ng4z57XRfYXoekRzMeGztUvz+i1EfH+ChdUihfNsHFHywL/ATuaWrrjbSF0BXW3hNOjsZMTStZt/z9AKM+kXyrnumIkDoF0C42QQP1xF4Ddu5vCjg4wRHfs+KuWTEYmYse/vWmwvORH23E1/DcN32yo60z+8AVLh5M0cghC8KBc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720804189; c=relaxed/simple; bh=bSuhaMRom2cOObZWO5sZ0z5SXM43/G/at3phYRV+d3A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a871f0esm363750466b.194.2024.07.12.10.09.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jul 2024 10:09:45 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 12 Jul 2024 18:09:44 +0100 Subject: [PATCH v4 2/2] clk: samsung: gs101: don't mark non-essential (UART) clocks critical Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240712-gs101-non-essential-clocks-2-v4-2-310aee0de46e@linaro.org> References: <20240712-gs101-non-essential-clocks-2-v4-0-310aee0de46e@linaro.org> In-Reply-To: <20240712-gs101-non-essential-clocks-2-v4-0-310aee0de46e@linaro.org> To: Peter Griffin , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Tudor Ambarus , Sam Protsenko Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.13.0 The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. Since then, the DT has been updated to use the correct clock in commit 21e4e8807bfc ("arm64: dts: exynos: gs101: use correct clocks for usi_uart") and the driver here should be corrected and the work-around removed. Link: https://lore.kernel.org/all/d45de3b2bb6b48653842cf1f74e58889ed6783ae.= camel@linaro.org/ [1] Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v4: - the earlycon issue described in the commit message in previous versions of this patch is gone with "clk: samsung: gs101: allow earlycon to work unconditionally", so no need to mention anything v3: - add git commit SHA1s (Krzysztof) - add link to wordier description of earlycon issue v2: - commit message typo fixed - collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 429690757923..a6fc4d7e47fd 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -3951,20 +3951,18 @@ static const struct samsung_gate_clock peric0_gate_= clks[] __initconst =3D { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, CLK_SET_RATE_PARENT, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, --=20 2.45.2.993.g49e7a77208-goog