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Correct this. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: split from main apq8064 patch arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/= dts/qcom/qcom-apq8064-pins.dtsi index 7c545c50847b..107fc19f1331 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -11,19 +11,19 @@ pios { sdcc1_pins: sdcc1-pin-active { clk { pins =3D "sdc1_clk"; - drive-strengh =3D <16>; + drive-strength =3D <16>; bias-disable; }; =20 cmd { pins =3D "sdc1_cmd"; - drive-strengh =3D <10>; + drive-strength =3D <10>; bias-pull-up; }; =20 data { pins =3D "sdc1_data"; - drive-strengh =3D <10>; + drive-strength =3D <10>; bias-pull-up; }; }; @@ -31,19 +31,19 @@ data { sdcc3_pins: sdcc3-pin-active { clk { pins =3D "sdc3_clk"; - drive-strengh =3D <8>; + drive-strength =3D <8>; bias-disable; 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Thu, 11 Jul 2024 04:07:24 -0700 (PDT) From: Rayyan Ansari To: linux-arm-msm@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/5] ARM: dts: qcom: asus,nexus7-flo: remove duplicate pinctrl handle in i2c nodes Date: Thu, 11 Jul 2024 12:01:39 +0100 Message-ID: <20240711110545.31641-4-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240711110545.31641-2-rayyan.ansari@linaro.org> References: <20240711110545.31641-2-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove duplicate handle to i2c pins in the device tree, as they are already set in qcom-apq8064.dtsi. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: split from main apq8064 patch=20 arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch= /arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index d460743fbb94..947183992850 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -125,8 +125,6 @@ &gsbi1 { &gsbi1_i2c { status =3D "okay"; clock-frequency =3D <200000>; - pinctrl-0 =3D <&i2c1_pins>; - pinctrl-names =3D "default"; =20 eeprom@52 { compatible =3D "atmel,24c128"; @@ -148,8 +146,6 @@ &gsbi3 { =20 &gsbi3_i2c { clock-frequency =3D <200000>; - pinctrl-0 =3D <&i2c3_pins>; - pinctrl-names =3D "default"; status =3D "okay"; =20 trackpad@10 { --=20 2.45.2 From nobody Fri Dec 19 04:00:25 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3566516728E for ; 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Thu, 11 Jul 2024 04:07:33 -0700 (PDT) Received: from rayyan-pc.broadband ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4266f6e097bsm115686685e9.6.2024.07.11.04.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 04:07:33 -0700 (PDT) From: Rayyan Ansari To: linux-arm-msm@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 3/5] ARM: dts: qcom: apq8064: adhere to pinctrl dtschema Date: Thu, 11 Jul 2024 12:01:40 +0100 Message-ID: <20240711110545.31641-5-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240711110545.31641-2-rayyan.ansari@linaro.org> References: <20240711110545.31641-2-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pass dtbs_check for qcom,apq8064-pinctrl.yaml. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: split previous 2 commits from this patch, corrected commit message .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 25 +- .../boot/dts/qcom/qcom-apq8064-ifc6410.dts | 25 +- arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 350 +++++++----------- .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 10 +- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 34 +- 5 files changed, 166 insertions(+), 278 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/bo= ot/dts/qcom/qcom-apq8064-cm-qs600.dts index 671d58cc2741..178c55c1efeb 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -188,24 +188,17 @@ &sdcc4 { }; =20 &tlmm_pinmux { - card_detect: card_detect { - mux { - pins =3D "gpio26"; - function =3D "gpio"; - bias-disable; - }; + card_detect: card-detect-state { + pins =3D "gpio26"; + function =3D "gpio"; + bias-disable; }; =20 - pcie_pins: pcie_pinmux { - mux { - pins =3D "gpio27"; - function =3D "gpio"; - }; - conf { - pins =3D "gpio27"; - drive-strength =3D <12>; - bias-disable; - }; + pcie_pins: pcie-state { + pins =3D "gpio27"; + function =3D "gpio"; + drive-strength =3D <12>; + bias-disable; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boo= t/dts/qcom/qcom-apq8064-ifc6410.dts index ed86b24119c9..b3ff8010b149 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -321,24 +321,17 @@ &sdcc4 { }; =20 &tlmm_pinmux { - card_detect: card_detect { - mux { - pins =3D "gpio26"; - function =3D "gpio"; - bias-disable; - }; + card_detect: card-detect-state { + pins =3D "gpio26"; + function =3D "gpio"; + bias-disable; }; =20 - pcie_pins: pcie_pinmux { - mux { - pins =3D "gpio27"; - function =3D "gpio"; - }; - conf { - pins =3D "gpio27"; - drive-strength =3D <12>; - bias-disable; - }; + pcie_pins: pcie-state { + pins =3D "gpio27"; + function =3D "gpio"; + drive-strength =3D <12>; + bias-disable; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/= dts/qcom/qcom-apq8064-pins.dtsi index 107fc19f1331..e53de709e9d1 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -1,318 +1,218 @@ // SPDX-License-Identifier: GPL-2.0 =20 &tlmm_pinmux { - sdc4_gpios: sdc4-gpios { - pios { - pins =3D "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function =3D "sdc4"; - }; - }; - - sdcc1_pins: sdcc1-pin-active { - clk { + sdcc1_default_state: sdcc1-default-state { + clk-pins { pins =3D "sdc1_clk"; drive-strength =3D <16>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc1_cmd"; drive-strength =3D <10>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc1_data"; drive-strength =3D <10>; bias-pull-up; }; }; =20 - sdcc3_pins: sdcc3-pin-active { - clk { + sdcc3_default_state: sdcc3-default-state { + clk-pins { pins =3D "sdc3_clk"; drive-strength =3D <8>; bias-disable; }; =20 - cmd { + cmd-pins { pins =3D "sdc3_cmd"; drive-strength =3D <8>; bias-pull-up; }; =20 - data { + data-pins { pins =3D "sdc3_data"; drive-strength =3D <8>; bias-pull-up; }; }; =20 - ps_hold: ps_hold { - mux { - pins =3D "gpio78"; - function =3D "ps_hold"; - }; + sdc4_default_state: sdc4-default-state { + pins =3D "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function =3D "sdc4"; }; =20 - i2c1_pins: i2c1 { - mux { - pins =3D "gpio20", "gpio21"; - function =3D "gsbi1"; - }; + gsbi1_uart_2pins: gsbi1-uart-2pins-state { + pins =3D "gpio18", "gpio19"; + function =3D "gsbi1"; + }; =20 - pinconf { - pins =3D "gpio20", "gpio21"; - drive-strength =3D <16>; - bias-disable; - }; + gsbi1_uart_4pins: gsbi1-uart-4pins-state { + pins =3D "gpio18", "gpio19", "gpio20", "gpio21"; + function =3D "gsbi1"; }; =20 - i2c1_pins_sleep: i2c1_pins_sleep { - mux { - pins =3D "gpio20", "gpio21"; - function =3D "gpio"; - }; - pinconf { - pins =3D "gpio20", "gpio21"; + gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { + rx-pins { + pins =3D "gpio11"; + function =3D "gsbi4"; drive-strength =3D <2>; bias-disable; }; - }; =20 - gsbi1_uart_2pins: gsbi1_uart_2pins { - mux { - pins =3D "gpio18", "gpio19"; - function =3D "gsbi1"; + tx-pins { + pins =3D "gpio10"; + function =3D "gsbi4"; + drive-strength =3D <4>; + bias-disable; }; }; =20 - gsbi1_uart_4pins: gsbi1_uart_4pins { - mux { - pins =3D "gpio18", "gpio19", "gpio20", "gpio21"; - function =3D "gsbi1"; - }; + gsbi6_uart_2pins: gsbi6-uart-2pins-state { + pins =3D "gpio14", "gpio15"; + function =3D "gsbi6"; }; =20 - i2c2_pins: i2c2 { - mux { - pins =3D "gpio24", "gpio25"; - function =3D "gsbi2"; - }; - - pinconf { - pins =3D "gpio24", "gpio25"; - drive-strength =3D <16>; - bias-disable; - }; + gsbi6_uart_4pins: gsbi6-uart-4pins-state { + pins =3D "gpio14", "gpio15", "gpio16", "gpio17"; + function =3D "gsbi6"; }; =20 - i2c2_pins_sleep: i2c2_pins_sleep { - mux { - pins =3D "gpio24", "gpio25"; - function =3D "gpio"; - }; - - pinconf { - pins =3D "gpio24", "gpio25"; - drive-strength =3D <2>; - bias-disable; - }; + gsbi7_uart_2pins: gsbi7-uart-2pins-state { + pins =3D "gpio82", "gpio83"; + function =3D "gsbi7"; }; =20 - i2c3_pins: i2c3 { - mux { - pins =3D "gpio8", "gpio9"; - function =3D "gsbi3"; - }; - - pinconf { - pins =3D "gpio8", "gpio9"; - drive-strength =3D <16>; - bias-disable; - }; + gsbi7_uart_4pins: gsbi7_uart_4pins-state { + pins =3D "gpio82", "gpio83", "gpio84", "gpio85"; + function =3D "gsbi7"; }; =20 - i2c3_pins_sleep: i2c3_pins_sleep { - mux { - pins =3D "gpio8", "gpio9"; - function =3D "gpio"; - }; - pinconf { - pins =3D "gpio8", "gpio9"; - drive-strength =3D <2>; - bias-disable; - }; + i2c1_default_state: i2c1-default-state { + pins =3D "gpio20", "gpio21"; + function =3D "gsbi1"; + drive-strength =3D <16>; + bias-disable; }; =20 - i2c4_pins: i2c4 { - mux { - pins =3D "gpio12", "gpio13"; - function =3D "gsbi4"; - }; - - pinconf { - pins =3D "gpio12", "gpio13"; - drive-strength =3D <16>; - bias-disable; - }; + i2c1_sleep_state: i2c1-sleep-state { + pins =3D "gpio20", "gpio21"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - i2c4_pins_sleep: i2c4_pins_sleep { - mux { - pins =3D "gpio12", "gpio13"; - function =3D "gpio"; - }; - pinconf { - pins =3D "gpio12", "gpio13"; - drive-strength =3D <2>; - bias-disable; - }; + i2c2_default_state: i2c2-default-state { + pins =3D "gpio24", "gpio25"; + function =3D "gsbi2"; + drive-strength =3D <16>; + bias-disable; }; =20 - spi5_default: spi5_default { - pinmux { - pins =3D "gpio51", "gpio52", "gpio54"; - function =3D "gsbi5"; - }; - - pinmux_cs { - function =3D "gpio"; - pins =3D "gpio53"; - }; - - pinconf { - pins =3D "gpio51", "gpio52", "gpio54"; - drive-strength =3D <16>; - bias-disable; - }; - - pinconf_cs { - pins =3D "gpio53"; - drive-strength =3D <16>; - bias-disable; - output-high; - }; + i2c2_sleep_state: i2c2-sleep-state { + pins =3D "gpio24", "gpio25"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - spi5_sleep: spi5_sleep { - pinmux { - function =3D "gpio"; - pins =3D "gpio51", "gpio52", "gpio53", "gpio54"; - }; - - pinconf { - pins =3D "gpio51", "gpio52", "gpio53", "gpio54"; - drive-strength =3D <2>; - bias-pull-down; - }; + i2c3_default_state: i2c3-default-state { + pins =3D "gpio8", "gpio9"; + function =3D "gsbi3"; + drive-strength =3D <16>; + bias-disable; }; =20 - i2c6_pins: i2c6 { - mux { - pins =3D "gpio16", "gpio17"; - function =3D "gsbi6"; - }; - - pinconf { - pins =3D "gpio16", "gpio17"; - drive-strength =3D <16>; - bias-disable; - }; + i2c3_sleep_state: i2c3-sleep-state { + pins =3D "gpio8", "gpio9"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - i2c6_pins_sleep: i2c6_pins_sleep { - mux { - pins =3D "gpio16", "gpio17"; - function =3D "gpio"; - }; - pinconf { - pins =3D "gpio16", "gpio17"; - drive-strength =3D <2>; - bias-disable; - }; + i2c4_default_state: i2c4-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "gsbi4"; + drive-strength =3D <16>; + bias-disable; }; =20 - gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { - rx-pins { - pins =3D "gpio11"; - function =3D "gsbi4"; - drive-strength =3D <2>; - bias-disable; - }; - - tx-pins { - pins =3D "gpio10"; - function =3D "gsbi4"; - drive-strength =3D <4>; - bias-disable; - }; + i2c4_sleep_state: i2c4-sleep-state { + pins =3D "gpio12", "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - gsbi6_uart_2pins: gsbi6_uart_2pins { - mux { - pins =3D "gpio14", "gpio15"; - function =3D "gsbi6"; - }; + i2c6_default_state: i2c6-default-state { + pins =3D "gpio16", "gpio17"; + function =3D "gsbi6"; + drive-strength =3D <16>; + bias-disable; }; =20 - gsbi6_uart_4pins: gsbi6_uart_4pins { - mux { - pins =3D "gpio14", "gpio15", "gpio16", "gpio17"; - function =3D "gsbi6"; - }; + i2c6_sleep_state: i2c6-sleep-state { + pins =3D "gpio16", "gpio17"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - gsbi7_uart_2pins: gsbi7_uart_2pins { - mux { - pins =3D "gpio82", "gpio83"; - function =3D "gsbi7"; - }; + i2c7_default_state: i2c7-default-state { + pins =3D "gpio84", "gpio85"; + function =3D "gsbi7"; + drive-strength =3D <16>; + bias-disable; }; =20 - gsbi7_uart_4pins: gsbi7_uart_4pins { - mux { - pins =3D "gpio82", "gpio83", "gpio84", "gpio85"; - function =3D "gsbi7"; - }; + i2c7_sleep_state: i2c7-sleep-state { + pins =3D "gpio84", "gpio85"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; }; =20 - i2c7_pins: i2c7 { - mux { - pins =3D "gpio84", "gpio85"; - function =3D "gsbi7"; + spi5_default_state: spi5-default-state { + spi5-pins { + pins =3D "gpio51", "gpio52", "gpio54"; + function =3D "gsbi5"; + drive-strength =3D <16>; + bias-disable; }; =20 - pinconf { - pins =3D "gpio84", "gpio85"; + spi5-cs-pins { + pins =3D "gpio53"; + function =3D "gpio"; drive-strength =3D <16>; bias-disable; + output-high; }; }; =20 - i2c7_pins_sleep: i2c7_pins_sleep { - mux { - pins =3D "gpio84", "gpio85"; + spi5_sleep_state: spi5-sleep-state { + spi5-pins { + pins =3D "gpio51", "gpio52", "gpio53", "gpio54"; function =3D "gpio"; - }; - pinconf { - pins =3D "gpio84", "gpio85"; drive-strength =3D <2>; - bias-disable; + bias-pull-down; }; }; =20 - riva_fm_pin_a: riva-fm-active { + riva_fm_pin_a: riva-fm-active-state { pins =3D "gpio14", "gpio15"; function =3D "riva_fm"; }; =20 - riva_bt_pin_a: riva-bt-active { + riva_bt_pin_a: riva-bt-active-state { pins =3D "gpio16", "gpio17"; function =3D "riva_bt"; }; =20 - riva_wlan_pin_a: riva-wlan-active { + riva_wlan_pin_a: riva-wlan-active-state { pins =3D "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; function =3D "riva_wlan"; =20 @@ -320,22 +220,24 @@ riva_wlan_pin_a: riva-wlan-active { bias-pull-down; }; =20 - hdmi_pinctrl: hdmi-pinctrl { - mux { - pins =3D "gpio70", "gpio71", "gpio72"; - function =3D "hdmi"; - }; - - pinconf_ddc { + hdmi_pinctrl: hdmi-pinctrl-state { + ddc-pins { pins =3D "gpio70", "gpio71"; + function =3D "hdmi"; bias-pull-up; drive-strength =3D <2>; }; =20 - pinconf_hpd { + hpd-pins { pins =3D "gpio72"; + function =3D "hdmi"; bias-pull-down; drive-strength =3D <16>; }; }; + + ps_hold_default_state: ps-hold-default-state { + pins =3D "gpio78"; + function =3D "ps_hold"; + }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts= b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 2412aa3e3e8d..7752f07973f9 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -373,21 +373,21 @@ &sdcc3 { cd-gpios =3D <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; =20 pinctrl-names =3D "default"; - pinctrl-0 =3D <&sdcc3_pins>, <&sdcc3_cd_pin_a>; + pinctrl-0 =3D <&sdcc3_default_state>, <&sdcc3_cd_pin_a>; =20 status =3D "okay"; }; =20 &tlmm_pinmux { - gsbi5_uart_pin_a: gsbi5-uart-pin-active { - rx { + gsbi5_uart_pin_a: gsbi5-uart-pin-active-state { + rx-pins { pins =3D "gpio52"; function =3D "gsbi5"; drive-strength =3D <2>; bias-pull-up; }; =20 - tx { + tx-pins { pins =3D "gpio51"; function =3D "gsbi5"; drive-strength =3D <4>; @@ -396,7 +396,7 @@ tx { }; =20 =20 - sdcc3_cd_pin_a: sdcc3-cd-pin-active { + sdcc3_cd_pin_a: sdcc3-cd-pin-active-state { pins =3D "gpio26"; function =3D "gpio"; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-apq8064.dtsi index 769e151747c3..00f273ffea9c 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -302,7 +302,7 @@ tlmm_pinmux: pinctrl@800000 { interrupts =3D ; =20 pinctrl-names =3D "default"; - pinctrl-0 =3D <&ps_hold>; + pinctrl-0 =3D <&ps_hold_default_state>; }; =20 sfpb_wrapper_mutex: syscon@1200000 { @@ -435,8 +435,8 @@ gsbi1_serial: serial@12450000 { =20 gsbi1_i2c: i2c@12460000 { compatible =3D "qcom,i2c-qup-v1.1.1"; - pinctrl-0 =3D <&i2c1_pins>; - pinctrl-1 =3D <&i2c1_pins_sleep>; + pinctrl-0 =3D <&i2c1_default_state>; + pinctrl-1 =3D <&i2c1_sleep_state>; pinctrl-names =3D "default", "sleep"; reg =3D <0x12460000 0x1000>; interrupts =3D ; @@ -465,8 +465,8 @@ gsbi2: gsbi@12480000 { gsbi2_i2c: i2c@124a0000 { compatible =3D "qcom,i2c-qup-v1.1.1"; reg =3D <0x124a0000 0x1000>; - pinctrl-0 =3D <&i2c2_pins>; - pinctrl-1 =3D <&i2c2_pins_sleep>; + pinctrl-0 =3D <&i2c2_default_state>; + pinctrl-1 =3D <&i2c2_sleep_state>; pinctrl-names =3D "default", "sleep"; interrupts =3D ; clocks =3D <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; @@ -489,8 +489,8 @@ gsbi3: gsbi@16200000 { ranges; gsbi3_i2c: i2c@16280000 { compatible =3D "qcom,i2c-qup-v1.1.1"; - pinctrl-0 =3D <&i2c3_pins>; - pinctrl-1 =3D <&i2c3_pins_sleep>; + pinctrl-0 =3D <&i2c3_default_state>; + pinctrl-1 =3D <&i2c3_sleep_state>; pinctrl-names =3D "default", "sleep"; reg =3D <0x16280000 0x1000>; interrupts =3D ; @@ -528,8 +528,8 @@ gsbi4_serial: serial@16340000 { =20 gsbi4_i2c: i2c@16380000 { compatible =3D "qcom,i2c-qup-v1.1.1"; - pinctrl-0 =3D <&i2c4_pins>; - pinctrl-1 =3D <&i2c4_pins_sleep>; + pinctrl-0 =3D <&i2c4_default_state>; + pinctrl-1 =3D <&i2c4_sleep_state>; pinctrl-names =3D "default", "sleep"; reg =3D <0x16380000 0x1000>; interrupts =3D ; @@ -565,8 +565,8 @@ gsbi5_spi: spi@1a280000 { compatible =3D "qcom,spi-qup-v1.1.1"; reg =3D <0x1a280000 0x1000>; interrupts =3D ; - pinctrl-0 =3D <&spi5_default>; - pinctrl-1 =3D <&spi5_sleep>; + pinctrl-0 =3D <&spi5_default_state>; + pinctrl-1 =3D <&spi5_sleep_state>; pinctrl-names =3D "default", "sleep"; clocks =3D <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names =3D "core", "iface"; @@ -599,8 +599,8 @@ gsbi6_serial: serial@16540000 { =20 gsbi6_i2c: i2c@16580000 { compatible =3D "qcom,i2c-qup-v1.1.1"; - pinctrl-0 =3D <&i2c6_pins>; - pinctrl-1 =3D <&i2c6_pins_sleep>; + pinctrl-0 =3D <&i2c6_default_state>; + pinctrl-1 =3D <&i2c6_sleep_state>; pinctrl-names =3D "default", "sleep"; reg =3D <0x16580000 0x1000>; interrupts =3D ; @@ -635,8 +635,8 @@ gsbi7_serial: serial@16640000 { =20 gsbi7_i2c: i2c@16680000 { compatible =3D "qcom,i2c-qup-v1.1.1"; - pinctrl-0 =3D <&i2c7_pins>; - pinctrl-1 =3D <&i2c7_pins_sleep>; + pinctrl-0 =3D <&i2c7_default_state>; + pinctrl-1 =3D <&i2c7_sleep_state>; pinctrl-names =3D "default", "sleep"; reg =3D <0x16680000 0x1000>; interrupts =3D ; @@ -945,7 +945,7 @@ sdcc4: mmc@121c0000 { dmas =3D <&sdcc4bam 2>, <&sdcc4bam 1>; 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Thu, 11 Jul 2024 04:07:37 -0700 (PDT) From: Rayyan Ansari To: linux-arm-msm@vger.kernel.org Cc: Rayyan Ansari , Krzysztof Kozlowski , Bjorn Andersson , Conor Dooley , devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 4/5] ARM: dts: qcom: ipq8064: adhere to pinctrl dtschema Date: Thu, 11 Jul 2024 12:01:41 +0100 Message-ID: <20240711110545.31641-6-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240711110545.31641-2-rayyan.ansari@linaro.org> References: <20240711110545.31641-2-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pass dtbs_check for qcom,ipq8064-pinctrl.yaml. Also remove invalid "bias-none" property, which I have assumed to mean "bias-disable". Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: corrected commit message, added r-b tag arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts | 11 +- .../arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts | 76 +++++------- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 114 ++++++++---------- 3 files changed, 87 insertions(+), 114 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts b/arch/arm/boot/= dts/qcom/qcom-ipq8064-ap148.dts index a654d3c22c4f..5a8bf1a6f559 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts @@ -7,12 +7,11 @@ / { =20 soc { pinmux@800000 { - buttons_pins: buttons_pins { - mux { - pins =3D "gpio54", "gpio65"; - drive-strength =3D <2>; - bias-pull-up; - }; + buttons_pins: buttons-state { + pins =3D "gpio54", "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot= /dts/qcom/qcom-ipq8064-rb3011.dts index 12e806adcda8..f09da9460c86 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -404,59 +404,49 @@ main@800000 { }; =20 &qcom_pinmux { - buttons_pins: buttons_pins { - mux { - pins =3D "gpio66"; - drive-strength =3D <16>; - bias-disable; - }; + buttons_pins: buttons-state { + pins =3D "gpio66"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; }; =20 - leds_pins: leds_pins { - mux { - pins =3D "gpio33"; - drive-strength =3D <16>; - bias-disable; - }; + leds_pins: leds-state { + pins =3D "gpio33"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; }; =20 - mdio1_pins: mdio1_pins { - mux { - pins =3D "gpio10", "gpio11"; - function =3D "gpio"; - drive-strength =3D <8>; - bias-disable; - }; + mdio1_pins: mdio1-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; }; =20 - sw0_reset_pin: sw0_reset_pin { - mux { - pins =3D "gpio16"; - drive-strength =3D <16>; - function =3D "gpio"; - bias-disable; - input-disable; - }; + sw0_reset_pin: sw0-reset-state { + pins =3D "gpio16"; + drive-strength =3D <16>; + function =3D "gpio"; + bias-disable; + input-disable; }; =20 - sw1_reset_pin: sw1_reset_pin { - mux { - pins =3D "gpio17"; - drive-strength =3D <16>; - function =3D "gpio"; - bias-disable; - input-disable; - }; + sw1_reset_pin: sw1-reset-state { + pins =3D "gpio17"; + drive-strength =3D <16>; + function =3D "gpio"; + bias-disable; + input-disable; }; =20 - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins =3D "gpio4"; - function =3D "gpio"; - drive-strength =3D <16>; - bias-disable; - output-high; - }; + usb1_pwr_en_pins: usb1-pwr-en-state { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-high; }; }; =20 diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/q= com/qcom-ipq8064.dtsi index da0fd75f4711..9adefc88c5b4 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -399,70 +399,58 @@ qcom_pinmux: pinmux@800000 { #interrupt-cells =3D <2>; interrupts =3D ; =20 - pcie0_pins: pcie0_pinmux { - mux { - pins =3D "gpio3"; - function =3D "pcie1_rst"; - drive-strength =3D <12>; - bias-disable; - }; + pcie0_pins: pcie0-state { + pins =3D "gpio3"; + function =3D "pcie1_rst"; + drive-strength =3D <12>; + bias-disable; }; =20 - pcie1_pins: pcie1_pinmux { - mux { - pins =3D "gpio48"; - function =3D "pcie2_rst"; - drive-strength =3D <12>; - bias-disable; - }; + pcie1_pins: pcie1-state { + pins =3D "gpio48"; + function =3D "pcie2_rst"; + drive-strength =3D <12>; + bias-disable; }; =20 - pcie2_pins: pcie2_pinmux { - mux { - pins =3D "gpio63"; - function =3D "pcie3_rst"; - drive-strength =3D <12>; - bias-disable; - }; + pcie2_pins: pcie2-state { + pins =3D "gpio63"; + function =3D "pcie3_rst"; + drive-strength =3D <12>; + bias-disable; }; =20 - i2c4_pins: i2c4-default { + i2c4_pins: i2c4-state { pins =3D "gpio12", "gpio13"; function =3D "gsbi4"; drive-strength =3D <12>; bias-disable; }; =20 - spi_pins: spi_pins { - mux { - pins =3D "gpio18", "gpio19", "gpio21"; - function =3D "gsbi5"; - drive-strength =3D <10>; - bias-none; - }; + spi_pins: spi-state { + pins =3D "gpio18", "gpio19", "gpio21"; + function =3D "gsbi5"; + drive-strength =3D <10>; + bias-disable; }; =20 - leds_pins: leds_pins { - mux { - pins =3D "gpio7", "gpio8", "gpio9", - "gpio26", "gpio53"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-down; - output-low; - }; + leds_pins: leds-state { + pins =3D "gpio7", "gpio8", "gpio9", + "gpio26", "gpio53"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + output-low; }; =20 - buttons_pins: buttons_pins { - mux { - pins =3D "gpio54"; - drive-strength =3D <2>; - bias-pull-up; - }; + buttons_pins: buttons-state { + pins =3D "gpio54"; + drive-strength =3D <2>; + bias-pull-up; }; =20 - nand_pins: nand_pins { - mux { + nand_pins: nand-state { + nand-pins { pins =3D "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", @@ -473,14 +461,14 @@ mux { bias-disable; }; =20 - pullups { + nand-pullup-pins { pins =3D "gpio39"; function =3D "nand"; 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charset="utf-8" Pass dtbs_check for qcom,ipq4019-pinctrl.yaml. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: corrected commit message, added r-b tag .../boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 34 ++++++++----------- .../boot/dts/qcom/qcom-ipq4018-jalapeno.dts | 27 ++++++--------- .../boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 26 +++++--------- .../boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 14 ++++---- .../dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts | 8 ++--- .../dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts | 2 +- .../boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi | 6 ++-- 7 files changed, 50 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/= boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index da67d55fa557..0d23c03fae33 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -28,46 +28,42 @@ key-reset { }; =20 &tlmm { - i2c0_pins: i2c0_pinmux { - mux_i2c { - function =3D "blsp_i2c0"; - pins =3D "gpio58", "gpio59"; - drive-strength =3D <16>; - bias-disable; - }; + i2c0_pins: i2c0-state { + function =3D "blsp_i2c0"; + pins =3D "gpio58", "gpio59"; + drive-strength =3D <16>; + bias-disable; }; =20 - mdio_pins: mdio_pinmux { - mux_mdio { + mdio_pins: mdio-state { + mdio-pins { pins =3D "gpio53"; function =3D "mdio"; bias-pull-up; }; =20 - mux_mdc { + mdc-pins { pins =3D "gpio52"; function =3D "mdc"; bias-pull-up; }; }; =20 - serial0_pins: serial0_pinmux { - mux_uart { - pins =3D "gpio60", "gpio61"; - function =3D "blsp_uart0"; - bias-disable; - }; + serial0_pins: serial0-state { + pins =3D "gpio60", "gpio61"; + function =3D "blsp_uart0"; + bias-disable; }; =20 - spi0_pins: spi0_pinmux { - mux_spi { + spi0_pins: spi0-state { + spi0-pins { function =3D "blsp_spi0"; pins =3D "gpio55", "gpio56", "gpio57"; drive-strength =3D <12>; bias-disable; }; =20 - mux_cs { + spi0-cs-pins { function =3D "gpio"; pins =3D "gpio54", "gpio4"; drive-strength =3D <2>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/bo= ot/dts/qcom/qcom-ipq4018-jalapeno.dts index 365fbac417fd..ac3b30072a22 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -11,40 +11,35 @@ / { }; =20 &tlmm { - mdio_pins: mdio_pinmux { - pinmux_1 { + mdio_pins: mdio-state { + mdio-pins { pins =3D "gpio53"; function =3D "mdio"; + bias-pull-up; }; =20 - pinmux_2 { + mdc-pins { pins =3D "gpio52"; function =3D "mdc"; - }; - - pinconf { - pins =3D "gpio52", "gpio53"; bias-pull-up; }; }; =20 - serial_pins: serial_pinmux { - mux { - pins =3D "gpio60", "gpio61"; - function =3D "blsp_uart0"; - bias-disable; - }; + serial_pins: serial-state{ + pins =3D "gpio60", "gpio61"; + function =3D "blsp_uart0"; + bias-disable; }; =20 - spi_0_pins: spi_0_pinmux { - pin { + spi_0_pins: spi-0-state { + spi0-pins { function =3D "blsp_spi0"; pins =3D "gpio55", "gpio56", "gpio57"; drive-strength =3D <2>; bias-disable; }; =20 - pin_cs { + spi0-cs-pins { function =3D "gpio"; pins =3D "gpio54", "gpio59"; drive-strength =3D <2>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/= boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi index f7ac8f9d0b6f..efbe89dd4793 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi @@ -34,30 +34,22 @@ &prng { }; =20 &tlmm { - serial_pins: serial_pinmux { - mux { - pins =3D "gpio60", "gpio61"; - function =3D "blsp_uart0"; - bias-disable; - }; + serial_pins: serial-state { + pins =3D "gpio60", "gpio61"; + function =3D "blsp_uart0"; + bias-disable; }; =20 - spi_0_pins: spi_0_pinmux { - pinmux { - function =3D "blsp_spi0"; - pins =3D "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function =3D "gpio"; - pins =3D "gpio54"; - }; - pinconf { + spi_0_pins: spi-0-state { + spi0-pins { pins =3D "gpio55", "gpio56", "gpio57"; + function =3D "blsp_spi0"; drive-strength =3D <12>; bias-disable; }; - pinconf_cs { + spi0-cs-pins { pins =3D "gpio54"; + function =3D "gpio"; drive-strength =3D <2>; bias-disable; output-high; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/= boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi index 374af6dd360a..91e296d2ea82 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -24,26 +24,26 @@ memory { =20 soc { pinctrl@1000000 { - serial_0_pins: serial0-pinmux { + serial_0_pins: serial0-state { pins =3D "gpio16", "gpio17"; function =3D "blsp_uart0"; bias-disable; }; =20 - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; function =3D "blsp_uart1"; bias-disable; }; =20 - spi_0_pins: spi-0-pinmux { - pinmux { + spi_0_pins: spi-0-state { + spi0-pins { function =3D "blsp_spi0"; pins =3D "gpio13", "gpio14", "gpio15"; bias-disable; }; - pinmux_cs { + spi0-cs-pins { function =3D "gpio"; pins =3D "gpio12"; bias-disable; @@ -51,13 +51,13 @@ pinmux_cs { }; }; =20 - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins =3D "gpio20", "gpio21"; function =3D "blsp_i2c0"; bias-disable; }; =20 - nand_pins: nand-pins { + nand_pins: nand-state { pins =3D "gpio53", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio62", "gpio63", diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/ar= m/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts index ea2987fcbff8..41c5874f6f97 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts @@ -19,20 +19,20 @@ spi@78b6000 { }; =20 pinctrl@1000000 { - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; function =3D "blsp_uart1"; bias-disable; }; =20 - spi_0_pins: spi-0-pinmux { - pinmux { + spi_0_pins: spi-0-state { + spi0-pins { function =3D "blsp_spi0"; pins =3D "gpio13", "gpio14", "gpio15"; bias-disable; }; - pinmux_cs { + spio-cs-pins { function =3D "gpio"; pins =3D "gpio12"; bias-disable; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/ar= m/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts index bd3553dd2070..67ee99d69757 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts @@ -9,7 +9,7 @@ / { =20 soc { pinctrl@1000000 { - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins =3D "gpio8", "gpio9"; function =3D "blsp_uart1"; bias-disable; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/= boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index 7ef635997efa..cc88cf5f0d9b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -24,19 +24,19 @@ chosen { =20 soc { pinctrl@1000000 { - serial_0_pins: serial0-pinmux { + serial_0_pins: serial0-state { pins =3D "gpio16", "gpio17"; function =3D "blsp_uart0"; bias-disable; }; =20 - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins =3D "gpio20", "gpio21"; function =3D "blsp_i2c0"; bias-disable; }; =20 - nand_pins: nand-pins { + nand_pins: nand-state { pins =3D "gpio53", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio62", "gpio63", --=20 2.45.2