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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c99a95624dsm10689540a91.20.2024.07.09.18.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 18:17:03 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 5526B80D2B; Wed, 10 Jul 2024 09:26:28 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH 2/3] mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT Date: Wed, 10 Jul 2024 09:15:40 +0800 Message-Id: <20240710011541.342682-3-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240710011541.342682-1-linchengming884@gmail.com> References: <20240710011541.342682-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index 3f9e9c572854..c61f1ba31f0c 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -100,6 +100,39 @@ static int mx35lf1ge4ab_ecc_get_status(struct spinand_= device *spinand, return -EINVAL; } =20 +/** + * Macronix serial NAND flash with a two-plane structure + * should insert Plane Select bit into the column address + * during the write_to_cache operation. + * Additionally, MX35{U,F}2G14AC also need to insert Plane + * Select bit into the column address during the read_from_cache + * operation. + */ +static unsigned int write_Plane_Select_bit_in_cadd(struct spinand_device *= spinand, + const struct nand_page_io_req *req, unsigned int column) +{ + struct nand_device *nand =3D spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static u16 read_Plane_Select_bit_in_cadd(struct spinand_device *spinand, + const struct nand_page_io_req *req, u16 column) +{ + struct nand_device *nand =3D spinand_to_nand(spinand); + + return column | (req->pos.plane << fls(nanddev_page_size(nand))); +} + +static const struct spi_nand_fixups write_fixups =3D { + .write_to_cache =3D write_Plane_Select_bit_in_cadd, +}; + +static const struct spi_nand_fixups read_and_write_fixups =3D { + .write_to_cache =3D write_Plane_Select_bit_in_cadd, + .read_from_cache =3D read_Plane_Select_bit_in_cadd, +}; + static const struct spinand_info macronix_spinand_table[] =3D { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -157,7 +190,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -175,7 +209,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -215,7 +250,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -225,7 +261,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -255,7 +292,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&read_and_write_fixups)), SPINAND_INFO("MX35UF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -265,7 +303,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { &update_cache_variants), SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, - mx35lf1ge4ab_ecc_get_status)), + mx35lf1ge4ab_ecc_get_status), + SPINAND_PLANE_SELECT_BIT(&write_fixups)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), --=20 2.25.1