From nobody Fri Sep 20 01:36:24 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E15DF1527A7 for ; Wed, 10 Jul 2024 08:52:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720601575; cv=none; b=J0xW1bKPoDI+IeCnbT/sZ5VRk0ITaeLXKBfh6lq3tO0gouQzAU5IilatCE24atRAcfVXXkTn+AW28qiHWCiC9b4gEXikeo2DopylDVaeeFv+MJ7TOjCi4oCUQMaHZ4OOALvFVrKumF4IYEvUsVVr7Ae3YG78SgwjGz8DsKHXY74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720601575; c=relaxed/simple; bh=tfabwBvvONPi6G1imBOAg7bICWXSe8zF8QtpBuR5L0s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gVG5qoAIJmxhE+7KDSGTZGpSO9ah2VyCUljlCjELMLe9naq90glAIoKQrc/Jp/K+cBieBef7qIfaOyLimXw3lHwOg8VwRrwp9b/xq3KSCiowKzsWPit10py6KE+Uhy3KNuK/CxT3xh05tdSowlMYoof2MlR2k6KLMJnfRjlTqCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fE8DpEo7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fE8DpEo7" Received: by smtp.kernel.org (Postfix) with ESMTPS id 91461C32786; Wed, 10 Jul 2024 08:52:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720601574; bh=tfabwBvvONPi6G1imBOAg7bICWXSe8zF8QtpBuR5L0s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fE8DpEo7oLB67fr9MBZkFR7jZWWurjdqEd2CnObxrdZLhQGrZmvDrNBa0w6lhpSlX XcD4l1+t3t0Rx8tFhk/YrsrXhG6jO+BhbaEd9sfy5j5qAwmPVw2TYrbp6zaF3xGc1H Wk6fKPlGcNp6+XfMe2P0wXAB7OJFberhsVZaOYZP6p8+SOq+XY96A1zjl8BpJEqDoW jsP1fK19Y6JGD7A2FOAXSzq9JIgRwgLRHXcUKjXH5S9uikH+DSw8dQ21G3lrEWJwKL QHrUOrwXJ6KYhYpIw3QfAi3LUvkuJLI4jePJK5uU5ovJkeD29AknHWms1pKcY/yXGY G7hrOke6BHopg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 805B0C3DA45; Wed, 10 Jul 2024 08:52:54 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 10 Jul 2024 16:52:51 +0800 Subject: [PATCH v3 1/5] drm/mediatek: Support "None" blending in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240710-alpha-blending-v3-1-289c187f9c6f@mediatek.com> References: <20240710-alpha-blending-v3-0-289c187f9c6f@mediatek.com> In-Reply-To: <20240710-alpha-blending-v3-0-289c187f9c6f@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , CK Hu , Hsiao Chien Sung X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720601573; l=1452; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=XPDvZ7xzyMMnOIwBspXj+lmld62ksCxAgrZn9GTIqIg=; b=HsOsrqhmRFl9fOXtcJXMLvv7rJjJpW6kf0KLPrSnRxb0hCnapq32yLAZm87y5QwTs/neDBkI/ RNVEsgjQwWGClW02cW487yVZf0rmheO51TuYbL+5AP8CYBueAfgYWIr X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "None" alpha blending mode on MediaTek's chips. Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 9d6d9fd8342e..add671c38613 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -434,6 +434,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int blend_mode =3D state->base.pixel_blend_mode; unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; @@ -463,7 +464,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, * For RGB888 related formats, whether CONST_BLD is enabled or not won't * affect the result. Therefore we use !has_alpha as the condition. */ - if (state->base.fb && !state->base.fb->format->has_alpha) + if ((state->base.fb && !state->base.fb->format->has_alpha) || + blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { --=20 2.43.0