From nobody Thu Sep 19 23:10:02 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 263EE13D53A for ; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; cv=none; b=C/JV7iPjQDtQNGVN/UE+6h8UTGfA1FseGjp8Y4Bu75hNm+qlASqPh4fLr3MQQPt2rToq061zvlETGfbKOUwSDyQ0wcb4QDCfU0wwzNKful5S2+nqX3H6tPcNOexMgkEe8kp1XTxMnFIt+0V3HuDI5ApfYlohlM5Tx2HkQUswdlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; c=relaxed/simple; bh=tfabwBvvONPi6G1imBOAg7bICWXSe8zF8QtpBuR5L0s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p5dG3cV84p+NSh6E1O4RZutaeVJU4kvy10AODiuOcSYyKwzdnd40RFhCseCrLZsvahthmqneBnyWh5uXxwfAQnTjTFVLAH76hPP+/h/poDIRkF8RxKywVKvaSGlaqFaRQ19mZnGodqExqX7F+6dBEWaaFrCFoGLTCc87XJ9y7JI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sxofKbwx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sxofKbwx" Received: by smtp.kernel.org (Postfix) with ESMTPS id B85ADC32786; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720600642; bh=tfabwBvvONPi6G1imBOAg7bICWXSe8zF8QtpBuR5L0s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=sxofKbwxJrcZPRM3OnpVr7hAH1vyRhNrYVD65gNKcDv9gSyh0+BN1+o6iLdgF17pm xneZcFH8HF2Nf6v+W0nK/nMA0+MlBDWs5WhkDuPtk196DgHcQWZj6MkoXZvD95RJZd gmqJsFuF1Wl8hpVkZJl6oUcA8/gGg6VRHSOEzEifgHYEaMkHxWgeTnoN2wxaj37/K+ 88/97uiA8k3oDdw+QelNaVKw94Q2SUkxBWOLe9amJHhY5tOhnj1F948mCtNyGKmrMC pUinrv1Rsj+rP8fFFUdl3q32UintvGzl5rWLnjHZFY57FAHy4AiXyY10JkNhIoLikA xiScfTC5ZJeew== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 985E5C3DA42; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 10 Jul 2024 16:37:19 +0800 Subject: [PATCH v2 1/5] drm/mediatek: Support "None" blending in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240710-alpha-blending-v2-1-d4b505e6980a@mediatek.com> References: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> In-Reply-To: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , CK Hu , Hsiao Chien Sung X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720600641; l=1452; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=XPDvZ7xzyMMnOIwBspXj+lmld62ksCxAgrZn9GTIqIg=; b=GqcT87r4rRyr78YQwa4jrGqrbCdQkmHOav67BxTW5YqCT+5auldhvgktksMw2qCOf9cwLvSYQ nDSQsai+RpUB63G9x2WlWi9G7wZnlBUt3Yii8x5RGVzu7tZkp1ItpQT X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "None" alpha blending mode on MediaTek's chips. Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 9d6d9fd8342e..add671c38613 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -434,6 +434,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int fmt =3D pending->format; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; + unsigned int blend_mode =3D state->base.pixel_blend_mode; unsigned int ignore_pixel_alpha =3D 0; unsigned int con; bool is_afbc =3D pending->modifier !=3D DRM_FORMAT_MOD_LINEAR; @@ -463,7 +464,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, * For RGB888 related formats, whether CONST_BLD is enabled or not won't * affect the result. Therefore we use !has_alpha as the condition. */ - if (state->base.fb && !state->base.fb->format->has_alpha) + if ((state->base.fb && !state->base.fb->format->has_alpha) || + blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) ignore_pixel_alpha =3D OVL_CONST_BLEND; =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { --=20 2.43.0 From nobody Thu Sep 19 23:10:02 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2638D13D509 for ; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; cv=none; b=YIq6t5zATl2+1LPaaB7Rdph11mdkpI41KP39CmbgmJCwpi4lDfsI12d1BNANrqiNPgTPxPH9XqefuCFWnyJhsfN3cbdYMy3E/poS5AF+q1e8Jl/HL7CTNRGM+JUEPe6yfeanajVsAhJm13Ucxd6+lr91S4z/xUjVIe/GA0huOZs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; c=relaxed/simple; bh=mpbbUI/mfwuOOro+o5eOZMLj6A6beyQDhQ6pgkpGycU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ois4OBtZuJRDVzNEC03PtRZfJFlXnhi5Tw3ZTzpn7CQDoPNwPko5b8Accg5FDvOrgnnJCO5Qkj3KSVs+7ob4eiSG62KzjZPIpS02UHsQRuyCoatBlaVAqaueYYJ/baoKe3qWiZ2EuKYPwJbfTufyHsVqJtynQQB52YrJ9azr194= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WyproQ6O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WyproQ6O" Received: by smtp.kernel.org (Postfix) with ESMTPS id C8879C4AF0C; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720600642; bh=mpbbUI/mfwuOOro+o5eOZMLj6A6beyQDhQ6pgkpGycU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WyproQ6Ok09KxPh5i3X68h/IMVMV8hpu+9K1W5PGqCr+8OTwIi/0KCWkzy4qT5VuY LOnyBKb03nTmqiqmCUXNAclGyhySdoc1gLhlaW1R/IeshrDlPzMjvCTn8A+JCeLL/N 06hI6jpFoJjVp9II+rMww+Yq0XG61MT7IaFeG6yPkNVmwFWxGj0SW49DgTP3wk7AcM A2AwU2entnR/fdUPsegQOQI4NTQ68PQfLzSu/3mUKqLt42XSNIieHxTnEYXydPMbFp x1i0lo0Ubw7kBF4SnGuP+WFOe6mMhKco50DD6D3y+LjbHMfGbTl2VZ3rmVzLa1boRM xON0EgFD0BH8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9BDFC3DA45; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 10 Jul 2024 16:37:20 +0800 Subject: [PATCH v2 2/5] drm/mediatek: Support "None" blending in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240710-alpha-blending-v2-2-d4b505e6980a@mediatek.com> References: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> In-Reply-To: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , Hsiao Chien Sung X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720600641; l=1135; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=V+WmuBOlE61kgcB5A/JpymRNWhSW2cZJELqH7p6yZBM=; b=qo2kqnA8BYODr1XXhQEwuQy1ZySuB5FV/+zsYdB9VQTWywlOfLdLbbFntw8gDVjlJfaZGWEuT qNjVJikekxxCiDFFrN/P9CS7YhwuSJmQj8ZUIjGXMcDRwEN5LkLHP9I X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "None" alpha blending mode on MediaTek's chips. Change-Id: I9455c367bb74b75461935ecf4a3eb8e429f6e95e Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 9dfd13d32dfa..80ccdad3741b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ =20 +#include #include #include #include @@ -175,7 +176,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, alpha_con |=3D state->base.alpha & MIXER_ALPHA; } =20 - if (state->base.fb && !state->base.fb->format->has_alpha) { + if ((state->base.fb && !state->base.fb->format->has_alpha) || + state->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) { /* * Mixer doesn't support CONST_BLD mode, * use a trick to make the output equivalent --=20 2.43.0 From nobody Thu Sep 19 23:10:02 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E6FA143736 for ; Wed, 10 Jul 2024 08:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; cv=none; b=U/0x1VeOkfGUIvr1l7T9SSzhcGb0lCRdrQEPh+v1aHu4YD2mpQgOQLC5TRCpihomgr7M2Hj3PCmQ2hBIBiGiGrkaWMJsvwOehC3fVQ+D/Rq2q3IXUUTyYQPckTxgVqrnPE7KwsSDzLXpffmllpfbXlU/yJVhGrlPb3m4TDabwzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; c=relaxed/simple; bh=Z3rw5iK5CWgQLQ9VFjjvq460MP3tcbVilCNqTAWvdUE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r3503ACDxqObJsLPEYSn+ywY3cHHTBls/OzEiy7h8wO0PFr3MR8GoIbtLaTiD6ooTY+rg+nHx+aYYw4GSklfg9y74JdD633Co2LRgLc9sZDvn/TxrktJd//fmBER1cMRgwtr5FZUjLKhyrLRXHFH7+ZEyHUv3JbvZpulCMq1e4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tBg49rT9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tBg49rT9" Received: by smtp.kernel.org (Postfix) with ESMTPS id E33E2C4AF12; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720600643; bh=Z3rw5iK5CWgQLQ9VFjjvq460MP3tcbVilCNqTAWvdUE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tBg49rT9wjyCQoDopjon0DoadTFiBbwVNyzByBtTHZ/4NP6C/IPDJTUakKWt2Cvdo RYWXncPCP6x7NxfLfsOV1Y1nw9toOu3eXSdd6e6Pw0iSetpqOixvtOyp81IjZwmKFW AWiorX5t3IEK8NrshManYH6MlxvTy1NwBCTce7LY8UKLtR+aY5XSHk7jcxjF2SJYsK hTTxGM24/xihsMo8HlwmHAUoj67Z1mrz8cMhYC78cFmS3VmchRHI7GS/QkiHMn8PcT n3YK1MQkHx5PlaKLlxwscWvl7WNh1d6uiBdkvtrcqaas6GAB8P6oIjEdyDsSq3pkUy 3tp91SO2j/KvA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEB17C3DA49; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 10 Jul 2024 16:37:21 +0800 Subject: [PATCH v2 3/5] drm/mediatek: Support "Pre-multiplied" blending in OVL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240710-alpha-blending-v2-3-d4b505e6980a@mediatek.com> References: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> In-Reply-To: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , Hsiao Chien Sung , CK Hu X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720600641; l=3842; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=HXrXvrv6JMwYLM8mVe79fCqiqkK/QRt/Mduzl1YEBDY=; b=T4pYx2Y8esdJdrrjwQ1NQGOSa8SutRFuD27HTQQvMXzU3wkKkH7UU8aZY8w7G75fai03eGFIm LduvDnIGk29BnelnAM2vIspAkx8jznqcwf/W2BfAQX5iGAerr/+iEb2 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "Pre-multiplied" alpha blending mode on in OVL. Before this patch, only the "coverage" mode is supported. Signed-off-by: Hsiao Chien Sung Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++----= --- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index add671c38613..89b439dcf3a6 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -56,8 +56,12 @@ #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) =20 +#define OVL_CON_CLRFMT_MAN BIT(23) #define OVL_CON_BYTE_SWAP BIT(24) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) + +/* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ +#define OVL_CON_RGB_SWAP BIT(25) + #define OVL_CON_CLRFMT_RGB (1 << 12) #define OVL_CON_CLRFMT_ARGB8888 (2 << 12) #define OVL_CON_CLRFMT_RGBA8888 (3 << 12) @@ -65,6 +69,11 @@ #define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) #define OVL_CON_CLRFMT_UYVY (4 << 12) #define OVL_CON_CLRFMT_YUYV (5 << 12) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN) +#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_S= WAP) +#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_= SWAP) +#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_= SWAP) #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ @@ -377,7 +386,8 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int= idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt) +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, + unsigned int blend_mode) { /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" * is defined in mediatek HW data sheet. @@ -398,22 +408,30 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_o= vl *ovl, unsigned int fmt) case DRM_FORMAT_RGBA8888: case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: - return OVL_CON_CLRFMT_RGBA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_RGBA8888 : + OVL_CON_CLRFMT_PRGBA8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - return OVL_CON_CLRFMT_BGRA8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_BGRA8888 : + OVL_CON_CLRFMT_PBGRA8888; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - return OVL_CON_CLRFMT_ARGB8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ARGB8888 : + OVL_CON_CLRFMT_PARGB8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - return OVL_CON_CLRFMT_ABGR8888; + return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? + OVL_CON_CLRFMT_ABGR8888 : + OVL_CON_CLRFMT_PABGR8888; case DRM_FORMAT_UYVY: return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; case DRM_FORMAT_YUYV: @@ -453,7 +471,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt); + con =3D ovl_fmt_convert(ovl, fmt, blend_mode); if (state->base.fb) { con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; --=20 2.43.0 From nobody Thu Sep 19 23:10:02 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DA1413E41A for ; Wed, 10 Jul 2024 08:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; cv=none; b=stHKMv7gMahHeqee4Kfu0ZJDPLterKbk7W3KTWByLAiVntuS+tHrYfAIXFcpnv6xUUpQJn3IP8QNO+ECG8Fgwd2rxoR5kBjMQKjJXc2gkZig31Bs6fF2L2llDsuiLUooCaqKL7fsEFjt+JQ1fYdHwtBLu/aRyLsgY/XTenzSxww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720600643; c=relaxed/simple; bh=FrXpXFM8hU8nJEtAJsJHGV8jQY/M8JZ5BXMOtazVLvA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pNiT9d1alzX2lJ3+2j4tdC1fZ++dyXXolBPWconIPETkteNGj0UIsmukzdErm2B0tYtj0TakczkoZfdQDcXBb/QsEy1yLrM9EYqTosuzLZRVyWgL1oHn3/yl4rE2S+4s8QlLSsSlxnll+jBNPRJGTFSJCTdKaZuYlCivpFcy+v0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kEF+QMeT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kEF+QMeT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1F542C4AF07; Wed, 10 Jul 2024 08:37:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720600643; bh=FrXpXFM8hU8nJEtAJsJHGV8jQY/M8JZ5BXMOtazVLvA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kEF+QMeT8WtCEAnfkrRKO2Nax7gTdNBjg/szekpejoYED4qnlC8B4XmgexsYhHPY1 clDVN8dbhFk1v9F7B5Yq5R3yTAj5VuHidO6RVnL9Aisn5f1BW2UGjhmZbUNPMePdIH wcwapVY829+IAoxKs6UgS6bEp6213hCdeFLzhjk8e799F/ArqrSGROnlvIW7gn799b cGURoTW8cXDSvgrMdugmtUVtaVGs5Wcn9+wRGhDunGN91EirS49ttYArFxUCYREdOr w89lAHUDMorBob3hiArr5Njg6rUbugjLk288mzffLKz92ypbmSMA+WYQXdKyPWR0kb XhoeWI5B7LL7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0027BC3DA45; Wed, 10 Jul 2024 08:37:22 +0000 (UTC) From: Hsiao Chien Sung via B4 Relay Date: Wed, 10 Jul 2024 16:37:22 +0800 Subject: [PATCH v2 4/5] drm/mediatek: Support "Pre-multiplied" blending in Mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240710-alpha-blending-v2-4-d4b505e6980a@mediatek.com> References: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> In-Reply-To: <20240710-alpha-blending-v2-0-d4b505e6980a@mediatek.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hsiao Chien Sung , Hsiao Chien Sung X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720600641; l=2211; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=L3aSZMNI/5e4YMPf4nqEmkejhrP0vtCut0YLE0pQ+qs=; b=ar4ZvKNsZZFYYYRhlTblHJLqdhIfL3KbfOwFhbVhs5KkRPAiTvE1rR+Str+/zCYpkhyaY5p02 Tl997s/5QS1DTNJ2iL/1yJNE2W14+DA0gH+3bn6P9S3mTbkZrknCaQD X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "Pre-multiplied" alpha blending mode in Mixer. Before this patch, only the coverage mode is supported. To replace the default setting that is set in mtk_ethdr_config(), we change mtk_ddp_write_mask() to mtk_ddp_write(), and this change will also reset the NON_PREMULTI_SOURCE bit that was assigned in mtk_ethdr_config(). Therefore, we must still set NON_PREMULTI_SOURCE bit if the blend mode is not DRM_MODE_BLEND_PREMULTI. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index 80ccdad3741b..d1d9cf8b10e1 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -36,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -176,6 +177,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsign= ed int idx, alpha_con |=3D state->base.alpha & MIXER_ALPHA; } =20 + if (state->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) + alpha_con |=3D PREMULTI_SOURCE; + else + alpha_con |=3D NON_PREMULTI_SOURCE; + if ((state->base.fb && !state->base.fb->format->has_alpha) || state->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) { /* @@ -193,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigne= d int idx, mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq= _base, mixer->regs, MIX_L_SRC_SIZE(idx)); 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a=ed25519-sha256; t=1720600641; l=2210; i=shawn.sung@mediatek.com; s=20240710; h=from:subject:message-id; bh=NXMVY+5up48Xsv5+9pKY3kYmUYHXnlx5rItB6cJy0f4=; b=luIxk/kE+qqI+aQA1FJilq+yDoY7Bb9PvQdmMn20B4ySUDMDIoplbBxsaHZKR5Pp2S05lfRwS qR0SBaZHIXdA/aRiAIs4izDZpsyLzLT19+0Ds/EmZSnDgciLB4LK1S3 X-Developer-Key: i=shawn.sung@mediatek.com; a=ed25519; pk=VRlGZ3diQkQtpDd8fCL9/mx+TpZStm08pg8UPaG1NGc= X-Endpoint-Received: by B4 Relay for shawn.sung@mediatek.com/20240710 with auth_id=184 X-Original-From: Hsiao Chien Sung Reply-To: shawn.sung@mediatek.com From: Hsiao Chien Sung Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by adding correct blend mode property when the planes init. Before this patch, only the "Coverage" mode (default) is supported. For more information, there are three pixel blend modes in DRM driver: "None", "Pre-multiplied", and "Coverage". To understand the difference between these modes, let's take a look at the following two approaches to do alpha blending: 1. Straight: dst.RGB =3D src.RGB * src.A + dst.RGB * (1 - src.A) This is straightforward and easy to understand, when the source layer is compositing with the destination layer, it's alpha will affect the result. This is also known as "post-multiplied", or "Coverage" mode. 2. Pre-multiplied: dst.RGB =3D src.RGB + dst.RGB * (1 - src.A) Since the source RGB have already multiplied its alpha, only destination RGB need to multiply it. This is the "Pre-multiplied" mode in DRM. For the "None" blend mode in DRM, it means the pixel alpha is ignored when compositing the layers, only the constant alpha for the composited layer will take effects. Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_plane.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 1723d4333f37..5bf757a3ef20 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -346,6 +346,17 @@ int mtk_plane_init(struct drm_device *dev, struct drm_= plane *plane, DRM_INFO("Create rotation property failed\n"); } =20 + err =3D drm_plane_create_alpha_property(plane); + if (err) + DRM_ERROR("failed to create property: alpha\n"); + + err =3D drm_plane_create_blend_mode_property(plane, + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE)); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 return 0; --=20 2.43.0