From nobody Sun Feb 8 04:18:04 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 164001A0B0A for ; Tue, 9 Jul 2024 16:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542042; cv=none; b=CpIn/Hp7FpXl5AFYDynqRAzB1Obvq/wvf+bvc5gFPziyM6EXM8z+LJYcZgp7m8ZfT1g4tNdUEAS0ymXtIcnuoLco8R3rTLkArzGlkfWN8bJ8NMEEXLNH1Z8NtL6bcqB+31X6SBf8jMoc9y4eD64/ymIpzQFUjd/DRckBeWIn4GE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542042; c=relaxed/simple; bh=8NOqBbsSvFK4yjK2xkto5fV0gXtGYQKFlvHQg5hw0Mk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nwDgrc50jGXkFX5vHhsEiWuLHw/v23PjrizNagezEf9Fq5e+dvR0xVKVkXklEb63jQiGcMEgpOmcNqY0GzPsGyf76Mrgxk8t34WrkeLk3wQ3bQhvT65vZxIGuogqG8gpbEh1WrbpMzTSkP9Pfk1ABTaqX29cc8sGsSnRSXT3Wzo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=K8H9VEz1; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="K8H9VEz1" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-367963ea053so4460450f8f.2 for ; Tue, 09 Jul 2024 09:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720542038; x=1721146838; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6OcFxIacVPCI9fltIqvuSe/0ZyBydbNragsMq+b3rJs=; b=K8H9VEz1b3/h4G5CInOt6zPJk/kZVnfHAbzzA/0uc+bgd/IzLRYddvamulTVze2NCV 44pwjioDtq6TSP1+rpMbsOZIqJK+pr9MpoR6VuxBqRCCicHQKBWuKvQabZDF9EwOgy0P tpDQ6e9Bvz+wrVI5f/pdMj58jmyn6eZijG7oJOWgJvyQvCRo7Mq2hFnfb2AUCASB431m paiMJdWCvfGvLCdXH4Gq/gn4BYKdY5K6WHguApYwrUtNoH2DtdFXNJCBx7nyyHK4YdOj kXGodousaAyiqSga77k7F32bTsgpvSA9Ew61NL2K3moZ1dvaz7sr0P4aCFG2BT9lz9QM t+Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720542038; x=1721146838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6OcFxIacVPCI9fltIqvuSe/0ZyBydbNragsMq+b3rJs=; b=M2qpyilco6zFdmwc8oRuo1jzcli6/bc2d3MEk/+hLO3t47Rm+CM6Mn8268x2q+0j8b y1H7Yxm0xc6dCbJR1MoPM4YTrLd2TgWUqgHmHF8Z/6Gx/4jdxfTxdjmzucLBJSv51cld vfHywEdgY7kJg4XFmEnR8T1L0v1uiIQHiR6KfNelki6jMus0k1ptbaAHe3sQLAMFBLuw cMxvIWf30z4aIhxaZRyBUL+ZbdBPiM8p9OhDvZl/5F/hzcMuU69nF1/LlYhLs56KVgFq 1wlSrtPx129KOWTo7OMjKot4i+TiHvouPsZcGusgYJZd1ghOzG4UvYMl3e/9SDMlZetP Ra8Q== X-Forwarded-Encrypted: i=1; AJvYcCU85IAa8FSlZry5+PFD6Jd2vomIBl5GqtEPYDd6sLdHI+M4pYDcgUqI3w0+7uf33kARLJnpIkfnJEpC546g0nRqZHmA34rS0PpvQn2z X-Gm-Message-State: AOJu0YwcgldxcSBSMEduKIANn53wvLVs9gxD0zmhQpEDGhoz/1aWX6oH 6tnicVbtyor0wa3qXaccBBZyfHLSXUxfi9MdJfD3Z2CVycM/ruWnZPl6rhs0Bt0= X-Google-Smtp-Source: AGHT+IH9V/uONRD7mQD8SzcFcM47lU1aVaraBEMS3XW7Z4JsftrMZbO+szMbIdNTZXQmBucQ7UBjhg== X-Received: by 2002:adf:e54b:0:b0:367:9754:8107 with SMTP id ffacd0b85a97d-367ceadc90bmr2886800f8f.62.1720542038248; Tue, 09 Jul 2024 09:20:38 -0700 (PDT) Received: from rayyan-pc.broadband ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde7e07fsm2966955f8f.17.2024.07.09.09.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 09:20:37 -0700 (PDT) From: Rayyan Ansari To: devicetree@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH 1/4] dt-bindings: pinctrl: qcom,apq8064-pinctrl: convert to dtschema Date: Tue, 9 Jul 2024 17:17:53 +0100 Message-ID: <20240709162009.5166-2-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709162009.5166-1-rayyan.ansari@linaro.org> References: <20240709162009.5166-1-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Qualcomm APQ8064 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,apq8064-pinctrl.txt | 95 --------------- .../pinctrl/qcom,apq8064-pinctrl.yaml | 110 ++++++++++++++++++ 2 files changed, 110 insertions(+), 95 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8064-= pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8064-= pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl= .txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt deleted file mode 100644 index 4e90ddd77784..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt +++ /dev/null @@ -1,95 +0,0 @@ -Qualcomm APQ8064 TLMM block - -Required properties: -- compatible: "qcom,apq8064-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of t= he -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary num= ber of -subnodes. Each of these subnodes represents some desired configuration for= a -pin, a group, or a list of pins or groups. This configuration can include = the -mux function to select on those pin(s)/group(s), and various pin configura= tion -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerat= ed -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are va= lid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strengt= h, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for pins are: - gpio0-gpio89 - -Valid values for function are: - cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a, - gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4, - gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, - gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, - gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, - riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_ho= ld - -Example: - - msmgpio: pinctrl@800000 { - compatible =3D "qcom,apq8064-pinctrl"; - reg =3D <0x800000 0x4000>; - - gpio-controller; - #gpio-cells =3D <2>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D <0 16 0x4>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&gsbi5_uart_default>; - gpio-ranges =3D <&msmgpio 0 0 90>; - - gsbi5_uart_default: gsbi5_uart_default { - mux { - pins =3D "gpio51", "gpio52"; - function =3D "gsbi5"; - }; - - tx { - pins =3D "gpio51"; - drive-strength =3D <4>; - bias-disable; - }; - - rx { - pins =3D "gpio52"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml new file mode 100644 index 000000000000..f251dcd4bb7f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. APQ8064 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,apq8064-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-apq8064-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-apq8064-tlmm-state" + additionalProperties: false + +$defs: + qcom-apq8064-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-8][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, s= dc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, + gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b, + gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c, + gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, + gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, + gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3, + gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan, + sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, + ps_hold ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@800000 { + compatible =3D "qcom,apq8064-pinctrl"; + reg =3D <0x800000 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 90>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + uart-state { + rx-pins { + pins =3D "gpio52"; + function =3D "gsbi5"; + bias-pull-up; + }; + + tx-pins { + pins =3D "gpio51"; + function =3D "gsbi5"; + bias-disable; + }; + }; + }; --=20 2.45.2 From nobody Sun Feb 8 04:18:04 2026 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B420F1A2FCD for ; Tue, 9 Jul 2024 16:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542048; cv=none; b=gFvgUceD9jWaOyMpIiJvK+/YHNwqkLjg4p6ZllaA5gVHBYoZNqrOZrCtRhRXL5qMbkghzxePxp25hAaOsAxux3PH8RnIwgoI2GAJ2QmMj6n5tCf0ww2l4obr/KqPIoVo2mcXBe3NQyRH1cCQ9F0QRTBf2v3hbVd5FCQoa8NkjUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542048; c=relaxed/simple; bh=I+e/Ru/F7i8s3g90eMaGWGwVgP3LUnUVxX5/u8fkRVE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y4JrNov3aQdxGt72r7i7f1dFbeI0cFvJpt1s49INyL3oUrPbIXFHGdNYNwUrzGz8hH91snN2StjMLJUMicMWEZNVly/L2z94Q6DEW+DK3lSyAkW+t4VBqMKr6QnRpj6PeRHmxe/Q5Qt0X1OwT8b0XJtlICdsC6hqNNBg/ASm47U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fWjla2uf; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fWjla2uf" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-52e98087e32so5922670e87.2 for ; Tue, 09 Jul 2024 09:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720542045; x=1721146845; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N0znxVwwjji/DUtWTLARmbZTFvr2yZL9kSRXuxBRwMw=; b=fWjla2ufZu3a5Gm6xIE89vs0qzrwL2iAGtlnsYfc2JGZRg739GK7YWdVpwFi6NWinz 5X/GRwkEalkzqw26LaFNTp2BWfnJcR6BRJSMG7g7H5USMIjTdY0hpoU0/Q1+0ifv237/ LZYHDCvB0J/iqZMHSXnTNDCARBrqzv1qa4Bk8nRSnoqI3/qzuKKaiHKTgCYj1wurXKbf xnrP8AOZdkKTckwZmnde8yIDxw/DdLyvYZEoko994o+2hXgpxEQFQDxEehk0xLNaWMP6 zAP/7A62QwuBcpbMhvvAXKti3CpKBjBzKdk9kUDZXZTdHaQAh9wbH6AU9H+QaMaLp5ng qj/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720542045; x=1721146845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N0znxVwwjji/DUtWTLARmbZTFvr2yZL9kSRXuxBRwMw=; b=HsSplxsCEkxyM02uF8tsOIWPqznyz/4ISDBknkAFedI3jID9tsDEIY8y/tBa+IOZrm hHE0UYR+4b3OsCcf138a7n++QunjbjfZpp3jzKR6/MMLWR/w3Jppmbxb0otpd0ol9mqL Xm9L5HDqYZfy8lH1DW0y++tZUbfQ7g3b012j5r4JzB8/AicdbMsYsb3Eib99iJLWb7ha wQVT7QLIU2odNoLxXbwutjhm3NK+MVMUdwMaTFUxTmIdBtqkFCq8oMvLXW4T1AyqHOw4 5SfxYy13p+wDRIDARUu1JIiDZLrlMViduKrJz+lHeCoe6a72EkU/Mvwc9OePJ0SfY0xG nlHw== X-Forwarded-Encrypted: i=1; AJvYcCVzVLY6MN/QBqAjwAtRKCsru/uvl/neowWKaJXf0Paxx2bunsFSo5K7GC95o/x0IF+4yoKbooaXuWLv1GNT0x31AhJCHo9SkVnez+qx X-Gm-Message-State: AOJu0YxscI5BSmKN+gwMVcVO5fMepPW8wEJTe7n8q9lUjLPbn4dM5FQk 57tqJdmzX+6sk+F2x6gxcw90+lSHH1dSlbstdgpqe6P4vpAlCZ6vSgEiplRkFSU= X-Google-Smtp-Source: AGHT+IGEHZyHATXkbM3yaENJpeHbND/G7r/St/XcvgZYZHmV6fJy0I7tDkNlNpGUDeCi6fZCEeDukA== X-Received: by 2002:a05:6512:78c:b0:52c:c5c4:43d4 with SMTP id 2adb3069b0e04-52eb99caf68mr1644174e87.53.1720542044950; Tue, 09 Jul 2024 09:20:44 -0700 (PDT) Received: from rayyan-pc.broadband ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde7e07fsm2966955f8f.17.2024.07.09.09.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 09:20:44 -0700 (PDT) From: Rayyan Ansari To: devicetree@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH 2/4] dt-bindings: pinctrl: qcom,ipq8064-pinctrl: convert to dtschema Date: Tue, 9 Jul 2024 17:17:54 +0100 Message-ID: <20240709162009.5166-3-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709162009.5166-1-rayyan.ansari@linaro.org> References: <20240709162009.5166-1-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Qualcomm IPQ8064 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,ipq8064-pinctrl.txt | 101 ---------------- .../pinctrl/qcom,ipq8064-pinctrl.yaml | 108 ++++++++++++++++++ 2 files changed, 108 insertions(+), 101 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-= pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-= pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl= .txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt deleted file mode 100644 index a7aaaa7db83b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt +++ /dev/null @@ -1,101 +0,0 @@ -Qualcomm IPQ8064 TLMM block - -Required properties: -- compatible: "qcom,ipq8064-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of t= he -phrase "pin configuration node". - -Qualcomm's pin configuration nodes act as a container for an arbitrary num= ber of -subnodes. Each of these subnodes represents some desired configuration for= a -pin, a group, or a list of pins or groups. This configuration can include = the -mux function to select on those pin(s)/group(s), and various pin configura= tion -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerat= ed -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are va= lid -to specify in a pin configuration subnode: - - pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strengt= h, - output-low, output-high. - -Non-empty subnodes must specify the 'pins' property. - -Valid values for qcom,pins are: - gpio0-gpio68 - Supports mux, bias, and drive-strength - - sdc3_clk, sdc3_cmd, sdc3_data - Supports bias and drive-strength - - -Valid values for function are: - mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, - gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1, - spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, - pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt, - pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren, - pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n, - pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold - -Example: - - pinmux: pinctrl@800000 { - compatible =3D "qcom,ipq8064-pinctrl"; - reg =3D <0x800000 0x4000>; - - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&pinmux 0 0 69>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D <0 32 0x4>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&gsbi5_uart_default>; - - gsbi5_uart_default: gsbi5_uart_default { - mux { - pins =3D "gpio18", "gpio19"; - function =3D "gsbi5"; - }; - - tx { - pins =3D "gpio18"; - drive-strength =3D <4>; - bias-disable; - }; - - rx { - pins =3D "gpio19"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml new file mode 100644 index 000000000000..58f11e1bdd4f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ8064 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq8064-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq8064-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq8064-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq8064-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$" + - enum: [ sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2= , gsbi4, gsbi5, + gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7,= nss_spi, sdc1, + spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rg= mii2, sata, + pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_= pwrflt, + pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie= 2_pwren, + pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3= _pwren_n, + pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@800000 { + compatible =3D "qcom,ipq8064-pinctrl"; + reg =3D <0x00800000 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 69>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + uart-state { + rx-pins { + pins =3D "gpio19"; + function =3D "gsbi5"; + bias-pull-up; + }; + + tx-pins { + pins =3D "gpio18"; + function =3D "gsbi5"; + bias-disable; + }; + }; + }; --=20 2.45.2 From nobody Sun Feb 8 04:18:04 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B99F1ABC4A for ; Tue, 9 Jul 2024 16:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542055; cv=none; b=G3YFnBdHMmzYg9CG5EoKyeIO20eXl7lDMYiwXC2BkMluq8BHPxwtNlL5nT4rKI0PSRrkNjSVS7o3WG0U2/mObdRjjY2sc6M4t1fb9bn6kY69AYdoGCBE1nyINAJ3zrH9voi5n/voKynL4Byx+d2qaB+9Mzsi+cv2wP9v8TErgLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542055; c=relaxed/simple; bh=15/G0KHqA0dKur8q9uAiEUuJzQ4VCnWfgrKNlUgEpsU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TsnInSEbdTV7Nr+2QGJBTqqY8UyURIO9I3vw0BBJphFGPm2qTPx00CbxshlJvcpKGxAXzNUb9RNzt3mgbFl8i0+flEPVVMv0dffnfR6GDw6sYTz618cSsU2SCUGlkfhjrI0u3FLalL2c8Gj2IeFWFWUEOMUQX4AfW8bVpmDirGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SCcHm8LD; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SCcHm8LD" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-36798779d75so4703853f8f.3 for ; Tue, 09 Jul 2024 09:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720542052; x=1721146852; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hMw3Csc91xG1Dn/+t3HCdPJHIoD7h/vcI/ofAzBjPNA=; b=SCcHm8LDHvWkys6gqbLWNlSFyT19UrsfdvzG3hW2mlYtufwbdsFj815jQgPHajFJ0u +PjxPPH/+a4Mwd7FIx08BunxzkwqBLgri4Xm/s/EBJNU7O1u83h1Ky7Cg48gwBol3rEK 1u0ixegOf9kEX1oP9mp0LzAhjYScpOn11/pwzB41SD7vT/J6FPSYm/4FRgzA0+e4fhzR vO2eCwmiWkt4MiYaxf2CzSjts0KS2ymL+HFZxbqD3VsRitX2AkdzX+dP+zz6HXxAcpFp Lbd2rRsNrARNqeOFONJJCJuiN+/+0i3EZuTMa/59i9XWuIQrO8fivXzYiCuL5HyLJRzc pDuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720542052; x=1721146852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hMw3Csc91xG1Dn/+t3HCdPJHIoD7h/vcI/ofAzBjPNA=; b=jOPIBzM7DWTUuvRLuS917qZg4BkqWEN9O2/JzC/IR2lddWItOgAYZRPMarnlJJKmJ7 naViHkWqNrBHynoowO0O8klJH7K3e3xG1GTIkEDyMRIKx7wTbmugdxgT8bKkIO3l1fqv wFmXTLosLGefb9+bXmptFTt1R81VeSMITbYRn7s4EZ4xfxGeDJSSkJrGC8YmrKfCinev yDw+PdEnvvWaIqQNZHBxEGJrZ4IA6O3tnOO130L1w2aPf7omvXfVCN98gL2CCDrsVMzI uf2ZKMhendJafeEkLN2la0uAVvx1uKenCe/b+kIqlcXhV5yOs6Mt4IZ2chalyvQxfK/Z c9Lg== X-Forwarded-Encrypted: i=1; AJvYcCXfv9Fya3Da1JZ1DFyJKep6zqvUxRSx+njl3B7EV+1S6QQ+Ob/qV5T9KhE6wmwx8l3zDtzkYo5cm80gylesBoY8tSCGSp0QemXauDLi X-Gm-Message-State: AOJu0YyPZE521E2ZtDw/4hdpr9Xu4TL9R6Zrblgo2YWU0rk7j7wsOkpZ gPUX91SQL1XXeHnXY+oZoCRD9ovg4TbsWFSVCGYVqBRR25/RLJMIHyaRvNop3jE= X-Google-Smtp-Source: AGHT+IFe6PkqhiCDDJSXx6ob8a+E7JGUWgUrvxr1A9IgPNb3EmRBtZ3lIkQmLc8Rpz+Jj7CtmBiJDw== X-Received: by 2002:a5d:64c4:0:b0:366:efbd:8aa3 with SMTP id ffacd0b85a97d-367cea46767mr3526398f8f.2.1720542051822; Tue, 09 Jul 2024 09:20:51 -0700 (PDT) Received: from rayyan-pc.broadband ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde7e07fsm2966955f8f.17.2024.07.09.09.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 09:20:51 -0700 (PDT) From: Rayyan Ansari To: devicetree@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH 3/4] dt-bindings: pinctrl: qcom,ipq4019-pinctrl: convert to dtschema Date: Tue, 9 Jul 2024 17:17:55 +0100 Message-ID: <20240709162009.5166-4-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709162009.5166-1-rayyan.ansari@linaro.org> References: <20240709162009.5166-1-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Qualcomm IPQ4019 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,ipq4019-pinctrl.txt | 85 --------------- .../pinctrl/qcom,ipq4019-pinctrl.yaml | 102 ++++++++++++++++++ 2 files changed, 102 insertions(+), 85 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-= pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-= pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl= .txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt deleted file mode 100644 index 97858a7c07a2..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt +++ /dev/null @@ -1,85 +0,0 @@ -Qualcomm Atheros IPQ4019 TLMM block - -This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019 -platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities. - -Required properties: -- compatible: "qcom,ipq4019-pinctrl" -- reg: Should be the base address and length of the TLMM block. -- interrupts: Should be the parent IRQ of the TLMM block. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be two. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. - The first cell is the gpio pin number and the - second cell is used for optional parameters. -- gpio-ranges: see ../gpio/gpio.txt - -Optional properties: - -- gpio-reserved-ranges: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of t= he -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for= a -pin, a group, or a list of pins or groups. This configuration can include = the -mux function to select on those pin(s)/group(s), and various pin configura= tion -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerat= ed -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are va= lid -to specify in a pin configuration subnode: - pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-dr= ain, - drive-strength. - -Non-empty subnodes must specify the 'pins' property. -Note that not all properties are valid for all pins. - - -Valid values for qcom,pins are: - gpio0-gpio99 - Supports mux, bias and drive-strength - -Valid values for qcom,function are: -aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0, -blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i= 2s_tx, -jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, l= ed11, -mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, -smart2, smart3, tm, wifi0, wifi1 - -Example: - - tlmm: pinctrl@1000000 { - compatible =3D "qcom,ipq4019-pinctrl"; - reg =3D <0x1000000 0x300000>; - - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&tlmm 0 0 100>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D <0 208 0>; - - serial_pins: serial_pinmux { - mux { - pins =3D "gpio60", "gpio61"; - function =3D "blsp_uart0"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml new file mode 100644 index 000000000000..ebf74e48ec5b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ4019 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq4019-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq4019-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq4019-tlmm-state" + additionalProperties: false + + "-hog(-[0-9]+)?$": + required: + - gpio-hog + +$defs: + qcom-ipq4019-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, + blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio, + i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx, + jtag, led0, led1, led2, led3, led4, led5, led6, led7, + led8, led9, led10, led11, mdc, mdio, pcie, pmu, + prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, + smart2, smart3, tm, wifi0, wifi1 ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@1000000 { + compatible =3D "qcom,ipq4019-pinctrl"; + reg =3D <0x01000000 0x300000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 100>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + uart-state { + pins =3D "gpio16", "gpio17"; + function =3D "blsp_uart0"; + bias-disable; + }; + }; --=20 2.45.2 From nobody Sun Feb 8 04:18:04 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4196F1AC44A for ; Tue, 9 Jul 2024 16:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542062; cv=none; b=pbjAMz9Z4FcwZsxMFJMoN6PPByc6N35s4bKcvC9VI9fA3KgfxomhkUZdaCDHFf5VjXpnBlv5RtwxxhsjIEwe+Yrzi3zMVtlslqPrJt7vnqUZcs+duTvVwSf8DsqveQZpsHT7u59bJs8XCAisXaLqNiCfAOpqxvnQxa5jCi5pZnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720542062; c=relaxed/simple; bh=K5IDHOGwur5M1wxz6gR+ee2Yecqq87yweHl0ice3ziY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PGNB1wzf0Rb83jnfdRQlZhooxu+cU5EPtzSFQDA1eUFojTjEpB7fYp4xm5w1P4pysgiu61QatRncypxpbno0MF6oqcjkkD294pOXxT56wTtPwV+MXeds9WH3wLZ+JFm4PT1qeRSfFvSHkOJWzEgkuf09etFaW0Np6aGXMBUOCcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WNGTmAyL; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WNGTmAyL" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-426717a2d12so7201515e9.0 for ; Tue, 09 Jul 2024 09:21:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720542059; x=1721146859; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QZURG4DQ86OmYUEBMJ73gjiu+OgC68nhtpPKYr4JjTk=; b=WNGTmAyLKztkkcKDTtXHrg7WgBuD4WP/YUklpOIiFvCa4fU9/G8rP8vwzHIOvNjrpf n95Rf9eYxSc1hexXaSZAk1xc6lMI8D9a8bQEfuDSV2FGav8DsPnr3GXYcbtejLBdn8KT hD2tMcM/KO6W0ldJJdCdp4+oaPNxxvpHfyfdQC5xx2bF/GAwn4qreBx8ruG5lbDJu4nK OUgf90nXwW5NEysCdgziu3QL2qdrKNacavmVGsvYNzY5okSm3ETAuE4VgkavF09IaMjL LalontQ1CpQCqZ5RUrn+K3WdSodnFwpdvqiq49VvMIH0K3q9x3juQ0JCpDnPZ5X9TO7N z0hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720542059; x=1721146859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QZURG4DQ86OmYUEBMJ73gjiu+OgC68nhtpPKYr4JjTk=; b=ttstOKhWLD6CJBxDZzLWLTmwvcSlafu4Ts62D2PBcPdMaAEi17xE+LOizXCmL4DgSA o7PUn4VQzHqfW4MrCYCB7+JaiPAQFoa7v6R4SFvM2Thoj8NYBuPn0mM9dTjf4WhPkI09 Nt4yUdZspJmrUPi+prCKcq+wIDIE5C35X5cxbRgDurBsvnRGK/BdzvR85uKk5msLXO6Z 7ndo0cUI7+ull4Vr1vpg6f/1ttnIcYXVPeFsYIu3VaVruY9JQzFQSQQQQztrTFQa6aoQ 859SasrFoCLZXLlf5cBkcYAGD8yvD8Hq+osFn6/p7hnStZvCjpTiQsL3lqnpIgbORr2h VhqQ== X-Forwarded-Encrypted: i=1; AJvYcCW7rApofznOeC0RZjbDqhyQgNyxrzlbIIVrI2RiYgxTBzlqHvOxHIS2Z7b2xhg3+aauCo7EcgMoH0JbjxAjnOamABAaczgIa0yAXMy9 X-Gm-Message-State: AOJu0YzejaBxagwyLLhqN2hej/6YLKRlEUQwkFRrJ3QlSXySC4muq26c P80/xpiBR0WmcRLdbIJTK4R0A9E5e+WdWJOCs3dc7Hy5iHDEEUN+9xmeSxWKtNtf6mTLZRorQPY r X-Google-Smtp-Source: AGHT+IHJe6Owzua4x6G16KkskCgOHlwfWxLCcRpIy7XL32/xCG893IE+O2YynuqUNB0HAJGA159CzA== X-Received: by 2002:a05:600c:378d:b0:426:6981:1bd with SMTP id 5b1f17b1804b1-426722d4b4emr24632085e9.5.1720542058698; Tue, 09 Jul 2024 09:20:58 -0700 (PDT) Received: from rayyan-pc.broadband ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-367cde7e07fsm2966955f8f.17.2024.07.09.09.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 09:20:58 -0700 (PDT) From: Rayyan Ansari To: devicetree@vger.kernel.org Cc: Rayyan Ansari , Bjorn Andersson , Conor Dooley , Krzysztof Kozlowski , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH 4/4] dt-bindings: pinctrl: qcom,apq8084-pinctrl: convert to dtschema Date: Tue, 9 Jul 2024 17:17:56 +0100 Message-ID: <20240709162009.5166-5-rayyan.ansari@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709162009.5166-1-rayyan.ansari@linaro.org> References: <20240709162009.5166-1-rayyan.ansari@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Qualcomm APQ8084 TLMM block bindings from text to yaml dt schema format. Signed-off-by: Rayyan Ansari Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,apq8084-pinctrl.txt | 188 ------------------ .../pinctrl/qcom,apq8084-pinctrl.yaml | 129 ++++++++++++ 2 files changed, 129 insertions(+), 188 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-= pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,apq8084-= pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl= .txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt deleted file mode 100644 index c9782397ff14..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt +++ /dev/null @@ -1,188 +0,0 @@ -Qualcomm APQ8084 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8960 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apq8084-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.tx= t for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of t= he -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for= a -pin, a group, or a list of pins or groups. This configuration can include = the -mux function to select on those pin(s)/group(s), and various pin configura= tion -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerat= ed -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are va= lid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio146, - sdc1_clk, - sdc1_cmd, - sdc1_data - sdc2_clk, - sdc2_cmd, - sdc2_data - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, - blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, - blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, - blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, - blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, - blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, - blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, - blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, - blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, - blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, - blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, - cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, - edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i - gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio, - hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic, - ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, - pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, - qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, - sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, - spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1, - tsif2, uim, uim_batt_alarm - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@fd510000 { - compatible =3D "qcom,apq8084-pinctrl"; - reg =3D <0xfd510000 0x4000>; - - gpio-controller; - #gpio-cells =3D <2>; - gpio-ranges =3D <&tlmm 0 0 147>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupts =3D <0 208 0>; - - uart2: uart2-default { - mux { - pins =3D "gpio4", "gpio5"; - function =3D "blsp_uart2"; - }; - - tx { - pins =3D "gpio4"; - drive-strength =3D <4>; - bias-disable; - }; - - rx { - pins =3D "gpio5"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml new file mode 100644 index 000000000000..38877d8b97ff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. APQ8084 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,apq8084-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-apq8084-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-apq8084-tlmm-state" + additionalProperties: false + +$defs: + qcom-apq8084-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, + blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, + blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, + blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, + blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, + blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2, + blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7, + blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11, + blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, + cci_async, cci_async_in0, cci_i2c0, cci_i2c1, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, + gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest, + hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update, + mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1, + pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, + qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, + sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, + spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, + tsif1, tsif2, uim, uim_batt_alarm ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + tlmm: pinctrl@fd510000 { + compatible =3D "qcom,apq8084-pinctrl"; + reg =3D <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 147>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + uart-state { + rx-pins { + pins =3D "gpio5"; + function =3D "blsp_uart2"; + bias-pull-up; + }; + + tx-pins { + pins =3D "gpio4"; + function =3D "blsp_uart2"; + bias-disable; + }; + }; + }; --=20 2.45.2