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[83.30.46.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a6bcc21sm66528166b.16.2024.07.09.03.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:28:37 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Neil Armstrong , Vladimir Lypak , Rajendra Nayak , Rohit Agarwal , Danila Tikhonov , Bjorn Andersson , Stephan Gerhold , Andrew Halaney , Dmitry Baryshkov , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Barnabas Czeman , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Sibi Sankar Subject: [PATCH v3 2/9] interconnect: qcom: Add MSM8976 interconnect provider driver Date: Tue, 9 Jul 2024 12:22:47 +0200 Message-ID: <20240709102728.15349-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240709102728.15349-1-a39.skl@gmail.com> References: <20240709102728.15349-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for interconnect busses found in MSM8976 based platforms. The topology consists of four NoCs that are partially controlled by a RPM processor. Signed-off-by: Adam Skladowski --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8976.c | 1440 +++++++++++++++++++++++++++ 3 files changed, 1451 insertions(+) create mode 100644 drivers/interconnect/qcom/msm8976.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 9b84cd8becef..20238d231df4 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -53,6 +53,15 @@ config INTERCONNECT_QCOM_MSM8974 This is a driver for the Qualcomm Network-on-Chip on msm8974-based platforms. =20 +config INTERCONNECT_QCOM_MSM8976 + tristate "Qualcomm MSM8976 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on msm8976-based + platforms. + config INTERCONNECT_QCOM_MSM8996 tristate "Qualcomm MSM8996 interconnect driver" depends on INTERCONNECT_QCOM diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 7a7b6a71876f..9d44ea94847a 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -9,6 +9,7 @@ qnoc-msm8916-objs :=3D msm8916.o qnoc-msm8939-objs :=3D msm8939.o qnoc-msm8953-objs :=3D msm8953.o qnoc-msm8974-objs :=3D msm8974.o +qnoc-msm8976-objs :=3D msm8976.o qnoc-msm8996-objs :=3D msm8996.o icc-osm-l3-objs :=3D osm-l3.o qnoc-qcm2290-objs :=3D qcm2290.o @@ -44,6 +45,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916= .o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) +=3D qnoc-msm8939.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) +=3D qnoc-msm8953.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974.o +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) +=3D qnoc-msm8996.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) +=3D icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290.o diff --git a/drivers/interconnect/qcom/msm8976.c b/drivers/interconnect/qco= m/msm8976.c new file mode 100644 index 000000000000..ab963def77c3 --- /dev/null +++ b/drivers/interconnect/qcom/msm8976.c @@ -0,0 +1,1440 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Based on data from msm8976-bus.dtsi in Qualcomm's msm-3.10 release: + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "icc-rpm.h" + +enum { + QNOC_MASTER_AMPSS_M0 =3D 1, + QNOC_MNOC_BIMC_MAS, + QNOC_SNOC_BIMC_MAS, + QNOC_MASTER_TCU_0, + QNOC_MASTER_USB_HS2, + QNOC_MASTER_BLSP_1, + QNOC_MASTER_USB_HS, + QNOC_MASTER_BLSP_2, + QNOC_MASTER_CRYPTO_CORE0, + QNOC_MASTER_SDCC_1, + QNOC_MASTER_SDCC_2, + QNOC_MASTER_SDCC_3, + QNOC_SNOC_PNOC_MAS, + QNOC_MASTER_LPASS_AHB, + QNOC_MASTER_SPDM, + QNOC_MASTER_DEHR, + QNOC_MASTER_XM_USB_HS1, + QNOC_MASTER_QDSS_BAM, + QNOC_BIMC_SNOC_MAS, + QNOC_MASTER_JPEG, + QNOC_MASTER_GRAPHICS_3D, + QNOC_MASTER_MDP_PORT0, + QNOC_MASTER_MDP_PORT1, + QNOC_PNOC_SNOC_MAS, + QNOC_MASTER_VIDEO_P0, + QNOC_MASTER_VIDEO_P1, + QNOC_MASTER_VFE0, + QNOC_MASTER_VFE1, + QNOC_MASTER_CPP, + QNOC_MASTER_QDSS_ETR, + QNOC_MASTER_LPASS_PROC, + QNOC_MASTER_IPA, + QNOC_PNOC_M_0, + QNOC_PNOC_M_1, + QNOC_PNOC_INT_0, + QNOC_PNOC_INT_1, + QNOC_PNOC_INT_2, + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_3, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_8, + QNOC_PNOC_SLV_9, + QNOC_SNOC_MM_INT_0, + QNOC_SNOC_QDSS_INT, + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_INT_2, + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV, + QNOC_SLAVE_TCSR, + QNOC_SLAVE_TLMM, + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_MESSAGE_RAM, + QNOC_SLAVE_PDM, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_PMIC_ARB, + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_DCC_CFG, + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG, + QNOC_SLAVE_SDCC_1, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_SDCC_3, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_USB_HS2, + QNOC_SLAVE_BLSP_2, + QNOC_PNOC_SNOC_SLV, + QNOC_SLAVE_APPSS, + QNOC_MNOC_BIMC_SLV, + QNOC_SNOC_BIMC_SLV, + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SNOC_PNOC_SLV, + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, + QNOC_SLAVE_LPASS, +}; + +static const u16 mas_apps_proc_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_apps_proc =3D { + .name =3D "mas_apps_proc", + .id =3D QNOC_MASTER_AMPSS_M0, + .buswidth =3D 16, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_apps_proc_links), + .links =3D mas_apps_proc_links, +}; + +static const u16 mas_smmnoc_bimc_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_smmnoc_bimc =3D { + .name =3D "mas_smmnoc_bimc", + .id =3D QNOC_MNOC_BIMC_MAS, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D 135, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 2, + .num_links =3D ARRAY_SIZE(mas_smmnoc_bimc_links), + .links =3D mas_smmnoc_bimc_links, +}; + +static const u16 mas_snoc_bimc_links[] =3D { + QNOC_SLAVE_EBI_CH0 +}; + +static struct qcom_icc_node mas_snoc_bimc =3D { + .name =3D "mas_snoc_bimc", + .id =3D QNOC_SNOC_BIMC_MAS, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 3, + .num_links =3D ARRAY_SIZE(mas_snoc_bimc_links), + .links =3D mas_snoc_bimc_links, +}; + +static const u16 mas_tcu_0_links[] =3D { + QNOC_SLAVE_EBI_CH0, + QNOC_BIMC_SNOC_SLV +}; + +static struct qcom_icc_node mas_tcu_0 =3D { + .name =3D "mas_tcu_0", + .id =3D QNOC_MASTER_TCU_0, + .buswidth =3D 16, + .mas_rpm_id =3D 102, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 2, + .qos.qos_port =3D 4, + .num_links =3D ARRAY_SIZE(mas_tcu_0_links), + .links =3D mas_tcu_0_links, +}; + +static const u16 mas_usb_hs2_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_usb_hs2 =3D { + .name =3D "mas_usb_hs2", + .id =3D QNOC_MASTER_USB_HS2, + .buswidth =3D 4, + .mas_rpm_id =3D 57, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs2_links), + .links =3D mas_usb_hs2_links, +}; + +static const u16 mas_blsp_1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_1 =3D { + .name =3D "mas_blsp_1", + .id =3D QNOC_MASTER_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D 41, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_1_links), + .links =3D mas_blsp_1_links, +}; + +static const u16 mas_usb_hs1_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_usb_hs1 =3D { + .name =3D "mas_usb_hs1", + .id =3D QNOC_MASTER_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D 42, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_usb_hs1_links), + .links =3D mas_usb_hs1_links, +}; + +static const u16 mas_blsp_2_links[] =3D { + QNOC_PNOC_M_1 +}; + +static struct qcom_icc_node mas_blsp_2 =3D { + .name =3D "mas_blsp_2", + .id =3D QNOC_MASTER_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D 39, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_blsp_2_links), + .links =3D mas_blsp_2_links, +}; + +static const u16 mas_crypto_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_crypto =3D { + .name =3D "mas_crypto", + .id =3D QNOC_MASTER_CRYPTO_CORE0, + .buswidth =3D 8, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 0, + .num_links =3D ARRAY_SIZE(mas_crypto_links), + .links =3D mas_crypto_links, +}; + +static const u16 mas_sdcc_1_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_1 =3D { + .name =3D "mas_sdcc_1", + .id =3D QNOC_MASTER_SDCC_1, + .buswidth =3D 8, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_sdcc_1_links), + .links =3D mas_sdcc_1_links, +}; + +static const u16 mas_sdcc_2_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_2 =3D { + .name =3D "mas_sdcc_2", + .id =3D QNOC_MASTER_SDCC_2, + .buswidth =3D 8, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_sdcc_2_links), + .links =3D mas_sdcc_2_links, +}; + +static const u16 mas_sdcc_3_links[] =3D { + QNOC_PNOC_INT_1 +}; + +static struct qcom_icc_node mas_sdcc_3 =3D { + .name =3D "mas_sdcc_3", + .id =3D QNOC_MASTER_SDCC_3, + .buswidth =3D 8, + .mas_rpm_id =3D 34, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_sdcc_3_links), + .links =3D mas_sdcc_3_links, +}; + +static const u16 mas_snoc_pcnoc_links[] =3D { + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node mas_snoc_pcnoc =3D { + .name =3D "mas_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 77, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_snoc_pcnoc_links), + .links =3D mas_snoc_pcnoc_links, +}; + +static const u16 mas_lpass_ahb_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node mas_lpass_ahb =3D { + .name =3D "mas_lpass_ahb", + .id =3D QNOC_MASTER_LPASS_AHB, + .buswidth =3D 8, + .mas_rpm_id =3D 18, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_lpass_ahb_links), + .links =3D mas_lpass_ahb_links, +}; + +static const u16 mas_spdm_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_spdm =3D { + .name =3D "mas_spdm", + .id =3D QNOC_MASTER_SPDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_spdm_links), + .links =3D mas_spdm_links, +}; + +static const u16 mas_dehr_links[] =3D { + QNOC_PNOC_M_0 +}; + +static struct qcom_icc_node mas_dehr =3D { + .name =3D "mas_dehr", + .id =3D QNOC_MASTER_DEHR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_dehr_links), + .links =3D mas_dehr_links, +}; + +static const u16 mas_xm_usb_hs1_links[] =3D { + QNOC_PNOC_INT_0 +}; + +static struct qcom_icc_node mas_xm_usb_hs1 =3D { + .name =3D "mas_xm_usb_hs1", + .id =3D QNOC_MASTER_XM_USB_HS1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_xm_usb_hs1_links), + .links =3D mas_xm_usb_hs1_links, +}; + +static const u16 mas_qdss_bam_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_bam =3D { + .name =3D "mas_qdss_bam", + .id =3D QNOC_MASTER_QDSS_BAM, + .buswidth =3D 4, + .mas_rpm_id =3D 19, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 11, + .num_links =3D ARRAY_SIZE(mas_qdss_bam_links), + .links =3D mas_qdss_bam_links, +}; + +static const u16 mas_bimc_snoc_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_bimc_snoc =3D { + .name =3D "mas_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_bimc_snoc_links), + .links =3D mas_bimc_snoc_links, +}; + +static const u16 mas_jpeg_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_jpeg =3D { + .name =3D "mas_jpeg", + .id =3D QNOC_MASTER_JPEG, + .buswidth =3D 16, + .mas_rpm_id =3D 7, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(mas_jpeg_links), + .links =3D mas_jpeg_links, +}; + +static const u16 mas_oxili_links[] =3D { + QNOC_MNOC_BIMC_SLV, + QNOC_SNOC_MM_INT_0 +}; + +static struct qcom_icc_node mas_oxili =3D { + .name =3D "mas_oxili", + .id =3D QNOC_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 16, + .ib_coeff =3D 200, + .mas_rpm_id =3D 6, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 16, /* [16, 17] */ + .num_links =3D ARRAY_SIZE(mas_oxili_links), + .links =3D mas_oxili_links, +}; + +static const u16 mas_mdp0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_mdp0 =3D { + .name =3D "mas_mdp0", + .id =3D QNOC_MASTER_MDP_PORT0, + .buswidth =3D 16, + .ib_coeff =3D 50, + .mas_rpm_id =3D 8, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 7, + .num_links =3D ARRAY_SIZE(mas_mdp0_links), + .links =3D mas_mdp0_links, +}; + +static const u16 mas_mdp1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_mdp1 =3D { + .name =3D "mas_mdp1", + .id =3D QNOC_MASTER_MDP_PORT1, + .buswidth =3D 16, + .ib_coeff =3D 50, + .mas_rpm_id =3D 61, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 13, + .num_links =3D ARRAY_SIZE(mas_mdp1_links), + .links =3D mas_mdp1_links, +}; + +static const u16 mas_pcnoc_snoc_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_pcnoc_snoc =3D { + .name =3D "mas_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_MAS, + .buswidth =3D 8, + .mas_rpm_id =3D 29, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(mas_pcnoc_snoc_links), + .links =3D mas_pcnoc_snoc_links, +}; + +static const u16 mas_venus_0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_venus_0 =3D { + .name =3D "mas_venus_0", + .id =3D QNOC_MASTER_VIDEO_P0, + .buswidth =3D 16, + .mas_rpm_id =3D 9, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 8, + .num_links =3D ARRAY_SIZE(mas_venus_0_links), + .links =3D mas_venus_0_links, +}; + +static const u16 mas_venus_1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_venus_1 =3D { + .name =3D "mas_venus_1", + .id =3D QNOC_MASTER_VIDEO_P1, + .buswidth =3D 16, + .mas_rpm_id =3D 10, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 14, + .num_links =3D ARRAY_SIZE(mas_venus_1_links), + .links =3D mas_venus_1_links, +}; + +static const u16 mas_vfe_0_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_vfe_0 =3D { + .name =3D "mas_vfe_0", + .id =3D QNOC_MASTER_VFE0, + .buswidth =3D 16, + .mas_rpm_id =3D 11, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 9, + .num_links =3D ARRAY_SIZE(mas_vfe_0_links), + .links =3D mas_vfe_0_links, +}; + +static const u16 mas_vfe_1_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_vfe_1 =3D { + .name =3D "mas_vfe_1", + .id =3D QNOC_MASTER_VFE1, + .buswidth =3D 16, + .mas_rpm_id =3D 133, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 15, + .num_links =3D ARRAY_SIZE(mas_vfe_1_links), + .links =3D mas_vfe_1_links, +}; + +static const u16 mas_cpp_links[] =3D { + QNOC_SNOC_MM_INT_0, + QNOC_MNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_cpp =3D { + .name =3D "mas_cpp", + .id =3D QNOC_MASTER_CPP, + .buswidth =3D 16, + .mas_rpm_id =3D 115, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 12, + .num_links =3D ARRAY_SIZE(mas_cpp_links), + .links =3D mas_cpp_links, +}; + +static const u16 mas_qdss_etr_links[] =3D { + QNOC_SNOC_QDSS_INT +}; + +static struct qcom_icc_node mas_qdss_etr =3D { + .name =3D "mas_qdss_etr", + .id =3D QNOC_MASTER_QDSS_ETR, + .buswidth =3D 8, + .mas_rpm_id =3D 31, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 10, + .num_links =3D ARRAY_SIZE(mas_qdss_etr_links), + .links =3D mas_qdss_etr_links, +}; + +static const u16 mas_lpass_proc_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_SLV +}; + +static struct qcom_icc_node mas_lpass_proc =3D { + .name =3D "mas_lpass_proc", + .id =3D QNOC_MASTER_LPASS_PROC, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 19, + .num_links =3D ARRAY_SIZE(mas_lpass_proc_links), + .links =3D mas_lpass_proc_links, +}; + +static const u16 mas_ipa_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node mas_ipa =3D { + .name =3D "mas_ipa", + .id =3D QNOC_MASTER_IPA, + .buswidth =3D 8, + .mas_rpm_id =3D 59, + .slv_rpm_id =3D -1, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 1, + .qos.prio_level =3D 1, + .qos.qos_port =3D 18, + .num_links =3D ARRAY_SIZE(mas_ipa_links), + .links =3D mas_ipa_links, +}; + +static const u16 pcnoc_m_0_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_0 =3D { + .name =3D "pcnoc_m_0", + .id =3D QNOC_PNOC_M_0, + .buswidth =3D 4, + .mas_rpm_id =3D 87, + .slv_rpm_id =3D 116, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 5, + .num_links =3D ARRAY_SIZE(pcnoc_m_0_links), + .links =3D pcnoc_m_0_links, +}; + +static const u16 pcnoc_m_1_links[] =3D { + QNOC_PNOC_SNOC_SLV +}; + +static struct qcom_icc_node pcnoc_m_1 =3D { + .name =3D "pcnoc_m_1", + .id =3D QNOC_PNOC_M_1, + .buswidth =3D 4, + .mas_rpm_id =3D 88, + .slv_rpm_id =3D 117, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .qos.qos_port =3D 6, + .num_links =3D ARRAY_SIZE(pcnoc_m_1_links), + .links =3D pcnoc_m_1_links, +}; + +static const u16 pcnoc_int_0_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_0 =3D { + .name =3D "pcnoc_int_0", + .id =3D QNOC_PNOC_INT_0, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(pcnoc_int_0_links), + .links =3D pcnoc_int_0_links, +}; + +static const u16 pcnoc_int_1_links[] =3D { + QNOC_PNOC_SNOC_SLV, + QNOC_PNOC_INT_2 +}; + +static struct qcom_icc_node pcnoc_int_1 =3D { + .name =3D "pcnoc_int_1", + .id =3D QNOC_PNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 86, + .slv_rpm_id =3D 115, + .num_links =3D ARRAY_SIZE(pcnoc_int_1_links), + .links =3D pcnoc_int_1_links, +}; + +static const u16 pcnoc_int_2_links[] =3D { + QNOC_PNOC_SLV_1, + QNOC_PNOC_SLV_2, + QNOC_PNOC_SLV_4, + QNOC_PNOC_SLV_8, + QNOC_PNOC_SLV_9, + QNOC_PNOC_SLV_3 +}; + +static struct qcom_icc_node pcnoc_int_2 =3D { + .name =3D "pcnoc_int_2", + .id =3D QNOC_PNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 124, + .slv_rpm_id =3D 184, + .num_links =3D ARRAY_SIZE(pcnoc_int_2_links), + .links =3D pcnoc_int_2_links, +}; + +static const u16 pcnoc_s_1_links[] =3D { + QNOC_SLAVE_CRYPTO_0_CFG, + QNOC_SLAVE_PRNG, + QNOC_SLAVE_PDM, + QNOC_SLAVE_MESSAGE_RAM +}; + +static struct qcom_icc_node pcnoc_s_1 =3D { + .name =3D "pcnoc_s_1", + .id =3D QNOC_PNOC_SLV_1, + .buswidth =3D 4, + .mas_rpm_id =3D 90, + .slv_rpm_id =3D 119, + .num_links =3D ARRAY_SIZE(pcnoc_s_1_links), + .links =3D pcnoc_s_1_links, +}; + +static const u16 pcnoc_s_2_links[] =3D { + QNOC_SLAVE_PMIC_ARB +}; + +static struct qcom_icc_node pcnoc_s_2 =3D { + .name =3D "pcnoc_s_2", + .id =3D QNOC_PNOC_SLV_2, + .buswidth =3D 4, + .mas_rpm_id =3D 91, + .slv_rpm_id =3D 120, + .num_links =3D ARRAY_SIZE(pcnoc_s_2_links), + .links =3D pcnoc_s_2_links, +}; + +static const u16 pcnoc_s_3_links[] =3D { + QNOC_SLAVE_SNOC_CFG, + QNOC_SLAVE_DCC_CFG +}; + +static struct qcom_icc_node pcnoc_s_3 =3D { + .name =3D "pcnoc_s_3", + .id =3D QNOC_PNOC_SLV_3, + .buswidth =3D 4, + .mas_rpm_id =3D 92, + .slv_rpm_id =3D 121, + .num_links =3D ARRAY_SIZE(pcnoc_s_3_links), + .links =3D pcnoc_s_3_links, +}; + +static const u16 pcnoc_s_4_links[] =3D { + QNOC_SLAVE_CAMERA_CFG, + QNOC_SLAVE_DISPLAY_CFG, + QNOC_SLAVE_VENUS_CFG +}; + +static struct qcom_icc_node pcnoc_s_4 =3D { + .name =3D "pcnoc_s_4", + .id =3D QNOC_PNOC_SLV_4, + .buswidth =3D 4, + .mas_rpm_id =3D 93, + .slv_rpm_id =3D 122, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(pcnoc_s_4_links), + .links =3D pcnoc_s_4_links, +}; + +static const u16 pcnoc_s_8_links[] =3D { + QNOC_SLAVE_USB_HS, + QNOC_SLAVE_SDCC_3, + QNOC_SLAVE_BLSP_1, + QNOC_SLAVE_SDCC_1 +}; + +static struct qcom_icc_node pcnoc_s_8 =3D { + .name =3D "pcnoc_s_8", + .id =3D QNOC_PNOC_SLV_8, + .buswidth =3D 4, + .mas_rpm_id =3D 96, + .slv_rpm_id =3D 125, + .num_links =3D ARRAY_SIZE(pcnoc_s_8_links), + .links =3D pcnoc_s_8_links, +}; + +static const u16 pcnoc_s_9_links[] =3D { + QNOC_SLAVE_GRAPHICS_3D_CFG, + QNOC_SLAVE_USB_HS2, + QNOC_SLAVE_SDCC_2, + QNOC_SLAVE_BLSP_2 +}; + +static struct qcom_icc_node pcnoc_s_9 =3D { + .name =3D "pcnoc_s_9", + .id =3D QNOC_PNOC_SLV_9, + .buswidth =3D 4, + .mas_rpm_id =3D 97, + .slv_rpm_id =3D 126, + .num_links =3D ARRAY_SIZE(pcnoc_s_9_links), + .links =3D pcnoc_s_9_links, +}; + +static const u16 mm_int_0_links[] =3D { + QNOC_SNOC_INT_0 +}; + +static struct qcom_icc_node mm_int_0 =3D { + .name =3D "mm_int_0", + .id =3D QNOC_SNOC_MM_INT_0, + .buswidth =3D 16, + .ib_coeff =3D 200, + .mas_rpm_id =3D 79, + .slv_rpm_id =3D 108, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(mm_int_0_links), + .links =3D mm_int_0_links, +}; + +static const u16 qdss_int_links[] =3D { + QNOC_SNOC_INT_2 +}; + +static struct qcom_icc_node qdss_int =3D { + .name =3D "qdss_int", + .id =3D QNOC_SNOC_QDSS_INT, + .buswidth =3D 8, + .mas_rpm_id =3D 98, + .slv_rpm_id =3D 128, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(qdss_int_links), + .links =3D qdss_int_links, +}; + +static const u16 snoc_int_0_links[] =3D { + QNOC_SLAVE_QDSS_STM, + QNOC_SLAVE_SYSTEM_IMEM, + QNOC_SNOC_PNOC_SLV +}; + +static struct qcom_icc_node snoc_int_0 =3D { + .name =3D "snoc_int_0", + .id =3D QNOC_SNOC_INT_0, + .buswidth =3D 8, + .mas_rpm_id =3D 99, + .slv_rpm_id =3D 130, + .num_links =3D ARRAY_SIZE(snoc_int_0_links), + .links =3D snoc_int_0_links, +}; + +static const u16 snoc_int_1_links[] =3D { + QNOC_SLAVE_LPASS, + QNOC_SLAVE_CATS_128, + QNOC_SLAVE_OCMEM_64, + QNOC_SLAVE_APPSS +}; + +static struct qcom_icc_node snoc_int_1 =3D { + .name =3D "snoc_int_1", + .id =3D QNOC_SNOC_INT_1, + .buswidth =3D 8, + .mas_rpm_id =3D 100, + .slv_rpm_id =3D 131, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(snoc_int_1_links), + .links =3D snoc_int_1_links, +}; + +static const u16 snoc_int_2_links[] =3D { + QNOC_SNOC_INT_0, + QNOC_SNOC_INT_1, + QNOC_SNOC_BIMC_SLV +}; + +static struct qcom_icc_node snoc_int_2 =3D { + .name =3D "snoc_int_2", + .id =3D QNOC_SNOC_INT_2, + .buswidth =3D 8, + .mas_rpm_id =3D 134, + .slv_rpm_id =3D 197, + .num_links =3D ARRAY_SIZE(snoc_int_2_links), + .links =3D snoc_int_2_links, +}; + +static struct qcom_icc_node slv_ebi =3D { + .name =3D "slv_ebi", + .id =3D QNOC_SLAVE_EBI_CH0, + .channels =3D 2, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 slv_bimc_snoc_links[] =3D { + QNOC_BIMC_SNOC_MAS +}; + +static struct qcom_icc_node slv_bimc_snoc =3D { + .name =3D "slv_bimc_snoc", + .id =3D QNOC_BIMC_SNOC_SLV, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(slv_bimc_snoc_links), + .links =3D slv_bimc_snoc_links, +}; + +static struct qcom_icc_node slv_tcsr =3D { + .name =3D "slv_tcsr", + .id =3D QNOC_SLAVE_TCSR, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 50, +}; + +static struct qcom_icc_node slv_tlmm =3D { + .name =3D "slv_tlmm", + .id =3D QNOC_SLAVE_TLMM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 51, +}; + +static struct qcom_icc_node slv_crypto_0_cfg =3D { + .name =3D "slv_crypto_0_cfg", + .id =3D QNOC_SLAVE_CRYPTO_0_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 52, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_message_ram =3D { + .name =3D "slv_message_ram", + .id =3D QNOC_SLAVE_MESSAGE_RAM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 55, +}; + +static struct qcom_icc_node slv_pdm =3D { + .name =3D "slv_pdm", + .id =3D QNOC_SLAVE_PDM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 41, +}; + +static struct qcom_icc_node slv_prng =3D { + .name =3D "slv_prng", + .id =3D QNOC_SLAVE_PRNG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 44, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_pmic_arb =3D { + .name =3D "slv_pmic_arb", + .id =3D QNOC_SLAVE_PMIC_ARB, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 59, +}; + +static struct qcom_icc_node slv_snoc_cfg =3D { + .name =3D "slv_snoc_cfg", + .id =3D QNOC_SLAVE_SNOC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 70, +}; + +static struct qcom_icc_node slv_dcc_cfg =3D { + .name =3D "slv_dcc_cfg", + .id =3D QNOC_SLAVE_DCC_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 155, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_camera_ss_cfg =3D { + .name =3D "slv_camera_ss_cfg", + .id =3D QNOC_SLAVE_CAMERA_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 3, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_disp_ss_cfg =3D { + .name =3D "slv_disp_ss_cfg", + .id =3D QNOC_SLAVE_DISPLAY_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 4, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_venus_cfg =3D { + .name =3D "slv_venus_cfg", + .id =3D QNOC_SLAVE_VENUS_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 10, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_sdcc_1 =3D { + .name =3D "slv_sdcc_1", + .id =3D QNOC_SLAVE_SDCC_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 31, +}; + +static struct qcom_icc_node slv_blsp_1 =3D { + .name =3D "slv_blsp_1", + .id =3D QNOC_SLAVE_BLSP_1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 39, +}; + +static struct qcom_icc_node slv_usb_hs =3D { + .name =3D "slv_usb_hs", + .id =3D QNOC_SLAVE_USB_HS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 40, +}; + +static struct qcom_icc_node slv_sdcc_3 =3D { + .name =3D "slv_sdcc_3", + .id =3D QNOC_SLAVE_SDCC_3, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 32, +}; + +static struct qcom_icc_node slv_sdcc_2 =3D { + .name =3D "slv_sdcc_2", + .id =3D QNOC_SLAVE_SDCC_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 33, +}; + +static struct qcom_icc_node slv_gpu_cfg =3D { + .name =3D "slv_gpu_cfg", + .id =3D QNOC_SLAVE_GRAPHICS_3D_CFG, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 11, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_usb_hs2 =3D { + .name =3D "slv_usb_hs2", + .id =3D QNOC_SLAVE_USB_HS2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 79, +}; + +static struct qcom_icc_node slv_blsp_2 =3D { + .name =3D "slv_blsp_2", + .id =3D QNOC_SLAVE_BLSP_2, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 37, +}; + +static const u16 slv_pcnoc_snoc_links[] =3D { + QNOC_PNOC_SNOC_MAS +}; + +static struct qcom_icc_node slv_pcnoc_snoc =3D { + .name =3D "slv_pcnoc_snoc", + .id =3D QNOC_PNOC_SNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 45, + .num_links =3D ARRAY_SIZE(slv_pcnoc_snoc_links), + .links =3D slv_pcnoc_snoc_links, +}; + +static struct qcom_icc_node slv_kpss_ahb =3D { + .name =3D "slv_kpss_ahb", + .id =3D QNOC_SLAVE_APPSS, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 20, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static const u16 slv_smmnoc_bimc_links[] =3D { + QNOC_MNOC_BIMC_MAS +}; + +static struct qcom_icc_node slv_smmnoc_bimc =3D { + .name =3D "slv_smmnoc_bimc", + .id =3D QNOC_MNOC_BIMC_SLV, + .channels =3D 2, + .buswidth =3D 16, + .ib_coeff =3D 200, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 198, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_smmnoc_bimc_links), + .links =3D slv_smmnoc_bimc_links, +}; + +static const u16 slv_snoc_bimc_links[] =3D { + QNOC_SNOC_BIMC_MAS +}; + +static struct qcom_icc_node slv_snoc_bimc =3D { + .name =3D "slv_snoc_bimc", + .id =3D QNOC_SNOC_BIMC_SLV, + .channels =3D 2, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 24, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_links), + .links =3D slv_snoc_bimc_links, +}; + +static struct qcom_icc_node slv_imem =3D { + .name =3D "slv_imem", + .id =3D QNOC_SLAVE_SYSTEM_IMEM, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static const u16 slv_snoc_pcnoc_links[] =3D { + QNOC_SNOC_PNOC_MAS +}; + +static struct qcom_icc_node slv_snoc_pcnoc =3D { + .name =3D "slv_snoc_pcnoc", + .id =3D QNOC_SNOC_PNOC_SLV, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 28, + .num_links =3D ARRAY_SIZE(slv_snoc_pcnoc_links), + .links =3D slv_snoc_pcnoc_links, +}; + +static struct qcom_icc_node slv_qdss_stm =3D { + .name =3D "slv_qdss_stm", + .id =3D QNOC_SLAVE_QDSS_STM, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node slv_cats_0 =3D { + .name =3D "slv_cats_0", + .id =3D QNOC_SLAVE_CATS_128, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 106, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_cats_1 =3D { + .name =3D "slv_cats_1", + .id =3D QNOC_SLAVE_OCMEM_64, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 107, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node slv_lpass =3D { + .name =3D "slv_lpass", + .id =3D QNOC_SLAVE_LPASS, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 21, + .qos.ap_owned =3D true, + .qos.qos_mode =3D NOC_QOS_MODE_INVALID, +}; + +static struct qcom_icc_node * const msm8976_bimc_nodes[] =3D { + [MAS_APPS_PROC] =3D &mas_apps_proc, + [MAS_SMMNOC_BIMC] =3D &mas_smmnoc_bimc, + [MAS_SNOC_BIMC] =3D &mas_snoc_bimc, + [MAS_TCU_0] =3D &mas_tcu_0, + [SLV_EBI] =3D &slv_ebi, + [SLV_BIMC_SNOC] =3D &slv_bimc_snoc, +}; + +static const struct regmap_config msm8976_bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x62000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_bimc =3D { + .type =3D QCOM_ICC_BIMC, + .nodes =3D msm8976_bimc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_bimc_nodes), + .bus_clk_desc =3D &bimc_clk, + .regmap_cfg =3D &msm8976_bimc_regmap_config, + .qos_offset =3D 0x8000, + .ab_coeff =3D 154, +}; + +static struct qcom_icc_node * const msm8976_pcnoc_nodes[] =3D { + [MAS_USB_HS2] =3D &mas_usb_hs2, + [MAS_BLSP_1] =3D &mas_blsp_1, + [MAS_USB_HS1] =3D &mas_usb_hs1, + [MAS_BLSP_2] =3D &mas_blsp_2, + [MAS_CRYPTO] =3D &mas_crypto, + [MAS_SDCC_1] =3D &mas_sdcc_1, + [MAS_SDCC_2] =3D &mas_sdcc_2, + [MAS_SDCC_3] =3D &mas_sdcc_3, + [MAS_SNOC_PCNOC] =3D &mas_snoc_pcnoc, + [MAS_LPASS_AHB] =3D &mas_lpass_ahb, + [MAS_SPDM] =3D &mas_spdm, + [MAS_DEHR] =3D &mas_dehr, + [MAS_XM_USB_HS1] =3D &mas_xm_usb_hs1, + [PCNOC_M_0] =3D &pcnoc_m_0, + [PCNOC_M_1] =3D &pcnoc_m_1, + [PCNOC_INT_0] =3D &pcnoc_int_0, + [PCNOC_INT_1] =3D &pcnoc_int_1, + [PCNOC_INT_2] =3D &pcnoc_int_2, + [PCNOC_S_1] =3D &pcnoc_s_1, + [PCNOC_S_2] =3D &pcnoc_s_2, + [PCNOC_S_3] =3D &pcnoc_s_3, + [PCNOC_S_4] =3D &pcnoc_s_4, + [PCNOC_S_8] =3D &pcnoc_s_8, + [PCNOC_S_9] =3D &pcnoc_s_9, + [SLV_TCSR] =3D &slv_tcsr, + [SLV_TLMM] =3D &slv_tlmm, + [SLV_CRYPTO_0_CFG] =3D &slv_crypto_0_cfg, + [SLV_MESSAGE_RAM] =3D &slv_message_ram, + [SLV_PDM] =3D &slv_pdm, + [SLV_PRNG] =3D &slv_prng, + [SLV_PMIC_ARB] =3D &slv_pmic_arb, + [SLV_SNOC_CFG] =3D &slv_snoc_cfg, + [SLV_DCC_CFG] =3D &slv_dcc_cfg, + [SLV_CAMERA_SS_CFG] =3D &slv_camera_ss_cfg, + [SLV_DISP_SS_CFG] =3D &slv_disp_ss_cfg, + [SLV_VENUS_CFG] =3D &slv_venus_cfg, + [SLV_SDCC_1] =3D &slv_sdcc_1, + [SLV_BLSP_1] =3D &slv_blsp_1, + [SLV_USB_HS] =3D &slv_usb_hs, + [SLV_SDCC_3] =3D &slv_sdcc_3, + [SLV_SDCC_2] =3D &slv_sdcc_2, + [SLV_GPU_CFG] =3D &slv_gpu_cfg, + [SLV_USB_HS2] =3D &slv_usb_hs2, + [SLV_BLSP_2] =3D &slv_blsp_2, + [SLV_PCNOC_SNOC] =3D &slv_pcnoc_snoc, +}; + +static const struct regmap_config msm8976_pcnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_pcnoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_pcnoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_pcnoc_nodes), + .bus_clk_desc =3D &bus_0_clk, + .qos_offset =3D 0x7000, + .keep_alive =3D true, + .regmap_cfg =3D &msm8976_pcnoc_regmap_config, +}; + +static struct qcom_icc_node * const msm8976_snoc_nodes[] =3D { + [MAS_QDSS_BAM] =3D &mas_qdss_bam, + [MAS_BIMC_SNOC] =3D &mas_bimc_snoc, + [MAS_PCNOC_SNOC] =3D &mas_pcnoc_snoc, + [MAS_QDSS_ETR] =3D &mas_qdss_etr, + [MAS_LPASS_PROC] =3D &mas_lpass_proc, + [MAS_IPA] =3D &mas_ipa, + [QDSS_INT] =3D &qdss_int, + [SNOC_INT_0] =3D &snoc_int_0, + [SNOC_INT_1] =3D &snoc_int_1, + [SNOC_INT_2] =3D &snoc_int_2, + [SLV_KPSS_AHB] =3D &slv_kpss_ahb, + [SLV_SNOC_BIMC] =3D &slv_snoc_bimc, + [SLV_IMEM] =3D &slv_imem, + [SLV_SNOC_PCNOC] =3D &slv_snoc_pcnoc, + [SLV_QDSS_STM] =3D &slv_qdss_stm, + [SLV_CATS_0] =3D &slv_cats_0, + [SLV_CATS_1] =3D &slv_cats_1, + [SLV_LPASS] =3D &slv_lpass, +}; + +static const struct regmap_config msm8976_snoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1A000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc msm8976_snoc =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_snoc_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_snoc_nodes), + .bus_clk_desc =3D &bus_1_clk, + .regmap_cfg =3D &msm8976_snoc_regmap_config, + .qos_offset =3D 0x7000, +}; + +static struct qcom_icc_node * const msm8976_snoc_mm_nodes[] =3D { + [MAS_JPEG] =3D &mas_jpeg, + [MAS_OXILI] =3D &mas_oxili, + [MAS_MDP0] =3D &mas_mdp0, + [MAS_MDP1] =3D &mas_mdp1, + [MAS_VENUS_0] =3D &mas_venus_0, + [MAS_VENUS_1] =3D &mas_venus_1, + [MAS_VFE_0] =3D &mas_vfe_0, + [MAS_VFE_1] =3D &mas_vfe_1, + [MAS_CPP] =3D &mas_cpp, + [MM_INT_0] =3D &mm_int_0, + [SLV_SMMNOC_BIMC] =3D &slv_smmnoc_bimc, +}; + +static const struct qcom_icc_desc msm8976_snoc_mm =3D { + .type =3D QCOM_ICC_NOC, + .nodes =3D msm8976_snoc_mm_nodes, + .num_nodes =3D ARRAY_SIZE(msm8976_snoc_mm_nodes), + .bus_clk_desc =3D &bus_2_clk, + .regmap_cfg =3D &msm8976_snoc_regmap_config, + .qos_offset =3D 0x7000, + .ab_coeff =3D 154, +}; + +static const struct of_device_id msm8976_noc_of_match[] =3D { + { .compatible =3D "qcom,msm8976-bimc", .data =3D &msm8976_bimc }, + { .compatible =3D "qcom,msm8976-pcnoc", .data =3D &msm8976_pcnoc }, + { .compatible =3D "qcom,msm8976-snoc", .data =3D &msm8976_snoc }, + { .compatible =3D "qcom,msm8976-snoc-mm", .data =3D &msm8976_snoc_mm }, + { } +}; +MODULE_DEVICE_TABLE(of, msm8976_noc_of_match); + +static struct platform_driver msm8976_noc_driver =3D { + .probe =3D qnoc_probe, + .remove_new =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-msm8976", + .of_match_table =3D msm8976_noc_of_match, + .sync_state =3D icc_sync_state, + }, +}; +module_platform_driver(msm8976_noc_driver); + +MODULE_DESCRIPTION("Qualcomm MSM8976 NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2