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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:29 +0200 Subject: [PATCH v5 1/5] drm/msm/adreno: Implement SMEM-based speed bin Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240709-topic-smem_speedbin-v5-1-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=6084; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EZnPsbf895Nk5+GhF8GX16MJZewwBwjtmiFmsqKVj/E=; b=ofzGt665lRV73DHN1FYY/bCFj4utkgtRqb78xzJO4AhiNNAaX88SPIUrJ7rZTp+qwl8D+dgx/ Qjtzuwfx42BCGsI3SBnFhMjoYrnCMLAynqXFghKGFuzriKzoFSYGeJk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 42 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index bcaec86ac67a..0d8682c28ba4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2117,18 +2117,20 @@ static u32 fuse_to_supp_hw(const struct adreno_info= *info, u32 fuse) return UINT_MAX; } =20 -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_i= nfo *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; =20 - ret =3D adreno_read_speedbin(dev, &speedbin); + ret =3D adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine + * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin + * which is fine */ - if (ret =3D=3D -ENOENT) { + if (ret =3D=3D -ENOENT || ret =3D=3D -EOPNOTSUPP) { return 0; } else if (ret) { dev_err_probe(dev, ret, @@ -2283,7 +2285,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->info); + ret =3D a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index cfc74a9e2646..0842ea76e616 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ =20 +#include + #include "adreno_gpu.h" =20 bool hang_debug =3D false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 1c6626747b98..cf6652c4439d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" =20 +#include +#include + static u64 address_space_size =3D 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes priva= te GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1061,9 +1064,40 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *a= dreno_ocmem) adreno_ocmem->hdl); } =20 -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret =3D nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret !=3D -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n= "); + +#ifdef CONFIG_QCOM_SMEM + u32 fcode; + + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret =3D qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse =3D ADRENO_SKU_ID(fcode); + else if (ret !=3D -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return ret; } =20 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1102,9 +1136,9 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } =20 - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin =3D 0xffff; - adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin =3D speedbin; =20 gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 1ab523a163a0..0d629343ebb4 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,6 +79,10 @@ struct adreno_reglist { =20 struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; =20 @@ -555,7 +559,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned = long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); =20 -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:35 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:30 +0200 Subject: [PATCH v5 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240709-topic-smem_speedbin-v5-2-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=1480; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qLAOTrSFtuBecm3+EwggXg43xqGrGY4RLrmT8vpNaLU=; b=felzT5CFkBH3CSD4+amuMEw8IiUfz80JoigCu+pRFOy5BlFTjJygWaDDjwtuKGHNKBhm30wZg NBUe1/jVPMZBLTAjuLJBMe6dl3+f4IGUf2f654Aut78+wx/zTfxZ3ug X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 68ba9aed5506..e3322f6aec13 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" =20 +#include +#include + static const struct adreno_reglist a612_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1209,6 +1212,11 @@ static const struct adreno_info a7xx_gpus[] =3D { .gmu_chipid =3D 0x7020100, }, .address_space_size =3D SZ_16G, + .speedbins =3D ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43050c01), /* "C512v2" */ .family =3D ADRENO_7XX_GEN2, --=20 2.45.2 From nobody Wed Dec 17 15:34:29 2025 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ABE9157466 for ; Tue, 9 Jul 2024 10:45:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720521958; cv=none; b=QxPejsV5lxOsoe+qyE3zEWeDTtFDrkmYdd8nAiHgCvgfL7S8g831yoCXFde4oVP1O0L4Ew+1G0iPaPu3u2VlNZedBjdABhtGFrKsgKsBUn2J0S3Sw0AN9GPKZgyZrZM9961vTYh2h2YELAyx5nK7p/ichXagbnYjiohRCIUzRlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720521958; c=relaxed/simple; bh=4D54MBq6zoAcYkfe7iD2ltE1UzYmVaRiFpw+gSQkiFQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eKcPHjeqBKK5W5OoBYD5qZ71eePDj6A++3dqgmUhMPjH2hPnnlR/3rUtZ4AYoMeeVdmvZxfG3cquT0FITb3n/8IysfDZRlLjVcyODMJysIuS4dHg84e0ZsadqqjQAHO54Tvzhf8K/IiRmUNYg2WEdu4+Q1OzXxESODxfqGEgb/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fEr11I1O; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fEr11I1O" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a77c4309fc8so533864466b.3 for ; Tue, 09 Jul 2024 03:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720521955; x=1721126755; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OCdrWwyibH7SidMAd8gXxhcbnOnPffTnyQEY5fVW104=; b=fEr11I1OzCK500TytfuuvEz3wC0K2XALleau/t3ifocJ0lwCwxzl2l9IuGb0zU0rQa s0NlR23kSP1maB7UScBAGUBhYReO41YonPZyH1tlHl4FyDg5ROjZqpx4LAgtj0wo2q72 r8DG4MZRLyGabkIy5T/RZifzfSCYZQV/tGgIKiq8bw402idly2Eu4bJMlSBu7BAdRrx9 QnED4bmAkEcuBjZZwjaPXSiawiDWt6HgthIffaaHRmoa92QPzgz/rTzjCFfgzNUiGBZ8 i8NE6+Az5V+iNcO+muGzvsTJbhtHT9ssW+EKb4WptgSx8HoE7q28YFSUpylndLgJMZtm PqAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720521955; x=1721126755; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OCdrWwyibH7SidMAd8gXxhcbnOnPffTnyQEY5fVW104=; b=blpM6dAtUExtKBwDzTByorjIGEkTYXeoTVqFhDoZFlpvpJTLwFu4sDyiqPovcNBbCI a1eSNtNFd1mK0HQ+yEwg4oGvIhxv9lVRwzD18vqO3zbNqVEE7vgY1MXOm+wIUqeBD4Nc PJckoU+kh7cssppOhU3ihgrBGxej3skup3P81RZw2rrvw/XWbCdD5iysxijkG/Fc9qnj Qlz1IqR3Hqd3vwbmL/+eCZhw2ackpr//bn5gq7QoEjrqUKrAhl9xhiI0P+WSbn6d1Tqn uRIb8unIUC3E5WpoAxetoGWO7BigVtq9OCRXgvU5tQkkkx9wW0r/nxj1LcxLgXvpKeu4 2GCA== X-Forwarded-Encrypted: i=1; AJvYcCUsCTiCDAyAM+HerlZARaY5yiG6SwN/0lPT/JGd0s4+jI6NoKKspb9zwcBD/BEy3Wc82vNPTeWCWSWH4RyB+xQYVQagd1m80jvd3HnO X-Gm-Message-State: AOJu0Yy6yXCUNycsAAnJqHHwkem1V6vnWjKg+zH21ZJxgjHKnoQmyjp0 Hlgjl4mPgYdCrUfMxn9oqdMdOrTe1n+aNPJnJHL4uYioDxDsTYl/2gOaTrDjrVg= X-Google-Smtp-Source: AGHT+IEnddeAQttVIjPlE5QwA1Ejq9Sgylm5fg+WQ2PeIGDvlnpy6g/83mPoUVgnq4+Ux2PORfhdCA== X-Received: by 2002:a17:907:3f20:b0:a72:554d:82af with SMTP id a640c23a62f3a-a780df5e5fbmr146263266b.20.1720521938009; Tue, 09 Jul 2024 03:45:38 -0700 (PDT) Received: from [192.168.105.194] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:37 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:31 +0200 Subject: [PATCH v5 3/5] drm/msm/adreno: Define A530 speed bins explicitly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240709-topic-smem_speedbin-v5-3-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4D54MBq6zoAcYkfe7iD2ltE1UzYmVaRiFpw+gSQkiFQ=; b=WfLMIj4SCvcJlhKnPfLp36Ctyq2d6AHSfVTYR87sgyW+uMP6er36Q2p56z8XMiCz66+azs3NP ysIMX7TBRifDWp6wRSAsHAMRBbWj13kMAR33/CyVT8WKhZ6XMnbO7V7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a5xx_catalog.c index 633f31539162..105b3d14bd75 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -129,6 +129,12 @@ static const struct adreno_info a5xx_gpus[] =3D { ADRENO_QUIRK_FAULT_DETECT_MASK, .init =3D a5xx_gpu_init, .zapfw =3D "a530_zap.mdt", + .speedbins =3D ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05040001), .family =3D ADRENO_5XX, --=20 2.45.2 From nobody Wed Dec 17 15:34:29 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B922C15749B for ; Tue, 9 Jul 2024 10:45:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720521960; cv=none; b=UOrj1Cnp4NqX/B1Qns+mrckjD9Az46XmQDjesg4ITapqOEBteOmqHgj1E8V2tOO+TnhISjFYyR/DJSLqjMutliK1xLLqf1kPlq8F1e+Nhfe+ABhUXevjLjS7gmeN2OoFPr+U9MG26xy8y0qm2t+IY7L1uAxKBVbzLtLCgGm2StQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720521960; c=relaxed/simple; bh=ZSzgpQ49WT7GffGNsAbL1pXn75NnMBX03jO7rZdfrlQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eGQdCQbYo1o/rWyiZsmHiQC60DdBr8NOJyr0sKkFvoEi8Wh2mGWWPyvvIbEqcm45lvqxg8LIIuKkW2Qof4txh+dVv7jwYmmgSR0MADZxrrQnR8rBRlOiIGTKtlxmYSrHhCEKnq1AeXQwozCGsTxaZxIpAHqDO2heRaaX9yikxnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=br9NbIhb; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="br9NbIhb" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a77dc08db60so425853866b.1 for ; Tue, 09 Jul 2024 03:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1720521957; x=1721126757; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+25nY/rYNm7YLajBTpZeCUf/L8baTplxhtXdEO1SETc=; b=br9NbIhbbNWT9Ql9ElwpSET5dJiysmyA/lARlYUo5/H3odh++Z2XCB6bzp2SMIi7Ab shadztK1tsBFReedT33Z3+J4ghyKfvgvSAQx5tJVxsqhqopMs2UahqPZCitI5XXo3jFY SeMLGgs24DCJsBctg1iAfkj10RJoYHeb34RN/yemW40tSoJ0hMrOLeDL6vEDPe5LOYW8 7hI+2aVRaEp2QA+CMrobYDqNCUTul7AYrTRYbOqKB8DXNfBbfyYcj71SK0fn1OdbeU7l 9cAv56GJ6PxHHG37G/od1WRZODbQPdbx2/TF0Qa8OUgLNj8RvE52tYpT+MbnRJb5K+Jl tftQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720521957; x=1721126757; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+25nY/rYNm7YLajBTpZeCUf/L8baTplxhtXdEO1SETc=; b=UdLvDaj4RO1G5MWyr1UZASVuGlDJaaZIK0WVMnsH3BQu/vZYC8hsAdZo2FXV/E2V/8 2pQzl8//q39+Frqpf3F5cSa/mjq29S7mS4BEUPrMqOFPjpOwMGAXzZvzHzMCclYTWRo3 snqu0Ia5e1HWAGvb2Dm91zUgVrA9NgA8ojpwRLb2f2d7cUu0jEF7Lrnapj2ioMe6jrta tUtmtl7KFJXdXgTPtJqcilQ+EYhR5J3wT6xn1BLP7GS00t2ps8fv+T7TSzJWbZ+vplJ8 VyiNq1zNiTbl1RwaklT4B8yBOGpBfb2gd/bar6xnCElEqdVJL6g6wIGyNK8A7Hczwmln hI0A== X-Forwarded-Encrypted: i=1; AJvYcCWlV2QAGQJUk1X19TWYd8Km/kMSt3O7M31iDo4AZ9wrksfzgta4+UXQ9stG9FdGjPSjQuG51KFA60mGymg5Nr+yZ1ApzvBsKKKFDCzq X-Gm-Message-State: AOJu0YyJUUJ31Q7Hqhr9qxQsVIwEnun1wuaKIch9BR0t1R3XkfOY9Ph6 pgpgZfSRWJvVhK9zyIdCtf6PPG8vA3PfX43ylVttoIY7kneU/hg8CahPlc26cek= X-Google-Smtp-Source: AGHT+IG5FoktpVWK5QM17btN/ecwjh50i59Wtdzqowaj+yV2WoSrncfLxmfmu2om6K3T1xTR5sEtYQ== X-Received: by 2002:a17:906:d9d1:b0:a77:ec9f:d9c1 with SMTP id a640c23a62f3a-a780b89d4bemr184412766b.70.1720521956898; Tue, 09 Jul 2024 03:45:56 -0700 (PDT) Received: from [192.168.105.194] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:32 +0200 Subject: [PATCH v5 4/5] drm/msm/adreno: Redo the speedbin assignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240709-topic-smem_speedbin-v5-4-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=7871; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZSzgpQ49WT7GffGNsAbL1pXn75NnMBX03jO7rZdfrlQ=; b=NDdA24B5tdof5NaIKHu2eEqkNTFs05sN8KmxuwUU4w3M0iDVaZvuPQaCX9QUrvaMXzWhZfbMo 0Fi5mtGdvHRD+RHdXNtusFL9vK44fnT9giovlszJqlvGOEca3vV5/C5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 -----------------------------= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 51 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 45 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index c0b5373e90d7..d62b12efac57 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1709,38 +1709,6 @@ static const struct adreno_gpu_funcs funcs =3D { .get_timestamp =3D a5xx_get_timestamp, }; =20 -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val =3D 0x80; - - cell =3D nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf =3D nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin =3D *((u8 *) buf); - - val =3D (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; @@ -1768,8 +1736,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) =20 a5xx_gpu->lm_leakage =3D 0x4E001A; =20 - check_speed_bin(&pdev->dev); - nr_rings =3D 4; =20 if (config->info->revn =3D=3D 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 0d8682c28ba4..849a14fe2319 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2105,55 +2105,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i =3D 0; info->speedbins[i].fuse !=3D SHRT_MAX; i++) - if (info->speedbins[i].fuse =3D=3D fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret =3D adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT/EOPNOTSUPP means that the platform doesn't support speedbin - * which is fine - */ - if (ret =3D=3D -ENOENT || ret =3D=3D -EOPNOTSUPP) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hard= ware\n"); - return ret; - } - - supp_hw =3D fuse_to_supp_hw(info, speedbin); - - if (supp_hw =3D=3D UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by h= ardware\n", - speedbin); - supp_hw =3D BIT(0); /* Default */ - } - - ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs =3D { .base =3D { .get_param =3D adreno_get_param, @@ -2285,13 +2236,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 - ret =3D a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if (is_a7xx) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index cf6652c4439d..6d0397a0554e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1064,8 +1064,8 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ad= reno_ocmem) adreno_ocmem->hdl); } =20 -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { int ret; =20 @@ -1100,6 +1100,46 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_g= pu, return ret; } =20 +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expecte= d by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct devic= e *dev) +{ + const struct adreno_info *info =3D adreno_gpu->info; + u32 fuse =3D ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw =3D UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU =3D> allow all defined OPPs */ + if (!info->speedbins) { + adreno_gpu->speedbin =3D ADRENO_SPEEDBIN_FUSE_NODATA; + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + /* + * If a real error (not counting older devicetrees having no nvmem refere= nces) + * occurs when trying to get the fuse value, bail out. + */ + ret =3D adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse =3D=3D ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT doesn't =3D> allow all = OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree= \n"); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + adreno_gpu->speedbin =3D fuse; + + /* Traverse the known speedbins */ + for (int i =3D 0; info->speedbins[i].fuse !=3D SHRT_MAX; i++) { + if (info->speedbins[i].fuse =3D=3D fuse) { + supp_hw =3D BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n"= , fuse); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -1109,7 +1149,6 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, struct msm_gpu_config adreno_gpu_config =3D { 0 }; struct msm_gpu *gpu =3D &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; =20 adreno_gpu->funcs =3D funcs; @@ -1136,9 +1175,9 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } =20 - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin =3D 0xffff; - adreno_gpu->speedbin =3D speedbin; + ret =3D adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; =20 gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 0d629343ebb4..eef450dc3732 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -559,9 +559,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned = long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); =20 -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a780a7ff038sm66295466b.115.2024.07.09.03.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 03:45:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 09 Jul 2024 12:45:33 +0200 Subject: [PATCH v5 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240709-topic-smem_speedbin-v5-5-e2146be0c96f@linaro.org> References: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> In-Reply-To: <20240709-topic-smem_speedbin-v5-0-e2146be0c96f@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720521930; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=UbAw9OwhyAwE8k7rUjhzv7OltpusBA6x/6YgB89OJWD+ojTrhyLuMSRDX4HAiIBsrrG0jevUW UobpDIs2ywfBIgClNuK2w9UxluMiW7//vluUrY7DilgVsJMyXYkgv3/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region =3D <&gpu_micro_code_mem>; }; =20 - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 + opp-719000000 { + opp-hz =3D /bits/ 64 <719000000>; + opp-level =3D ; + opp-supported-hw =3D <0x1>; + }; + opp-680000000 { opp-hz =3D /bits/ 64 <680000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-615000000 { opp-hz =3D /bits/ 64 <615000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-550000000 { opp-hz =3D /bits/ 64 <550000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-475000000 { opp-hz =3D /bits/ 64 <475000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-401000000 { opp-hz =3D /bits/ 64 <401000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-348000000 { opp-hz =3D /bits/ 64 <348000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-295000000 { opp-hz =3D /bits/ 64 <295000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-220000000 { opp-hz =3D /bits/ 64 <220000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; + }; + + opp-124800000 { + opp-hz =3D /bits/ 64 <124800000>; + opp-level =3D ; + opp-supported-hw =3D <0x3>; }; }; }; --=20 2.45.2