From nobody Wed Dec 17 19:04:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA2441CF8A for ; Mon, 8 Jul 2024 19:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720467166; cv=none; b=rjymiN1wuJnRp3ZO1MtnZBdY5Ycxt8eL1OBn0MpOlzELbHMQ1zgJh6x6PMzsklso+Od93fXNDBJD6tgKU9TaUPi8gG/zkhwhSYTaUDrA4qQqhYKjzF4f3LEwKjubf23EC4Pm2OLTtY6SWDUeCDBqFW89Ood8u+Jaa9INgf0gPpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720467166; c=relaxed/simple; bh=mvYpcvn8HdNEeFCNfMxdpJeijYhFR0AMPQTvbjyZGx0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AyHlpsZ/ChrSlq+dgFpCaB7STAQuTSWdv4vcM7ls8TqR4EgEL1DQ7Y+op31mDEdqxmyGSOs7K5nU6pGPnOP5y+bE0VlA7Z/7wfzFkdm2wVV5WbxtYLMm8MDfOulpvGaRLT7D+8YFGXOk6By22uO0gOERkmjvCjUpbU75VhTAi1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hqlDL/Af; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hqlDL/Af" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720467164; x=1752003164; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mvYpcvn8HdNEeFCNfMxdpJeijYhFR0AMPQTvbjyZGx0=; b=hqlDL/AfJwXeXwucBM8uwS4I3qxwYF0Rcto4bwrjQEx1K6Tr9qfn9rne 1ymVJ5/898sL6ovXEg817DGYPTc/22xnreA/DCHB3fFlBJlkItpmHDFJs Pg/U6FHylRCQLVTygJQQo5/Z7PJW3bw5tRkBCvVIhyrZXSRQnY7xk0ayO 43ks6FA4oi0HIswNoga/OJ9X3N+0wx3B+z6DhAkQEFy4bwtNZgXpQIyWA vQoN69hAoEvPxzDzNZxFChpqNqnQoR9m4IUtrQjincSyy7zD4hTuJQmqf Sro2ZjkkC0IhEJ6WGRzordLXTkNyrDPPvGHVaWWZSS9oG4rUMEk296Cky Q==; X-CSE-ConnectionGUID: VnWL6Zn8SQG/NJHUyrEveQ== X-CSE-MsgGUID: yNNZaNmmTb++LUkavmteBg== X-IronPort-AV: E=McAfee;i="6700,10204,11127"; a="17520486" X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="17520486" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2024 12:32:42 -0700 X-CSE-ConnectionGUID: TNRPMLeeRM+RzvuTgx3hyA== X-CSE-MsgGUID: 262OQIxyTqCm+g64Y09VOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="48265594" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orviesa007.jf.intel.com with ESMTP; 08 Jul 2024 12:32:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, Kan Liang , Dongli Zhang Subject: [PATCH 1/3] perf/x86/intel: Hide Topdown metrics events if the feature is not enumerated Date: Mon, 8 Jul 2024 12:33:34 -0700 Message-Id: <20240708193336.1192217-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240708193336.1192217-1-kan.liang@linux.intel.com> References: <20240708193336.1192217-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The below error is observed on Ice Lake VM. $ perf stat Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (slots). /bin/dmesg | grep -i perf may provide additional information. In a virtualization env, the Topdown metrics and the slots event haven't been supported yet. The guest CPUID doesn't enumerate them. However, the current kernel unconditionally exposes the slots event and the Topdown metrics events to sysfs, which misleads the perf tool and triggers the error. Hide the perf-metrics topdown events and the slots event if the perf-metrics feature is not enumerated. The big core of a hybrid platform can also supports the perf-metrics feature. Fix the hybrid platform as well. Reported-by: Dongli Zhang Closes: https://lore.kernel.org/lkml/CAM9d7cj8z+ryyzUHR+P1Dcpot2jjW+Qcc4CPQ= pfafTXN=3DLEU0Q@mail.gmail.com/ Tested-by: Dongli Zhang Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index cd8f2db6cdf6..b61367991a16 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5830,8 +5830,22 @@ exra_is_visible(struct kobject *kobj, struct attribu= te *attr, int i) return x86_pmu.version >=3D 2 ? attr->mode : 0; } =20 +static umode_t +td_is_visible(struct kobject *kobj, struct attribute *attr, int i) +{ + /* + * Hide the perf metrics topdown events + * if the feature is not enumerated. + */ + if (x86_pmu.num_topdown_events) + return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0; + + return attr->mode; +} + static struct attribute_group group_events_td =3D { .name =3D "events", + .is_visible =3D td_is_visible, }; =20 static struct attribute_group group_events_mem =3D { @@ -6057,9 +6071,27 @@ static umode_t hybrid_format_is_visible(struct kobje= ct *kobj, return (cpu >=3D 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode = : 0; } =20 +static umode_t hybrid_td_is_visible(struct kobject *kobj, + struct attribute *attr, int i) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct x86_hybrid_pmu *pmu =3D + container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); + + if (!is_attr_for_this_pmu(kobj, attr)) + return 0; + + + /* Only the big core supports perf metrics */ + if (pmu->pmu_type =3D=3D hybrid_big) + return pmu->intel_cap.perf_metrics ? attr->mode : 0; + + return attr->mode; +} + static struct attribute_group hybrid_group_events_td =3D { .name =3D "events", - .is_visible =3D hybrid_events_is_visible, + .is_visible =3D hybrid_td_is_visible, }; =20 static struct attribute_group hybrid_group_events_mem =3D { --=20 2.38.1 From nobody Wed Dec 17 19:04:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E5971CFAF; Mon, 8 Jul 2024 19:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720467166; cv=none; b=iZg6hk0V9UKM/Na9h6Wj+Y/eBAi7OESAu1T5eeYbtk94gCDlJ56o4nf8rvuH4jj2fB4c9nborVQAcChp9/2I/SKuZZrmpcxC2RJ0iHgWqKUOVZjZIrIZycDtLqWnCJjMOkuUO/6B3mZqY4jAoED9+PylKCsiHuEZUaXSFREtHgI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720467166; c=relaxed/simple; bh=9azAPtHQWpCrAcC4hsFvD58GfVAqXFENVg14P/0VMTw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ImpFgB8SZ5VuC3HR307Bn+e2Mvy0sTsCBZYPLPhCMzJTopb1JHz+qp8a8r2TKmo8IHZQnmjSTAC7nejqlyp0REbl7r1WIgWqwBgETTZbVRWnC+mBtvsIe96BVwhueIjWalipZLnkgP6IBL4T6RxClsAWtTXHSVA9uG3PzSlYaGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nRMJ59C4; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nRMJ59C4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720467165; x=1752003165; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9azAPtHQWpCrAcC4hsFvD58GfVAqXFENVg14P/0VMTw=; b=nRMJ59C4oFaKJwcss+I8DHqIw7Gm/UwvJVz1fFfQFTAYqqief3C6+inc 60dc8V7LSh221aNbNyyZIsYSyGhyGekTlqR2BhGGdopDcCLG0mG2N71l9 aNJwtJv/k63Xr3JgL3+Bi5Q/KUoXWJcUky8J/OfODH3r/wPHRgYmm8J+p ndtJz0t5tNqGiNQu9j1AsnmuOVKsmJQLs7lun5yccD/09PMeK+s0X9Tmw R7/LJWZ74GRbuOZGfEXjLGDNVcu62dZ52/2WVqkIp4qE+AXojyqbLjeP8 dCnRR8A4Hbhctdc+n3hTxciJn33Kq7EkPm9wSr2Ep55rtKN9OiQ9uivRh Q==; X-CSE-ConnectionGUID: fc1b70G3Rfe1ZeXglMy0NA== X-CSE-MsgGUID: FIZRcosYRVS1CV+dDNJrRw== X-IronPort-AV: E=McAfee;i="6700,10204,11127"; a="17520493" X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="17520493" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2024 12:32:42 -0700 X-CSE-ConnectionGUID: 6WwrchycRtSTQilbKLfyEg== X-CSE-MsgGUID: xWuTnf5kQvuR6i/rdnWOWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,192,1716274800"; d="scan'208";a="48265598" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orviesa007.jf.intel.com with ESMTP; 08 Jul 2024 12:32:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, Kan Liang , Ahmad Yasin , stable@vger.kernel.org Subject: [PATCH 2/3] perf/x86/intel: Add a distinct name for Granite Rapids Date: Mon, 8 Jul 2024 12:33:35 -0700 Message-Id: <20240708193336.1192217-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240708193336.1192217-1-kan.liang@linux.intel.com> References: <20240708193336.1192217-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Kan Liang Currently, the Sapphire Rapids and Granite Rapids share the same PMU name, sapphire_rapids. Because from the kernel=E2=80=99s perspective, GNR is similar to SPR. The only key difference is that they support different extra MSRs. The code path and the PMU name are shared. However, from end users' perspective, they are quite different. Besides the extra MSRs, GNR has a newer PEBS format, supports Retire Latency, supports new CPUID enumeration architecture, doesn't required the load-latency AUX event, has additional TMA Level 1 Architectural Events, etc. The differences can be enumerated by CPUID or the PERF_CAPABILITIES MSR. They weren't reflected in the model-specific kernel setup. But it is worth to have a distinct PMU name for GNR. Fixes: a6742cb90b56 ("perf/x86/intel: Fix the FRONTEND encoding on GNR and = MTL") Suggested-by: Ahmad Yasin Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/intel/core.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b61367991a16..7a9f931a1f48 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6943,12 +6943,17 @@ __init int intel_pmu_init(void) case INTEL_EMERALDRAPIDS_X: x86_pmu.flags |=3D PMU_FL_MEM_LOADS_AUX; x86_pmu.extra_regs =3D intel_glc_extra_regs; + pr_cont("Sapphire Rapids events, "); + name =3D "sapphire_rapids"; fallthrough; case INTEL_GRANITERAPIDS_X: case INTEL_GRANITERAPIDS_D: intel_pmu_init_glc(NULL); - if (!x86_pmu.extra_regs) + if (!x86_pmu.extra_regs) { x86_pmu.extra_regs =3D intel_rwc_extra_regs; + pr_cont("Granite Rapids events, "); + name =3D "granite_rapids"; + } x86_pmu.pebs_ept =3D 1; x86_pmu.hw_config =3D hsw_hw_config; x86_pmu.get_event_constraints =3D glc_get_event_constraints; @@ -6959,8 +6964,6 @@ __init int intel_pmu_init(void) td_attr =3D glc_td_events_attrs; tsx_attr =3D glc_tsx_events_attrs; intel_pmu_pebs_data_source_skl(true); - pr_cont("Sapphire Rapids events, "); - name =3D "sapphire_rapids"; break; =20 case INTEL_ALDERLAKE: --=20 2.38.1 From nobody Wed Dec 17 19:04:45 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53C3C14900C; Mon, 8 Jul 2024 19:32:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720467168; cv=none; b=sN8kTPLPj/eS9Xp7Fc3Tcj2X4RfJeG1n2iG9tjORaD936VpWKYJ85FbW2ZnAkw0WBTlUaHCVggvQdW6bSDKo7TowDLEGNbh61Sw4GRJdg6NwqqpivvOS5VlhLWMLoStqS7m7EyDuxuHLQYAKVhPIA2WPP3xMVwCkmERcQoK7zvU= ARC-Message-Signature: i=1; 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d="scan'208";a="48265602" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orviesa007.jf.intel.com with ESMTP; 08 Jul 2024 12:32:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, Kan Liang , "Bayduraev, Alexey V" , stable@vger.kernel.org Subject: [PATCH 3/3] perf/x86/intel/ds: Fix non 0 retire latency on Raptorlake Date: Mon, 8 Jul 2024 12:33:36 -0700 Message-Id: <20240708193336.1192217-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240708193336.1192217-1-kan.liang@linux.intel.com> References: <20240708193336.1192217-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Kan Liang A non-0 retire latency can be observed on a Raptorlake which doesn't support the retire latency feature. By design, the retire latency shares the PERF_SAMPLE_WEIGHT_STRUCT sample type with other types of latency. That could avoid adding too many different sample types to support all kinds of latency. For the machine which doesn't support some kind of latency, 0 should be returned. Perf doesn=E2=80=99t clear/init all the fields of a sample data for the sake of performance. It expects the later perf_{prepare,output}_sample() to update the uninitialized field. However, the current implementation doesn't touch the field of the retire latency if the feature is not supported. The memory garbage is dumped into the perf data. Clear the retire latency if the feature is not supported. Fixes: c87a31093c70 ("perf/x86: Support Retire Latency") Reported-by: "Bayduraev, Alexey V" Tested-by: "Bayduraev, Alexey V" Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/intel/ds.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index b9cc520b2942..fa5ea65de0d0 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1944,8 +1944,12 @@ static void setup_pebs_adaptive_sample_data(struct p= erf_event *event, set_linear_ip(regs, basic->ip); regs->flags =3D PERF_EFLAGS_EXACT; =20 - if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_= RETIRE_LATENCY)) - data->weight.var3_w =3D format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS= _LATENCY_MASK; + if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) { + if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY) + data->weight.var3_w =3D format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEB= S_LATENCY_MASK; + else + data->weight.var3_w =3D 0; + } =20 /* * The record for MEMINFO is in front of GP --=20 2.38.1