From nobody Sun Feb 8 07:38:19 2026 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6520B38FB0; Mon, 8 Jul 2024 08:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428095; cv=none; b=WVkyh8lck18ntuqhwnDrktn89YO4nIE1+OOaJSmECWjfd4RVuCws7ayzAzew56zH+yr/Toxbx9mdk9o62/GIv24g3PSYRhM658I4CKA2Kthqh6pgLMcbNosTv/y/ce5x0yUHPVdy8phDjJrYPzjLhBtJTZcBBrQ2938whHK0P0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428095; c=relaxed/simple; bh=OlqDzkICZh/rXle1yN3cbMo0i3pUWIT0ry1t2Or0OBE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bzBB3Z6tFNKhnrfdcNyEJ6g+mdDjTZoE+fHuKSlxSqHwmWNTJvz+jZjLp/SXsBo1wiWTuhNBtCNwmmn8/d3+z6kLcufQEtCTI6mmsbpumg7+U9XHsdjo1kkm3wuldhigGRajC8fI/GITkUVzQWLaJ9MjmgO5HYUSwEZYE6jyKeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=Mdvazh3a; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="Mdvazh3a" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 0FA9DBFB4D; Mon, 8 Jul 2024 10:41:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1720428086; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=8b9WEdH6nX/uhqStbhCkxjbUTBocln+2zCJ0wjlz2TM=; b=Mdvazh3as5WxPvN2jOz6c7pNkuYrl00UjJ8Xt4UlUDINGARD/zK1yFD7tFfH1V8oRmNzOW 9J6lBuVIfboFtllMmf+D6/tCkeNfK6aNQqlKfM8P3c2n9QMPdrlLkQsNbwaLGHzfRK8/ND mqVnTgkENTszZAPB3C73dUKZbUh8qLrOuFz9KjwJMqvDA0azx+TWNrjZAVeM5l9pDQqzz+ Yur5ZeoEW9LKud5jkhL2P3ylAeYS/Km5qvdfl6u+ZhL77Zb23XRDqv8P0lATdnYoXm2Lb6 jLD55CCtRNYwCUmZiuZXTtl6QBpTmRLM5bMlg5nJ/VjXLjR+EDm7eGQ4rMFK4A== From: Frieder Schrempf To: Bartosz Golaszewski , Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Stefan Agner Cc: Frieder Schrempf , Bartosz Golaszewski , Krzysztof Kozlowski , Peng Fan Subject: [PATCH v2 1/5] dt-bindings: gpio: vf610: Allow gpio-line-names to be set Date: Mon, 8 Jul 2024 10:40:31 +0200 Message-ID: <20240708084107.38986-2-frieder@fris.de> In-Reply-To: <20240708084107.38986-1-frieder@fris.de> References: <20240708084107.38986-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Describe common "gpio-line-names" property to allow DTs to specify names for GPIO lines. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes for v2: * change commit message (remove non-existing warning) * add minItems and maxItems --- Documentation/devicetree/bindings/gpio/gpio-vf610.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Docum= entation/devicetree/bindings/gpio/gpio-vf610.yaml index a27f929502575..cabda2eab4a23 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml @@ -51,6 +51,10 @@ properties: =20 gpio-controller: true =20 + gpio-line-names: + minItems: 1 + maxItems: 32 + clocks: items: - description: SoC GPIO clock --=20 2.45.2 From nobody Sun Feb 8 07:38:19 2026 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EEC33B290; Mon, 8 Jul 2024 08:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428096; cv=none; b=hN+wl/TbkCGHTsPR3fbUbZQHRo07qHhe48VRUsFgaljv0t5jfx/oV0h9WdqochQWugtkFnyWBYpKogakvO0FgqtBKwRP2mjU6u5zhQtDEZVqjothmAI1AcDKseER4qrdJnMcflYkuL+ldqa7Qwoh6HQPTt63pXbeTopbXEccFeA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428096; c=relaxed/simple; bh=2cglFmVz1Xpw1R2sFVulz1T3QnWmHmbSEE+yMLLZFoA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HBHczwk9hUjlrdHPhjH2AZlpnLquhddRlOCWZ+Bgrkqyycwnhzuv0qF2KTgX13w1virHbuYN55cwjAdISsGUcJizLiey47dsi/Q+PzBRVyYihcF9wRX+rotYyQe1OVAMq2xJvm0vl5afjG7SOXvl5tcKERwHQrBbKKpFUVt2nvE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=SLV7V94N; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="SLV7V94N" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3F9AEBFBA8; Mon, 8 Jul 2024 10:41:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1720428087; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=D9oTaUMXzjcTo6Wf10s0ulRO2OkpFnNvTpduNNFrDRM=; b=SLV7V94NOqUs3KUx9onVyY3+nteYPa0rymNGgqQumEOUBCH7E0zxK0Dc+y05kqDsOk37f+ 4AwNiHgAA/E80SyJv5B4FkqQ+Sb+8sJR9SyGVQA1+NPUR9LGJ6ap7Wvj2XLSsHQnprq53v cKLtGrFMd8SIKZwhu5Jf8WO/0FRpAbEEBN2N1zdQ6lWrbQfxweInyO3Tmh8EaCRjcdkWQ9 V/A6toWTj2SC1aPgNmXwtmDuLTIpPN4ftVibzBgNe8gUtBp+oOAGRrj0DLXNn2t3cJca63 hH38D6yWArP/y3asGeFcuAQGCee4g3QftsfSPzZUTdIXEHdJFasZel+FgnEg6w== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , Liam Girdwood , linux-kernel@vger.kernel.org, Mark Brown , Rob Herring , Robin Gong Cc: Frieder Schrempf , Joy Zou , Krzysztof Kozlowski Subject: [PATCH v2 2/5] dt-bindings: regulator: pca9450: Make interrupt optional Date: Mon, 8 Jul 2024 10:40:32 +0200 Message-ID: <20240708084107.38986-3-frieder@fris.de> In-Reply-To: <20240708084107.38986-1-frieder@fris.de> References: <20240708084107.38986-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The interrupt is optional in hardware and not connected on some boards. Make it optional in the binding. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes for v2: * improve commit message --- .../devicetree/bindings/regulator/nxp,pca9450-regulator.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regula= tor.yaml b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulato= r.yaml index 849bfa50bdbab..f8057bba747a5 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml @@ -96,7 +96,6 @@ properties: required: - compatible - reg - - interrupts - regulators =20 additionalProperties: false --=20 2.45.2 From nobody Sun Feb 8 07:38:19 2026 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DBAA50276; Mon, 8 Jul 2024 08:41:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428098; cv=none; b=TCsLRETAGKh6BEtgsPMKqYGWfcRgDYJQiZneQl8IlfTqHS7U5eqzuNcsbU+dXwKoYGfy7llyepTUM7HZJTPEkxrm38I/8FTkFax3NvSdGJM2iFOHyghnLZeJURQ9EpFlY0Z04LsRW9JMRXtnYscEg4T3uQ7qusy09xirgClS1hI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428098; c=relaxed/simple; bh=VDC1D0H6FRPHVF2lVtnTQz7uJqjeGfJhvGsyEQA9a+Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jf6zF5zTlNI58OQMq1eaSqX/f3paXBsWkIFSZQVlAIqSg9r1E1TK6G1Qr1puvole/Hl8nRZykI6C5SL3tpPIym9yZ9TiBR8l70jwbsU7Vq5GVbktbmI8oV2kx4S9Ouh3bnngLIK76Kdb6ZDFFTPvfqMxvruLPZiY1SLsQd6ztUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=gRy4PEcO; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="gRy4PEcO" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 715A6BFBAB; Mon, 8 Jul 2024 10:41:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1720428088; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=YMcfbKShlC6yhIcdj/UB0uMGVB2w1gBHYsj3ySGDcHY=; b=gRy4PEcOremjDqhdsoBCrKVn9Uc6OnDETntMVeRK4k9Xse7D3Y6JNjW2qLzmWsj1hDU20F 0fV/ycC8DILLp8GzyJn11hABwPGHsaIMwcjBuFEymeAKEf3hhfx/s7+5x+8lMCjSuPrnMd jwpjjz6BVhGjK6YRwMW121cPCgA1Ws2KfPFXsPHv3YUYirQGJEPIWxFpHWhAIVU7M7UBfD j9TDnaMK4PYP5XQCVwnSgveLooNsm4NjX2Y6dc1xjgscMe2OqQNOrNFxyehJ4h3FLa5N9K SvWW265CmoFo5glgHuJC4lxc12OtfLKjw7/1Mbx8AS8Ao9zhAK+XSYav0nuGNQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , Shawn Guo Cc: Frieder Schrempf , Krzysztof Kozlowski , Alexander Stein , Bjorn Helgaas , Conor Dooley , Gregor Herburger , Hiago De Franco , Hugo Villeneuve , Joao Paulo Goncalves , Marco Felsch , Markus Niebel , Mathieu Othacehe , Tim Harvey Subject: [PATCH v2 3/5] dt-bindings: arm: fsl: Add Kontron i.MX93 OSM-S based boards Date: Mon, 8 Jul 2024 10:40:33 +0200 Message-ID: <20240708084107.38986-4-frieder@fris.de> In-Reply-To: <20240708084107.38986-1-frieder@fris.de> References: <20240708084107.38986-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Add the bindings for the Kontron i.MX93 OSM-S SoM and BL carrier board. Signed-off-by: Frieder Schrempf Acked-by: Krzysztof Kozlowski --- Changes for v2: * add tag from Krzysztof (thanks!) --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 6d185d09cb6ae..5fa1494435011 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1318,6 +1318,12 @@ properties: - const: variscite,var-som-mx93 - const: fsl,imx93 =20 + - description: Kontron OSM-S i.MX93 SoM based boards + items: + - const: kontron,imx93-bl-osm-s # Kontron BL i.MX93 OSM-S board + - const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings =20 --=20 2.45.2 From nobody Sun Feb 8 07:38:19 2026 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE8842033A for ; Mon, 8 Jul 2024 08:41:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428095; cv=none; b=ti2lBZZgciscqGQiIHRu4DZiFi4MJCssHgbn4UcyPOfhqgbDSH6qdb8BK7IXfJTHIku9h2H5TP3WXQafeE0joB7x1GqlJDNgs+IZy6qRgZ4N6ks7pwDCnDh/QLojHBy0/KaXF8ynYYDpInX7nU4hZdC9Fw6qsdX3l+DtoM7hRr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720428095; c=relaxed/simple; bh=p2rxEF5VMZjtICNyZJPHmhFLE1AycL7XT30yF4aoSrI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VOkG+6mx6ZFLx9jfZj/aUQ7VECaXSK02Tkin3r26i9ufv/p/YptIKZhil2o/wgF6+2B+mXteCrPOCXUm2RSloFgav3zUvHUHmvzGLRg+BXLVXjWhpu8xQnC8FQIpW8u3ugfpbJFfcwoVuXunp+cGH4fQp6//4HYM3aHwx8N8F1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b=gFwAX/Il; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="gFwAX/Il" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 67B0BBFBAD; Mon, 8 Jul 2024 10:41:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1720428090; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Bie3S+NRtQsHAbGNnD72XIrDGSrQyPJe4739teujuCY=; b=gFwAX/IlJ/OIRFFh7HeljCxmKKXyLq/p50urW+HdWGK20Q/9ie59qwOyWue2L4WvZ3UypY ddsTNmyQRcr0R96zvA/paTezwWxsr6DKWH4Fe7BXnw6m5Q5MvIh3JGMCGuUrVZf8Zu+s1B XnsZ4ZABy1OsurU/rscboX5yFBRU/ot2cujdkVgNncR67jHMeS+lG8CCOdFt4FJwDElPfu 1LX7YbCoVBjv4BsiMy4qGQ2Qt/gCBKhOknc64oqbFJpJ1wuxQ+8NmFBWJPKYavnJ1umq9j hvxYwx6YcCpJxDxS+BIZQUPHhAqlCH/4Chd79rSyGh+r6i7m27H1CICs9h8RTw== From: Frieder Schrempf To: Liam Girdwood , linux-kernel@vger.kernel.org, Mark Brown Cc: Frieder Schrempf , Bo Liu , Joy Zou , Rob Herring Subject: [PATCH v2 4/5] regulator: pca9450: Make IRQ optional Date: Mon, 8 Jul 2024 10:40:34 +0200 Message-ID: <20240708084107.38986-5-frieder@fris.de> In-Reply-To: <20240708084107.38986-1-frieder@fris.de> References: <20240708084107.38986-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The IRQ line might not be connected on some boards. Allow the driver to be probed without it. Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- drivers/regulator/pca9450-regulator.c | 41 +++++++++++++-------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/regulator/pca9450-regulator.c b/drivers/regulator/pca9= 450-regulator.c index be488c5dff140..9714afe347dcc 100644 --- a/drivers/regulator/pca9450-regulator.c +++ b/drivers/regulator/pca9450-regulator.c @@ -891,11 +891,6 @@ static int pca9450_i2c_probe(struct i2c_client *i2c) unsigned int reset_ctrl; int ret; =20 - if (!i2c->irq) { - dev_err(&i2c->dev, "No IRQ configured?\n"); - return -EINVAL; - } - pca9450 =3D devm_kzalloc(&i2c->dev, sizeof(struct pca9450), GFP_KERNEL); if (!pca9450) return -ENOMEM; @@ -967,23 +962,25 @@ static int pca9450_i2c_probe(struct i2c_client *i2c) } } =20 - ret =3D devm_request_threaded_irq(pca9450->dev, pca9450->irq, NULL, - pca9450_irq_handler, - (IRQF_TRIGGER_FALLING | IRQF_ONESHOT), - "pca9450-irq", pca9450); - if (ret !=3D 0) { - dev_err(pca9450->dev, "Failed to request IRQ: %d\n", - pca9450->irq); - return ret; - } - /* Unmask all interrupt except PWRON/WDOG/RSVD */ - ret =3D regmap_update_bits(pca9450->regmap, PCA9450_REG_INT1_MSK, - IRQ_VR_FLT1 | IRQ_VR_FLT2 | IRQ_LOWVSYS | - IRQ_THERM_105 | IRQ_THERM_125, - IRQ_PWRON | IRQ_WDOGB | IRQ_RSVD); - if (ret) { - dev_err(&i2c->dev, "Unmask irq error\n"); - return ret; + if (pca9450->irq) { + ret =3D devm_request_threaded_irq(pca9450->dev, pca9450->irq, NULL, + pca9450_irq_handler, + (IRQF_TRIGGER_FALLING | IRQF_ONESHOT), + "pca9450-irq", pca9450); + if (ret !=3D 0) { + dev_err(pca9450->dev, "Failed to request IRQ: %d\n", + pca9450->irq); + return ret; + } + /* Unmask all interrupt except PWRON/WDOG/RSVD */ + ret =3D regmap_update_bits(pca9450->regmap, PCA9450_REG_INT1_MSK, + IRQ_VR_FLT1 | IRQ_VR_FLT2 | IRQ_LOWVSYS | + IRQ_THERM_105 | IRQ_THERM_125, + IRQ_PWRON | IRQ_WDOGB | IRQ_RSVD); + if (ret) { + dev_err(&i2c->dev, "Unmask irq error\n"); + return ret; + } } =20 /* Clear PRESET_EN bit in BUCK123_DVS to use DVS registers */ --=20 2.45.2 From nobody Sun Feb 8 07:38:19 2026 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD39768EF; 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arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fris.de header.i=@fris.de header.b="GzgDePPF" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4C515BFBA8; Mon, 8 Jul 2024 10:41:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1720428098; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=j5c5NEwfDCzcK+X3ChRiJgZPE2mtbL8FXY+gGQit6RM=; b=GzgDePPFKTrXZFr9oB/XNmOhfohjIkzvVirfcaJCsP05D/EboROXB4qd++azMIyd2eLDhx Ppg6sR/lHSPu1dLtybzJ+jeN9KfllIfMfrIV6Kwn2MwGAxc/7SoTDqsAJSjitnjwCyAgB6 2wLEe3gRimhANOezQdMscWMJBaSOJsFZAESwTzLWXA7SwF4ZV0x3JHMC61SALGNUkm92pz m5RU2w2D2gsecj8cp0H7Dow0vD2pbLk91rk+iPcMMEqV5RU9f0oGNCBwLnEvVB2FhnKute zBw0fG4gN5MX49zE9OKbUUygnc4s4dkmvvTUak+Rx9uDaiRwmu5wYEy7wR6ciQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Alexander Stein , Fabio Estevam , Gregor Herburger , Hugo Villeneuve , Joao Paulo Goncalves , Pengutronix Kernel Team , Tim Harvey Subject: [PATCH v2 5/5] arm64: dts: Add support for Kontron i.MX93 OSM-S SoM and BL carrier board Date: Mon, 8 Jul 2024 10:40:35 +0200 Message-ID: <20240708084107.38986-6-frieder@fris.de> In-Reply-To: <20240708084107.38986-1-frieder@fris.de> References: <20240708084107.38986-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf This adds support for the Kontron Electronics OSM-S i.MX93 SoM and the matching baseboard BL i.MX93. The SoM hardware complies to the Open Standard Module (OSM) 1.1 specification, size S (https://sget.org/standards/osm). Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-kontron-bl-osm-s.dts | 165 ++++++ .../dts/freescale/imx93-kontron-osm-s.dtsi | 547 ++++++++++++++++++ 3 files changed, 713 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index bd443c2bc5a48..f848c4b69b000 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -232,6 +232,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arc= h/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts new file mode 100644 index 0000000000000..2dfa2381f4691 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx93-kontron-osm-s.dtsi" + +/ { + model =3D "Kontron BL i.MX93 OSM-S"; + compatible =3D "kontron,imx93-bl-osm-s", "kontron,imx93-osm-s", "fsl,imx9= 3"; + + aliases { + ethernet0 =3D &fec; + ethernet1 =3D &eqos; + }; + + leds { + compatible =3D "gpio-leds"; + + led1 { + label =3D "led1"; + gpios =3D <&gpio2 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + pwm-beeper { + compatible =3D "pwm-beeper"; + pwms =3D <&tpm6 1 5000 0>; + }; + + reg_vcc_panel: regulator-vcc-panel { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 3 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VCC_PANEL"; + }; +}; + +&lpspi8 { + status =3D "okay"; + assigned-clocks =3D <&clk IMX93_CLK_LPSPI8>; + assigned-clock-parents =3D <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates =3D <100000000>; + + eeram@0 { + compatible =3D "microchip,48l640"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + }; +}; + +&eqos { /* Second ethernet (OSM-S ETH_B) */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_rgmii>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy1>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-id4f51.e91b"; + reg =3D <1>; + reset-assert-us =3D <10000>; + reset-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fec { /* First ethernet (OSM-S ETH_A) */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_enet_rgmii>; + phy-connection-type =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-id4f51.e91b"; + reg =3D <1>; + reset-assert-us =3D <10000>; + reset-gpios =3D <&gpio2 18 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&flexcan1 { + status =3D "okay"; +}; + +&lpi2c2 { + status =3D "okay"; + + gpio_expander_dio: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN", + "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN"; + interrupt-parent =3D <&gpio4>; + interrupts =3D <28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio2 2 GPIO_ACTIVE_LOW>; + }; +}; + +&lpuart1 { + status =3D "okay"; +}; + +&lpuart7 { + uart-has-rtscts; + status =3D "okay"; +}; + +&lpuart6 { + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status =3D "okay"; +}; + +&tpm6 { + status =3D "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode =3D "host"; + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb1@1 { + compatible =3D "usb424,2514"; + reg =3D <1>; + }; +}; + +&usbotg2 { + adp-disable; + hnp-disable; + srp-disable; + + disable-over-current; + dr_mode =3D "otg"; + usb-role-switch; + status =3D "okay"; +}; + +&usdhc2 { + vmmc-supply =3D <®_vdd_3v3>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/= arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi new file mode 100644 index 0000000000000..926c622d380ee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Kontron Electronics GmbH + */ + +#include +#include "imx93.dtsi" + +/ { + model =3D "Kontron OSM-S i.MX93"; + compatible =3D "kontron,imx93-osm-s", "fsl,imx93"; + + aliases { + rtc0 =3D &rv3028; + rtc1 =3D &bbnsm_rtc; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "VCC_SDIO_A"; + }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_vdd_carrier>; + enable-active-high; + gpio =3D <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name =3D "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; +}; + +&lpspi1 { /* OSM-S SPI_A */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi1>; + cs-gpios =3D <&gpio1 11 GPIO_ACTIVE_LOW>; +}; + +&lpspi8 { /* OSM-S SPI_B */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi8>; + cs-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&flexcan1 { /* OSM-S CAN_A */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; +}; + +&flexcan2 { /* OSM-S CAN_B */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio1>; + gpio-line-names =3D "", "", "I2C_A_SCL", "I2C_A_SDA", + "UART_CON_RX", "UART_CON_TX", "UART_C_RX", "UART_C_TX", + "CAN_A_TX", "CAN_A_RX", "GPIO_A_0", "SPI_A_CS0", + "SPI_A_SDI", "SPI_A_SCK","SPI_A_SDO"; +}; + +&gpio2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio2>; + gpio-line-names =3D "I2C_B_SDA", "I2C_B_SCL", "GPIO_B_1", "GPIO_A_2", + "UART_B_TX", "UART_B_RX", "UART_B_RTS", "UART_B_CTS", + "UART_A_TX", "UART_A_RX", "UART_A_RTS", "UART_A_CTS", + "SPI_B_CS0", "SPI_B_SDI", "SPI_B_SDO", "SPI_B_SCK", + "I2S_BITCLK", "I2S_MCLK", "GPIO_A_1", "I2S_A_DATA_OUT", + "I2S_A_DATA_IN", "PWM_2", "GPIO_A_3", "PWM_1", + "PWM_0", "CAN_B_TX", "I2S_LRCLK", "CAN_B_RX", "GPIO_A_4", + "GPIO_A_5"; +}; + +&gpio3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio3>; + gpio-line-names =3D "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_B_CLK", "SDIO_B_CMD", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "GPIO_A_6", "GPIO_A_7"; +}; + +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + gpio-line-names =3D "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD4", "ETH_B_TXD3", + "ETH_B_TXD2", "ETH_B_TXD1", "ETH_B_TX_EN", "ETH_B_TX_CLK", + "ETH_B_RX_CTL", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", + "ETH_B_RXD2", "ETH_B_RXD3", "ETH_MDC", "ETH_MDIO", + "ETH_A_TXD3", "ETH_A_TXD2", "ETH_A_TXD1", "ETH_A_TXD0", + "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH_A_RX_CTL", "ETH_A_RX_CLK", + "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3", + "GPIO_B_0", "CARRIER_PWR_EN"; +}; + +&lpi2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + status =3D "okay"; + + pca9451: pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + nxp,i2c-lt-enable; + + regulators { + reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */ + regulator-name =3D "+0V8_VDD_SOC (BUCK1)"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + reg_vddq_ddr: BUCK2 { + regulator-name =3D "+0V6_VDDQ_DDR (BUCK2)"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name =3D "+3V3 (BUCK4)"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name =3D "+1V8 (BUCK5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name =3D "+1V1_NVCC_DRAM (BUCK6)"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name =3D "+1V8_NVCC_SNVS (LDO1)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_ana: LDO4 { + regulator-name =3D "+0V8_VDD_ANA (LDO4)"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name =3D "NVCC_SD (LDO5)"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + }; + + eeprom@50 { + compatible =3D "onnn,n24s64b", "atmel,24c64"; + reg =3D <0x50>; + pagesize =3D <32>; + size =3D <8192>; + num-addresses =3D <1>; + }; + + rv3028: rtc@52 { + compatible =3D "microcrystal,rv3028"; + reg =3D <0x52>; + }; +}; + +&lpi2c2 { /* OSM-S I2C_A */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpi2c2>; +}; + +&lpi2c3 { /* OSM-S I2C_B */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; +}; + +&tpm3 { /* OSM-S PWM_0 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm3>; +}; + +&tpm4 { /* OSM-S PWM_2 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm4>; +}; + +&tpm6 { /* OSM-S PWM_1 */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm6>; +}; + +&lpuart1 { /* OSM-S UART_CON */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart1>; +}; + +&lpuart2 { /* OSM-S UART_C */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart2>; +}; + +&lpuart6 { /* OSM-S UART_B */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart6>; +}; + +&lpuart7 { /* OSM-S UART_A */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart7>; +}; + +&usdhc1 { /* eMMC */ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_vdd_1v8>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&usdhc2 { /* OSM-S SDIO_A */ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + vmmc-supply =3D <®_usdhc2_vcc>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { /* OSM-S SDIO_B */ + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3>; + pinctrl-2 =3D <&pinctrl_usdhc3>; + vqmmc-supply =3D <®_vdd_1v8>; +}; + +&wdog3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_lpspi1: lpspi1grp { + fsl,pins =3D < + MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x3fe /* SPI_A_SDI_(IO0) */ + MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x3fe /* SPI_A_SDO_(IO1) */ + MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x3fe /* SPI_A_SCK */ + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x3fe /* SPI_A_CS0# */ + >; + }; + + pinctrl_lpspi8: lpspi8grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x3fe /* SPI_B_SDI */ + MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x3fe /* SPI_B_SDO */ + MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x3fe /* SPI_B_SCK */ + MX93_PAD_GPIO_IO12__GPIO2_IO12 0x3fe /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins =3D < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e /* ETH_MDC */ + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e /* ETH_MDIO */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e /* ETH_A_(R)(G)MII_RXD2 */ + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e /* ETH_A_(R)(G)MII_RXD3 */ + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe /* ETH_A_(R)(G)MII_RX_CLK */ + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e /* ETH_A_(R)(G)MII_RX_D= V(_ER) */ + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe /* ETH_A_(R)(G)MII_TX_CLK */ + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e /* ETH_A_(R)(G)MII_TX_E= N(_ER) */ + >; + }; + + pinctrl_eqos_rgmii: eqosrgmiigrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e /* ETH_B_MDC */ + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e /* ETH_B_MDIO */ + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e /* ETH_B_(S)(R)(G)MII_RXD= 0 */ + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e /* ETH_B_(S)(R)(G)MII_RXD= 1 */ + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e /* ETH_B_(R)(G)MII_RXD2 */ + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e /* ETH_B_(R)(G)MII_RXD3 */ + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x57e /* ETH_B_(= R)(G)MII_RX_CLK */ + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e /* ETH_B_(R)(G)MII_R= X_DV(_ER) */ + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e /* ETH_B_(S)(R)(G)MII_TXD= 0 */ + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e /* ETH_B_(S)(R)(G)MII_TXD= 1 */ + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e /* ETH_B_(S)(R)(G)MII_TXD= 2 */ + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e /* ETH_B_(S)(R)(G)MII_TXD= 3 */ + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x57e /* ETH_B_(= R)(G)MII_TX_CLK */ + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e /* ETH_B_(R)(G)MII_T= X_EN(_ER) */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e /* CAN_A_TX */ + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e /* CAN_A_RX */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e /* CAN_B_TX */ + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e /* CAN_B_RX */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins =3D < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e /* GPIO_A_0 */ + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e /* GPIO_A_1 */ + MX93_PAD_GPIO_IO03__GPIO2_IO03 0x31e /* GPIO_A_2 */ + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* GPIO_A_3 */ + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e /* GPIO_A_4 */ + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e /* GPIO_A_5 */ + MX93_PAD_GPIO_IO02__GPIO2_IO02 0x31e /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e /* GPIO_A_6 */ + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e /* GPIO_A_7 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x31e /* GPIO_B_0 */ + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e /* I2C_A_SCL */ + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e /* I2C_A_SDA */ + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e /* I2C_B_SCL */ + MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e /* I2C_B_SDA */ + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO24__TPM3_CH3 0x57e /* PWM_0 */ + >; + }; + + pinctrl_tpm4: tpm4grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO21__TPM4_CH1 0x57e /* PWM_2 */ + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO23__TPM6_CH1 0x57e /* PWM_1 */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins =3D < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins =3D < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* CARRIER_PWR_EN */ + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */ + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e /* I2S_A_DATA_OUT */ + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e /* I2S_MCLK */ + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e /* I2S_LRCLK */ + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e /* I2S_BITCLK */ + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e /* UART_CON_RX */ + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e /* UART_CON_TX */ + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins =3D < + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e /* UART_C_RX */ + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e /* UART_C_TX */ + >; + }; + + pinctrl_lpuart6: lpuart6grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e /* UART_B_RX */ + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e /* UART_B_TX */ + MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e /* UART_B_CTS */ + MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e /* UART_B_RTS */ + >; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e /* UART_A_RX */ + MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e /* UART_A_TX */ + MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e /* UART_A_CTS */ + MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e /* UART_A_RTS */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe /* SDIO_A_CLK */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe /* SDIO_A_CMD */ + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe /* SDIO_A_D0 */ + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe /* SDIO_A_D1 */ + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe /* SDIO_A_D2 */ + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe /* SDIO_A_D3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe /* SDIO_B_CLK */ + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe /* SDIO_B_CMD */ + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe /* SDIO_B_D0 */ + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe /* SDIO_B_D1 */ + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe /* SDIO_B_D2 */ + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe /* SDIO_B_D3 */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0xc6 + >; + }; +}; --=20 2.45.2