From nobody Sun Feb 8 09:12:56 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71BED17C66 for ; Mon, 8 Jul 2024 06:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720419678; cv=none; b=SFF2gEKcE55cENFLU3t0OZPKJ/P0dOUaIGmDGbeOQzAYuQqzBpZt/Lr/vAVFu3E3uN0vF+KIkJ5wQTYqrMTAUYo2giuw8wkAlZpsl5aEw2hoqPKY0A/6EudHYSnQkETOYA6/NBNbUBCwZE7QziOBQ5e8c+C3YtwVSNNgMwn6Ars= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720419678; c=relaxed/simple; bh=dQ7NHtYtF6uL+Y/Gr/LXsMc+5eb5CNZYrkqWBRic5w8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=MdbEIQUbq42rbgvrqinpVxzPDqLAfinpqh37sEh75zQlTBlgDuIPISp1+FmLr/GEkUtLfW9PCFxxcBflkz6J9T0jMcHpQuuxZUpgrFQHCPLDm0pivEbrpN+UUe+cnNMfSdjCvqgpVR4MwtrSDJrKHLCrWtnrS7CwylW6g9WC99Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--aniketmaurya.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=S+G5Y+Ha; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--aniketmaurya.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="S+G5Y+Ha" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-1fb1c206242so18695185ad.3 for ; Sun, 07 Jul 2024 23:21:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1720419677; x=1721024477; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=JBFBYt9OaLc4OX3uBfAr6G8BybiHmWegQe0q6D9D5b0=; b=S+G5Y+HacGwWj40SGkGOeKayZneXtDJTthOFxgW2tsqQoU/8mVP8vubGC/ifHtDVZq EXcbntiBmyoiefU9/YlnK27s+lLhUTdzAIK+RfoTkNyA3VaFOxEOM/PGI9Lphvxvh+qk h+o/tbUdHqoMih8ddad04cABMJxBnhodUgvcI/WsDo0Ys5jMkYS8Lt2Dq6edUWuKpvGl 5dokQUlhk3phD+ajF5WyonBD6XqSbw+EFtkezJ/LsNfKlXzoANtSnt0F0bR0La8Ifyiu kMEX5VOUk+zvqW13KxVljvDV4Lj01zibBQ7jxxLS2VFD0i/9Ufn+vwXF7QsfYSZbTiJf Vjww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1720419677; x=1721024477; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JBFBYt9OaLc4OX3uBfAr6G8BybiHmWegQe0q6D9D5b0=; b=tKQzXVj6CMaCP19JLM02hXmB9GbfBgyZLHm71cNoYp1k78vR6TW+kwWS+a4wv+Lpez x5hGSId6l0z21qGUWBCjYpjbltvhLg3j0YY0dS2L6xcfRGSgIVeJTWRdo/jTnppmmoFO AnfNXrZ6SbCCVjEDsbRdhFt437Y4TD2C35vcZs2xAitBXiERUtDOI0eWcnHraON/RhrS 5joZaTGOV/2L/g9YIZhQ81yx+YHfjViINJObv8HJWAx2SHXW8IOZMRkS9GhUZ9nNpDl/ iNiulacCkWpz9QH47+dpF4xpt1nVEyJJK7xtmoQaXVUNwM/A5E1HZ48IuZIKt+zirC6j tyGw== X-Forwarded-Encrypted: i=1; AJvYcCWczAVzeu8EDUdN2CHXD8vZF4I9CCLPbPGBeXIaCjgHsFvkHug/UWxooY5rtvWTnd+Zjrp1XRy9/1ACUahWObW+W59Ng4HlN204kHi2 X-Gm-Message-State: AOJu0Yy0owuhjSZY7mg28RNtcjHM9Oc2eHOAlr6nx8HRCapPedCq60ff kWxLqUvjUDwvWF78gc1NZW9aEGRGneYBEjaMhbBhvAGVETvkxmheYfvcqQMC4flm6H9ldjH+jGN 1lS1x3YYMfz2d9sgnBNJHtFQd0A== X-Google-Smtp-Source: AGHT+IGyxOofX5NtXwiv3RmzLQfz6C1YmxhTYd83aKt2ToUFb9JlL8B+I57wHdB8sG8W04bkwT3WNR5Ztv9XE9uNrHM= X-Received: from aniketm.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:3387]) (user=aniketmaurya job=sendgmr) by 2002:a17:902:c404:b0:1f7:3763:5ff0 with SMTP id d9443c01a7336-1fb33e3d924mr6890585ad.1.1720419676561; Sun, 07 Jul 2024 23:21:16 -0700 (PDT) Date: Mon, 8 Jul 2024 06:21:01 +0000 In-Reply-To: <20240708062103.3296587-1-aniketmaurya@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240708062103.3296587-1-aniketmaurya@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240708062103.3296587-2-aniketmaurya@google.com> Subject: [PATCH 1/3] i3c: dw: Save timing registers and other values From: Aniket To: Alexandre Belloni , Jeremy Kerr , Joel Stanley , Billy Tsai Cc: linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, vamshigajjela@google.com, Aniket Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add variables to store timing registers and other values. These variables would be later used to restore registers during resume without recomputation. Signed-off-by: Aniket --- drivers/i3c/master/dw-i3c-master.c | 15 +++++++++++++-- drivers/i3c/master/dw-i3c-master.h | 9 +++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 0ca41782f3a6..fcfa37f55d86 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -543,18 +543,22 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *maste= r) =20 scl_timing =3D SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); + master->i3c_pp_timing =3D scl_timing; =20 /* * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this * will be set up by dw_i2c_clk_cfg as tLOW. */ - if (master->base.bus.mode =3D=3D I3C_BUS_MODE_PURE) + if (master->base.bus.mode =3D=3D I3C_BUS_MODE_PURE) { writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); + master->bus_free_timing =3D BUS_I3C_MST_FREE(lcnt); + } =20 lcnt =3D max_t(u8, DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); scl_timing =3D SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); + master->i3c_od_timing =3D scl_timing; =20 lcnt =3D DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; scl_timing =3D SCL_EXT_LCNT_1(lcnt); @@ -565,6 +569,7 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master) lcnt =3D DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; scl_timing |=3D SCL_EXT_LCNT_4(lcnt); writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); + master->ext_lcnt_timing =3D scl_timing; =20 return 0; } @@ -586,16 +591,21 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *maste= r) scl_timing =3D SCL_I2C_FMP_TIMING_HCNT(hcnt) | SCL_I2C_FMP_TIMING_LCNT(lcnt); writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); + master->i2c_fmp_timing =3D scl_timing; =20 lcnt =3D DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); hcnt =3D DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt; scl_timing =3D SCL_I2C_FM_TIMING_HCNT(hcnt) | SCL_I2C_FM_TIMING_LCNT(lcnt); writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); + master->i2c_fm_timing =3D scl_timing; =20 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); + master->bus_free_timing =3D BUS_I3C_MST_FREE(lcnt); + writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, master->regs + DEVICE_CTRL); + master->i2c_slv_prsnt =3D true; =20 return 0; } @@ -650,7 +660,7 @@ static int dw_i3c_master_bus_init(struct i3c_master_con= troller *m) =20 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), master->regs + DEVICE_ADDR); - + master->dev_addr =3D ret; memset(&info, 0, sizeof(info)); info.dyn_addr =3D ret; =20 @@ -1077,6 +1087,7 @@ static int dw_i3c_master_attach_i2c_dev(struct i2c_de= v_desc *dev) =20 data->index =3D pos; master->devs[pos].addr =3D dev->addr; + master->devs[pos].is_i2c_addr =3D true; master->free_pos &=3D ~BIT(pos); i2c_dev_set_master_data(dev, data); =20 diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c= -master.h index fb7121c6c687..f23e9d5aca86 100644 --- a/drivers/i3c/master/dw-i3c-master.h +++ b/drivers/i3c/master/dw-i3c-master.h @@ -19,6 +19,7 @@ struct dw_i3c_master_caps { =20 struct dw_i3c_dat_entry { u8 addr; + bool is_i2c_addr; struct i3c_dev_desc *ibi_dev; }; =20 @@ -40,6 +41,14 @@ struct dw_i3c_master { char version[5]; char type[5]; u32 sir_rej_mask; + bool i2c_slv_prsnt; + u32 dev_addr; + u32 i3c_pp_timing; + u32 i3c_od_timing; + u32 ext_lcnt_timing; + u32 bus_free_timing; + u32 i2c_fm_timing; + u32 i2c_fmp_timing; /* * Per-device hardware data, used to manage the device address table * (DAT) --=20 2.45.2.803.g4e1b14247a-goog From nobody Sun Feb 8 09:12:56 2026 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3873B1B948 for ; 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Sun, 07 Jul 2024 23:21:21 -0700 (PDT) Date: Mon, 8 Jul 2024 06:21:02 +0000 In-Reply-To: <20240708062103.3296587-1-aniketmaurya@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240708062103.3296587-1-aniketmaurya@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240708062103.3296587-3-aniketmaurya@google.com> Subject: [PATCH 2/3] i3c: dw: Add some functions for reusability From: Aniket To: Alexandre Belloni , Jeremy Kerr , Joel Stanley , Billy Tsai Cc: linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, vamshigajjela@google.com, Aniket Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Separate logic for setting intr/thld registers in a func. Also modify enable function to take care of setting all fields in DEVICE_CT= RL. These functions can be reused later for power management. Signed-off-by: Aniket --- drivers/i3c/master/dw-i3c-master.c | 62 +++++++++++++++++------------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index fcfa37f55d86..fadb58ac8b68 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -300,7 +300,14 @@ static void dw_i3c_master_disable(struct dw_i3c_master= *master) =20 static void dw_i3c_master_enable(struct dw_i3c_master *master) { - writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE, + u32 dev_ctrl; + + dev_ctrl =3D readl(master->regs + DEVICE_CTRL); + /* For now don't support Hot-Join */ + dev_ctrl |=3D DEV_CTRL_HOT_JOIN_NACK; + if (master->i2c_slv_prsnt) + dev_ctrl |=3D DEV_CTRL_I2C_SLAVE_PRESENT; + writel(dev_ctrl | DEV_CTRL_ENABLE, master->regs + DEVICE_CTRL); } =20 @@ -521,6 +528,32 @@ static void dw_i3c_master_end_xfer_locked(struct dw_i3= c_master *master, u32 isr) dw_i3c_master_start_xfer_locked(master); } =20 +static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) +{ + u32 thld_ctrl; + + thld_ctrl =3D readl(master->regs + QUEUE_THLD_CTRL); + thld_ctrl &=3D ~(QUEUE_THLD_CTRL_RESP_BUF_MASK | + QUEUE_THLD_CTRL_IBI_STAT_MASK | + QUEUE_THLD_CTRL_IBI_DATA_MASK); + thld_ctrl |=3D QUEUE_THLD_CTRL_IBI_STAT(1) | + QUEUE_THLD_CTRL_IBI_DATA(31); + writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); + + thld_ctrl =3D readl(master->regs + DATA_BUFFER_THLD_CTRL); + thld_ctrl &=3D ~DATA_BUFFER_THLD_CTRL_RX_BUF; + writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); + + writel(INTR_ALL, master->regs + INTR_STATUS); + writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); + writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); + + master->sir_rej_mask =3D IBI_REQ_REJECT_ALL; + writel(master->sir_rej_mask, master->regs + IBI_SIR_REQ_REJECT); + + writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); +} + static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { unsigned long core_rate, core_period; @@ -615,7 +648,6 @@ static int dw_i3c_master_bus_init(struct i3c_master_con= troller *m) struct dw_i3c_master *master =3D to_dw_i3c_master(m); struct i3c_bus *bus =3D i3c_master_get_bus(m); struct i3c_device_info info =3D { }; - u32 thld_ctrl; int ret; =20 ret =3D master->platform_ops->init(master); @@ -638,22 +670,6 @@ static int dw_i3c_master_bus_init(struct i3c_master_co= ntroller *m) return -EINVAL; } =20 - thld_ctrl =3D readl(master->regs + QUEUE_THLD_CTRL); - thld_ctrl &=3D ~(QUEUE_THLD_CTRL_RESP_BUF_MASK | - QUEUE_THLD_CTRL_IBI_STAT_MASK | - QUEUE_THLD_CTRL_IBI_DATA_MASK); - thld_ctrl |=3D QUEUE_THLD_CTRL_IBI_STAT(1) | - QUEUE_THLD_CTRL_IBI_DATA(31); - writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); - - thld_ctrl =3D readl(master->regs + DATA_BUFFER_THLD_CTRL); - thld_ctrl &=3D ~DATA_BUFFER_THLD_CTRL_RX_BUF; - writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); - - writel(INTR_ALL, master->regs + INTR_STATUS); - writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); - writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); 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Sun, 07 Jul 2024 23:21:25 -0700 (PDT) Date: Mon, 8 Jul 2024 06:21:03 +0000 In-Reply-To: <20240708062103.3296587-1-aniketmaurya@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240708062103.3296587-1-aniketmaurya@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240708062103.3296587-4-aniketmaurya@google.com> Subject: [PATCH 3/3] i3c: dw: Add power management support From: Aniket To: Alexandre Belloni , Jeremy Kerr , Joel Stanley , Billy Tsai Cc: linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, vamshigajjela@google.com, Aniket Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for runtime and system power management. Handle clocks, resets, pads as part of suspend and resume. Restore controller registers that could be lost due to suspend. Finally add get and put calls appropriately in functions which access controller : bus_init, do_daa, send_ccc_cmd, priv_xfers, i2c_xfers, ibi and hot-join. Signed-off-by: Aniket --- drivers/i3c/master/dw-i3c-master.c | 225 ++++++++++++++++++++++++++--- drivers/i3c/master/dw-i3c-master.h | 1 + 2 files changed, 209 insertions(+), 17 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index fadb58ac8b68..8d694672c110 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -17,7 +17,9 @@ #include #include #include +#include #include +#include #include #include =20 @@ -217,7 +219,7 @@ #define I3C_BUS_THIGH_MAX_NS 41 =20 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) - +#define RPM_AUTOSUSPEND_TIMEOUT 1000 /* ms */ struct dw_i3c_cmd { u32 cmd_lo; u32 cmd_hi; @@ -650,29 +652,38 @@ static int dw_i3c_master_bus_init(struct i3c_master_c= ontroller *m) struct i3c_device_info info =3D { }; int ret; =20 + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } + ret =3D master->platform_ops->init(master); if (ret) - return ret; + goto rpm_out; =20 switch (bus->mode) { case I3C_BUS_MODE_MIXED_FAST: case I3C_BUS_MODE_MIXED_LIMITED: ret =3D dw_i2c_clk_cfg(master); if (ret) - return ret; + goto rpm_out; fallthrough; case I3C_BUS_MODE_PURE: ret =3D dw_i3c_clk_cfg(master); if (ret) - return ret; + goto rpm_out; break; default: - return -EINVAL; + ret =3D -EINVAL; + goto rpm_out; } =20 ret =3D i3c_master_get_free_addr(m, 0); if (ret < 0) - return ret; + goto rpm_out; =20 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), master->regs + DEVICE_ADDR); @@ -682,12 +693,15 @@ static int dw_i3c_master_bus_init(struct i3c_master_c= ontroller *m) =20 ret =3D i3c_master_set_info(&master->base, &info); if (ret) - return ret; + goto rpm_out; =20 dw_i3c_master_set_intr_regs(master); dw_i3c_master_enable(master); =20 - return 0; +rpm_out: + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); + return ret; } =20 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) @@ -789,11 +803,21 @@ static int dw_i3c_master_send_ccc_cmd(struct i3c_mast= er_controller *m, if (ccc->id =3D=3D I3C_CCC_ENTDAA) return -EINVAL; =20 + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } + if (ccc->rnw) ret =3D dw_i3c_ccc_get(master, ccc); else ret =3D dw_i3c_ccc_set(master, ccc); =20 + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); return ret; } =20 @@ -806,6 +830,14 @@ static int dw_i3c_master_daa(struct i3c_master_control= ler *m) u8 p, last_addr =3D 0; int ret, pos; =20 + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } + olddevs =3D ~(master->free_pos); =20 /* Prepare DAT before launching DAA. */ @@ -814,8 +846,10 @@ static int dw_i3c_master_daa(struct i3c_master_control= ler *m) continue; =20 ret =3D i3c_master_get_free_addr(m, last_addr + 1); - if (ret < 0) - return -ENOSPC; + if (ret < 0) { + ret =3D -ENOSPC; + goto rpm_out; + } =20 master->devs[pos].addr =3D ret; p =3D even_parity(ret); @@ -825,16 +859,21 @@ static int dw_i3c_master_daa(struct i3c_master_contro= ller *m) writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); + + ret =3D 0; } =20 xfer =3D dw_i3c_master_alloc_xfer(master, 1); - if (!xfer) - return -ENOMEM; + if (!xfer) { + ret =3D -ENOMEM; + goto rpm_out; + } =20 pos =3D dw_i3c_master_get_free_pos(master); if (pos < 0) { dw_i3c_master_free_xfer(xfer); - return pos; + ret =3D pos; + goto rpm_out; } cmd =3D &xfer->cmds[0]; cmd->cmd_hi =3D 0x1; @@ -859,7 +898,10 @@ static int dw_i3c_master_daa(struct i3c_master_control= ler *m) =20 dw_i3c_master_free_xfer(xfer); =20 - return 0; +rpm_out: + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); + return ret; } =20 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, @@ -894,6 +936,14 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_des= c *dev, if (!xfer) return -ENOMEM; =20 + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } + for (i =3D 0; i < i3c_nxfers; i++) { struct dw_i3c_cmd *cmd =3D &xfer->cmds[i]; =20 @@ -935,6 +985,8 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_desc= *dev, ret =3D xfer->ret; dw_i3c_master_free_xfer(xfer); =20 + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); return ret; } =20 @@ -1045,6 +1097,14 @@ static int dw_i3c_master_i2c_xfers(struct i2c_dev_de= sc *dev, if (!xfer) return -ENOMEM; =20 + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } + for (i =3D 0; i < i2c_nxfers; i++) { struct dw_i3c_cmd *cmd =3D &xfer->cmds[i]; =20 @@ -1075,6 +1135,8 @@ static int dw_i3c_master_i2c_xfers(struct i2c_dev_des= c *dev, ret =3D xfer->ret; dw_i3c_master_free_xfer(xfer); =20 + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); return ret; } =20 @@ -1217,6 +1279,15 @@ static void dw_i3c_master_set_sir_enabled(struct dw_= i3c_master *master, static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m) { struct dw_i3c_master *master =3D to_dw_i3c_master(m); + int ret; + + ret =3D pm_runtime_resume_and_get(master->dev); + if (ret < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, ret); + return ret; + } =20 dw_i3c_master_enable_sir_signal(master, true); writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_HOT_JOIN_NACK, @@ -1232,6 +1303,8 @@ static int dw_i3c_master_disable_hotjoin(struct i3c_m= aster_controller *m) writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, master->regs + DEVICE_CTRL); =20 + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); return 0; } =20 @@ -1242,12 +1315,23 @@ static int dw_i3c_master_enable_ibi(struct i3c_dev_= desc *dev) struct dw_i3c_master *master =3D to_dw_i3c_master(m); int rc; =20 + rc =3D pm_runtime_resume_and_get(master->dev); + if (rc < 0) { + dev_err(master->dev, + "<%s> cannot resume i3c bus master, err: %d\n", + __func__, rc); + return rc; + } + dw_i3c_master_set_sir_enabled(master, dev, data->index, true); =20 rc =3D i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); =20 - if (rc) + if (rc) { dw_i3c_master_set_sir_enabled(master, dev, data->index, false); + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); + } =20 return rc; } @@ -1265,6 +1349,8 @@ static int dw_i3c_master_disable_ibi(struct i3c_dev_d= esc *dev) =20 dw_i3c_master_set_sir_enabled(master, dev, data->index, false); =20 + pm_runtime_mark_last_busy(master->dev); + pm_runtime_put_autosuspend(master->dev); return 0; } =20 @@ -1465,6 +1551,8 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, if (!master->platform_ops) master->platform_ops =3D &dw_i3c_platform_ops_default; =20 + master->dev =3D &pdev->dev; + master->regs =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(master->regs)) return PTR_ERR(master->regs); @@ -1497,6 +1585,11 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, =20 platform_set_drvdata(pdev, master); =20 + pm_runtime_set_autosuspend_delay(&pdev->dev, RPM_AUTOSUSPEND_TIMEOUT); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + /* Information regarding the FIFOs/QUEUEs depth */ ret =3D readl(master->regs + QUEUE_STATUS_LEVEL); master->caps.cmdfifodepth =3D QUEUE_STATUS_LEVEL_CMD(ret); @@ -1513,10 +1606,15 @@ int dw_i3c_common_probe(struct dw_i3c_master *maste= r, ret =3D i3c_master_register(&master->base, &pdev->dev, &dw_mipi_i3c_ops, false); if (ret) - goto err_assert_rst; + goto err_disable_pm; =20 return 0; =20 +err_disable_pm: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + err_assert_rst: reset_control_assert(master->core_rst); =20 @@ -1528,7 +1626,9 @@ void dw_i3c_common_remove(struct dw_i3c_master *maste= r) { i3c_master_unregister(&master->base); =20 - reset_control_assert(master->core_rst); + pm_runtime_disable(master->dev); + pm_runtime_set_suspended(master->dev); + pm_runtime_dont_use_autosuspend(master->dev); } EXPORT_SYMBOL_GPL(dw_i3c_common_remove); =20 @@ -1552,6 +1652,96 @@ static void dw_i3c_remove(struct platform_device *pd= ev) dw_i3c_common_remove(master); } =20 +static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master) +{ + u32 pos, reg_val; + + writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(master->dev_addr), + master->regs + DEVICE_ADDR); + + for (pos =3D 0; pos < master->maxdevs; pos++) { + if (master->free_pos & BIT(pos)) + continue; + + if (master->devs[pos].is_i2c_addr) + reg_val =3D DEV_ADDR_TABLE_LEGACY_I2C_DEV | + DEV_ADDR_TABLE_STATIC_ADDR(master->devs[pos].addr); + else + reg_val =3D DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr); + + writel(reg_val, master->regs + DEV_ADDR_TABLE_LOC(master->datstartaddr, = pos)); + } +} + +static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) +{ + writel(master->i3c_pp_timing, master->regs + SCL_I3C_PP_TIMING); + writel(master->bus_free_timing, master->regs + BUS_FREE_TIMING); + writel(master->i3c_od_timing, master->regs + SCL_I3C_OD_TIMING); + writel(master->ext_lcnt_timing, master->regs + SCL_EXT_LCNT_TIMING); + + if (master->i2c_slv_prsnt) { + writel(master->i2c_fmp_timing, master->regs + SCL_I2C_FMP_TIMING); + writel(master->i2c_fm_timing, master->regs + SCL_I2C_FM_TIMING); + } +} + +static int dw_i3c_master_enable_clks(struct dw_i3c_master *master) +{ + int ret =3D 0; + + ret =3D clk_prepare_enable(master->core_clk); + if (ret) + return ret; + + ret =3D clk_prepare_enable(master->pclk); + if (ret) { + clk_disable_unprepare(master->core_clk); + return ret; + } + + return 0; +} + +static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master) +{ + clk_disable_unprepare(master->pclk); + clk_disable_unprepare(master->core_clk); +} + +static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev) +{ + struct dw_i3c_master *master =3D dev_get_drvdata(dev); + + dw_i3c_master_disable(master); + + reset_control_assert(master->core_rst); + dw_i3c_master_disable_clks(master); + pinctrl_pm_select_sleep_state(dev); + return 0; +} + +static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev) +{ + struct dw_i3c_master *master =3D dev_get_drvdata(dev); + + pinctrl_pm_select_default_state(dev); + dw_i3c_master_enable_clks(master); + reset_control_deassert(master->core_rst); + + dw_i3c_master_set_intr_regs(master); + dw_i3c_master_restore_timing_regs(master); + dw_i3c_master_restore_addrs(master); + + dw_i3c_master_enable(master); + return 0; +} + +static const struct dev_pm_ops dw_i3c_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(dw_i3c_master_runtime_suspend, dw_i3c_master_runtime_r= esume, NULL) +}; + static const struct of_device_id dw_i3c_master_of_match[] =3D { { .compatible =3D "snps,dw-i3c-master-1.00a", }, {}, @@ -1564,6 +1754,7 @@ static struct platform_driver dw_i3c_driver =3D { .driver =3D { .name =3D "dw-i3c-master", .of_match_table =3D dw_i3c_master_of_match, + .pm =3D &dw_i3c_pm_ops, }, }; module_platform_driver(dw_i3c_driver); diff --git a/drivers/i3c/master/dw-i3c-master.h b/drivers/i3c/master/dw-i3c= -master.h index f23e9d5aca86..219ff815d3a7 100644 --- a/drivers/i3c/master/dw-i3c-master.h +++ b/drivers/i3c/master/dw-i3c-master.h @@ -25,6 +25,7 @@ struct dw_i3c_dat_entry { =20 struct dw_i3c_master { struct i3c_master_controller base; + struct device *dev; u16 maxdevs; u16 datstartaddr; u32 free_pos; --=20 2.45.2.803.g4e1b14247a-goog