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This simplifies the code. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 111 ++++++++++++++++--------------= ---- 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 47134e2dfecf2..dbcb70186036e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); + int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); }; =20 struct imx_pcie { @@ -585,21 +586,20 @@ static int imx_pcie_attach_pd(struct device *dev) return 0; } =20 -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) +static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enab= le) { - unsigned int offset; - int ret =3D 0; + if (enable) + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); =20 - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); - break; - case IMX6QP: - case IMX6Q: + return 0; +} + +static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enabl= e) +{ + if (enable) { /* power up core phy and enable ref clock */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TES= T_PD); /* * the async reset input need ref clock to sync internally, * when the ref clock comes after reset, internal synced @@ -607,55 +607,33 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *i= mx_pcie) * add one ~10us delay here. */ usleep_range(10, 100); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - break; - case IMX7D: - case IMX95: - case IMX95_EP: - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - offset =3D imx_pcie_grp_offset(imx_pcie); - /* - * Set the over ride low and enabled - * make sure that REF_CLK is turned on. - */ - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, - 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - break; + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_C= LK_EN); + } else { + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF= _CLK_EN); + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_= PD); } =20 - return ret; + return 0; } =20 -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) +static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enab= le) { - switch (imx_pcie->drvdata->variant) { - case IMX6QP: - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, - IMX6Q_GPR1_PCIE_TEST_PD); - break; - case IMX7D: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - default: - break; + int offset =3D imx_pcie_grp_offset(imx_pcie); + + if (enable) { + regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_= OVERRIDE); + regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OV= ERRIDE_EN); } + + return 0; +} + +static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enabl= e) +{ + if (!enable) + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + return 0; } =20 static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_p= cie) if (ret) return ret; =20 - ret =3D imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + if (imx_pcie->drvdata->enable_ref_clk) { + ret =3D imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); + if (ret) { + dev_err(dev, "Failed to enable PCIe REFCLK\n"); + goto err_ref_clk; + } } =20 /* allow the clocks to stabilize */ @@ -686,7 +666,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pci= e) =20 static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx_pcie_disable_ref_clk(imx_pcie); + if (imx_pcie->drvdata->enable_ref_clk) + imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } =20 @@ -1475,6 +1456,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .init_phy =3D imx_pcie_init_phy, + .enable_ref_clk =3D imx6q_pcie_enable_ref_clk, }, [IMX6SX] =3D { .variant =3D IMX6SX, @@ -1489,6 +1471,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .init_phy =3D imx6sx_pcie_init_phy, + .enable_ref_clk =3D imx6sx_pcie_enable_ref_clk, }, [IMX6QP] =3D { .variant =3D IMX6QP, @@ -1504,6 +1487,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .init_phy =3D imx_pcie_init_phy, + .enable_ref_clk =3D imx6q_pcie_enable_ref_clk, }, [IMX7D] =3D { .variant =3D IMX7D, @@ -1516,6 +1500,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .init_phy =3D imx7d_pcie_init_phy, + .enable_ref_clk =3D imx7d_pcie_enable_ref_clk, }, [IMX8MQ] =3D { .variant =3D IMX8MQ, @@ -1529,6 +1514,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[1] =3D IOMUXC_GPR12, .mode_mask[1] =3D IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .init_phy =3D imx8mq_pcie_init_phy, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX8MM] =3D { .variant =3D IMX8MM, @@ -1540,6 +1526,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX8MP] =3D { .variant =3D IMX8MP, @@ -1551,6 +1538,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .clks_cnt =3D ARRAY_SIZE(imx8mm_clks), .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX95] =3D { .variant =3D IMX95, @@ -1577,6 +1565,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_mask[1] =3D IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .epc_features =3D &imx8m_pcie_epc_features, .init_phy =3D imx8mq_pcie_init_phy, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX8MM_EP] =3D { .variant =3D IMX8MM_EP, @@ -1589,6 +1578,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .epc_features =3D &imx8m_pcie_epc_features, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX8MP_EP] =3D { .variant =3D IMX8MP_EP, @@ -1601,6 +1591,7 @@ static const struct imx_pcie_drvdata drvdata[] =3D { .mode_off[0] =3D IOMUXC_GPR12, .mode_mask[0] =3D IMX6Q_GPR12_DEVICE_TYPE, .epc_features =3D &imx8m_pcie_epc_features, + .enable_ref_clk =3D imx8mm_pcie_enable_ref_clk, }, [IMX95_EP] =3D { .variant =3D IMX95_EP, --=20 2.34.1