From nobody Sun Feb 8 04:39:30 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 600B013A895; Sat, 6 Jul 2024 15:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720279275; cv=none; b=M4cQPNQbU3gFDdGmA4qaFUbPvFJYNE89CEA9+fWtEfciArWPP4maiy4H+D+5ZetNZb4EHdVbvvBAkimRfJJF0pT4aOsJLioanqKGKr0dfuZS9apj3FtRtxCLX79ajg/jPbpswKnxHTbb9n1/Hr8taW1oiAcisepkgCHgsH5PZGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720279275; c=relaxed/simple; bh=RTbf8OjTW1PHD5c8Ez3Vw/XWgfh3ubVm4i2VEAfelek=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b8smS9PXb13tsIfaD4fmpeAmgQNLPTqkMFCEBS7A+FAIbcAqUc+TbdAvF3uuZCRZW5YsL5R4jNPRoAGE8+O29TnhTln8NgNNGWOJJr3WNm8J6zyOTFF5bRJXFqtCGTNmcGRsIZZ6oSRv4Z3PPkOOcG11sazsniAtwZ2enbaL5MU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19A881477; Sat, 6 Jul 2024 08:21:31 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CF8AA3F762; Sat, 6 Jul 2024 08:21:03 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Ian Rogers , Namhyung Kim , James Clark , John Garry , Will Deacon , Adrian Hunter , Jiri Olsa , "Liang, Kan" , Suzuki K Poulose , Mike Leach , Kajol Jain , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan , James Clark Subject: [PATCH v2 1/2] perf arm-spe: Support multiple Arm SPE PMUs Date: Sat, 6 Jul 2024 16:20:34 +0100 Message-Id: <20240706152035.86983-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240706152035.86983-1-leo.yan@arm.com> References: <20240706152035.86983-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A platform can have more than one Arm SPE PMU. For example, a system with multiple clusters may have each cluster enabled with its own Arm SPE instance. In such case, the PMU devices will be named 'arm_spe_0', 'arm_spe_1', and so on. Currently, the tool only supports 'arm_spe_0'. This commit extends support to multiple Arm SPE PMUs by detecting the substring 'arm_spe_'. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/arch/arm/util/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c index 8b7cb68ba1a8..b762f6395d16 100644 --- a/tools/perf/arch/arm/util/pmu.c +++ b/tools/perf/arch/arm/util/pmu.c @@ -27,7 +27,7 @@ void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unu= sed) pmu->selectable =3D true; pmu->is_uncore =3D false; pmu->perf_event_attr_init_default =3D arm_spe_pmu_default_config; - if (!strcmp(pmu->name, "arm_spe_0")) + if (strstarts(pmu->name, "arm_spe_")) pmu->mem_events =3D perf_mem_events_arm; } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { pmu->selectable =3D true; --=20 2.34.1 From nobody Sun Feb 8 04:39:30 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8E82E13B285; Sat, 6 Jul 2024 15:21:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720279276; cv=none; b=kPYwH1iu6imHbQ0EFjwsHZFneupK+TKNksEwnpJfQTG0Qktc/EA59/Zfwp3w3hjVZqh7YZbtFptHf9LVXp45rtcBhV6suRYLceDsfmu0jrVHNZcEiU+O17hG38wV+f2S+ExEkI2rDssF3QF6G6AykPb+V45Ezkhmo2xl7RocFNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720279276; c=relaxed/simple; bh=yXdPT+WkyCxMh0Bgond9k/k+SWwa6T8kNHAgWgcUYnQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=onOvLIIHFbtWxhWhJ8bChWgKikNtZdDi2GiXyLbrBfbEE+qrh9o+HBb9FNoNyleykDfsFg/vzYY04JOKIPTnU+AcVS13V8nJUBL65cE81n2m46sOk3m0R6aFt196PQ1B9iVI1RXgUpt+mIKiSawqthEBY6+4WyaiK/I4IPL0WQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70B881596; Sat, 6 Jul 2024 08:21:33 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3BC623F762; Sat, 6 Jul 2024 08:21:06 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Ian Rogers , Namhyung Kim , James Clark , John Garry , Will Deacon , Adrian Hunter , Jiri Olsa , "Liang, Kan" , Suzuki K Poulose , Mike Leach , Kajol Jain , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan , James Clark Subject: [PATCH v2 2/2] perf mem: Warn if memory events are not supported on all CPUs Date: Sat, 6 Jul 2024 16:20:35 +0100 Message-Id: <20240706152035.86983-3-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240706152035.86983-1-leo.yan@arm.com> References: <20240706152035.86983-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is possible that memory events are not supported on all CPUs. Prints a warning by dumping the enabled CPU maps in this case. Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/mem-events.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 6dda47bb774f..8aff2ca8bbd5 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -8,6 +8,7 @@ #include #include #include +#include "cpumap.h" #include "map_symbol.h" #include "mem-events.h" #include "mem-info.h" @@ -242,6 +243,7 @@ int perf_mem_events__record_args(const char **rec_argv,= int *argv_nr) int i =3D *argv_nr; const char *s; char *copy; + struct perf_cpu_map *cpu_map =3D NULL; =20 while ((pmu =3D perf_pmus__scan_mem(pmu)) !=3D NULL) { for (int j =3D 0; j < PERF_MEM_EVENTS__MAX; j++) { @@ -266,7 +268,19 @@ int perf_mem_events__record_args(const char **rec_argv= , int *argv_nr) =20 rec_argv[i++] =3D "-e"; rec_argv[i++] =3D copy; + + cpu_map =3D perf_cpu_map__merge(cpu_map, pmu->cpus); + } + } + + if (cpu_map) { + if (!perf_cpu_map__equal(cpu_map, cpu_map__online())) { + char buf[200]; + + cpu_map__snprint(cpu_map, buf, sizeof(buf)); + pr_warning("Memory events are enabled on a subset of CPUs: %s\n", buf); } + perf_cpu_map__put(cpu_map); } =20 *argv_nr =3D i; --=20 2.34.1