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charset="utf-8" i.MX8qxp Display Controller has a built-in interrupt controller to support Enable/Status/Preset/Clear interrupt bit. Add driver for it. Signed-off-by: Liu Ying --- drivers/gpu/drm/imx/dc/Kconfig | 1 + drivers/gpu/drm/imx/dc/Makefile | 2 +- drivers/gpu/drm/imx/dc/dc-drv.c | 1 + drivers/gpu/drm/imx/dc/dc-drv.h | 1 + drivers/gpu/drm/imx/dc/dc-ic.c | 249 ++++++++++++++++++++++++++++++++ 5 files changed, 253 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/imx/dc/dc-ic.c diff --git a/drivers/gpu/drm/imx/dc/Kconfig b/drivers/gpu/drm/imx/dc/Kconfig index 32d7471c49d0..b66b815fbdf1 100644 --- a/drivers/gpu/drm/imx/dc/Kconfig +++ b/drivers/gpu/drm/imx/dc/Kconfig @@ -1,5 +1,6 @@ config DRM_IMX8_DC tristate "Freescale i.MX8 Display Controller Graphics" depends on DRM && COMMON_CLK && OF && (ARCH_MXC || COMPILE_TEST) + select GENERIC_IRQ_CHIP help enable Freescale i.MX8 Display Controller(DC) graphics support diff --git a/drivers/gpu/drm/imx/dc/Makefile b/drivers/gpu/drm/imx/dc/Makef= ile index 2942ae6fd5bd..1ce3e8a8db22 100644 --- a/drivers/gpu/drm/imx/dc/Makefile +++ b/drivers/gpu/drm/imx/dc/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 =20 imx8-dc-drm-objs :=3D dc-cf.o dc-de.o dc-drv.o dc-ed.o dc-fg.o dc-fl.o dc-= fu.o \ - dc-fw.o dc-lb.o dc-pe.o dc-tc.o + dc-fw.o dc-ic.o dc-lb.o dc-pe.o dc-tc.o =20 obj-$(CONFIG_DRM_IMX8_DC) +=3D imx8-dc-drm.o diff --git a/drivers/gpu/drm/imx/dc/dc-drv.c b/drivers/gpu/drm/imx/dc/dc-dr= v.c index 7c64acc863ad..fd68861f770a 100644 --- a/drivers/gpu/drm/imx/dc/dc-drv.c +++ b/drivers/gpu/drm/imx/dc/dc-drv.c @@ -15,6 +15,7 @@ static struct platform_driver * const dc_drivers[] =3D { &dc_fg_driver, &dc_fl_driver, &dc_fw_driver, + &dc_ic_driver, &dc_lb_driver, &dc_pe_driver, &dc_tc_driver, diff --git a/drivers/gpu/drm/imx/dc/dc-drv.h b/drivers/gpu/drm/imx/dc/dc-dr= v.h index c687a36b8153..3b11f4862c6c 100644 --- a/drivers/gpu/drm/imx/dc/dc-drv.h +++ b/drivers/gpu/drm/imx/dc/dc-drv.h @@ -25,6 +25,7 @@ extern struct platform_driver dc_de_driver; extern struct platform_driver dc_fg_driver; extern struct platform_driver dc_fl_driver; extern struct platform_driver dc_fw_driver; +extern struct platform_driver dc_ic_driver; extern struct platform_driver dc_lb_driver; extern struct platform_driver dc_pe_driver; extern struct platform_driver dc_tc_driver; diff --git a/drivers/gpu/drm/imx/dc/dc-ic.c b/drivers/gpu/drm/imx/dc/dc-ic.c new file mode 100644 index 000000000000..8540a0414b39 --- /dev/null +++ b/drivers/gpu/drm/imx/dc/dc-ic.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dc-drv.h" + +#define USERINTERRUPTMASK(n) (0x8 + 4 * (n)) +#define INTERRUPTENABLE(n) (0x10 + 4 * (n)) +#define INTERRUPTCLEAR(n) (0x20 + 4 * (n)) +#define INTERRUPTSTATUS(n) (0x28 + 4 * (n)) +#define USERINTERRUPTENABLE(n) (0x40 + 4 * (n)) +#define USERINTERRUPTCLEAR(n) (0x50 + 4 * (n)) +#define USERINTERRUPTSTATUS(n) (0x58 + 4 * (n)) + +#define IRQ_COUNT 49 +#define IRQ_RESERVED 35 +#define REG_NUM 2 + +struct dc_ic_data { + void __iomem *regs; + struct clk *clk_axi; + int irq[IRQ_COUNT]; + struct irq_domain *domain; +}; + +struct dc_ic_entry { + struct dc_ic_data *data; + int irq; +}; + +static void dc_ic_irq_handler(struct irq_desc *desc) +{ + struct dc_ic_entry *entry =3D irq_desc_get_handler_data(desc); + struct dc_ic_data *data =3D entry->data; + unsigned int virq; + u32 status; + + chained_irq_enter(irq_desc_get_chip(desc), desc); + + status =3D readl(data->regs + USERINTERRUPTSTATUS(entry->irq / 32)); + status &=3D readl(data->regs + USERINTERRUPTENABLE(entry->irq / 32)); + + if (status & BIT(entry->irq % 32)) { + virq =3D irq_linear_revmap(data->domain, entry->irq); + if (virq) + generic_handle_irq(virq); + } + + chained_irq_exit(irq_desc_get_chip(desc), desc); +} + +static const unsigned long unused_irq[REG_NUM] =3D {0x00000000, 0xfffe0008= }; + +static int +dc_ic_bind(struct device *dev, struct device *master, void *master_data) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct dc_drm_device *dc_drm =3D master_data; + struct dc_ic_entry *entry; + struct irq_chip_generic *gc; + struct dc_ic_data *data; + struct irq_chip_type *ct; + int i, ret; + + data =3D drmm_kzalloc(&dc_drm->base, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + entry =3D drmm_kcalloc(&dc_drm->base, IRQ_COUNT, sizeof(*entry), + GFP_KERNEL); + if (!entry) + return -ENOMEM; + + data->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->regs)) { + dev_err(dev, "failed to initialize reg\n"); + return PTR_ERR(data->regs); + } + + data->clk_axi =3D devm_clk_get(dev, NULL); + if (IS_ERR(data->clk_axi)) + return dev_err_probe(dev, PTR_ERR(data->clk_axi), + "failed to get AXI clock\n"); + + dev_set_drvdata(dev, data); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "failed to get runtime PM sync: %d\n", ret); + return ret; + } + + for (i =3D 0; i < REG_NUM; i++) { + /* mask and clear all interrupts */ + writel(0x0, data->regs + USERINTERRUPTENABLE(i)); + writel(0x0, data->regs + INTERRUPTENABLE(i)); + writel(0xffffffff, data->regs + USERINTERRUPTCLEAR(i)); + writel(0xffffffff, data->regs + INTERRUPTCLEAR(i)); + + /* set all interrupts to user mode */ + writel(0xffffffff, data->regs + USERINTERRUPTMASK(i)); + } + + data->domain =3D irq_domain_add_linear(dev->of_node, IRQ_COUNT, + &irq_generic_chip_ops, data); + if (!data->domain) { + dev_err(dev, "failed to create IRQ domain\n"); + pm_runtime_put(dev); + return -ENOMEM; + } + irq_domain_set_pm_device(data->domain, &pdev->dev); + + ret =3D irq_alloc_domain_generic_chips(data->domain, 32, 1, "DC", + handle_level_irq, 0, 0, 0); + if (ret) { + dev_err(dev, "failed to alloc generic IRQ chips: %d\n", ret); + irq_domain_remove(data->domain); + pm_runtime_put(dev); + return ret; + } + + for (i =3D 0; i < IRQ_COUNT; i +=3D 32) { + gc =3D irq_get_domain_generic_chip(data->domain, i); + gc->reg_base =3D data->regs; + gc->unused =3D unused_irq[i / 32]; + ct =3D gc->chip_types; + ct->chip.irq_ack =3D irq_gc_ack_set_bit; + ct->chip.irq_mask =3D irq_gc_mask_clr_bit; + ct->chip.irq_unmask =3D irq_gc_mask_set_bit; + ct->regs.ack =3D USERINTERRUPTCLEAR(i / 32); + ct->regs.mask =3D USERINTERRUPTENABLE(i / 32); + } + + for (i =3D 0; i < IRQ_COUNT; i++) { + /* skip the reserved IRQ */ + if (i =3D=3D IRQ_RESERVED) + continue; + + data->irq[i] =3D irq_of_parse_and_map(dev->of_node, i); + + entry[i].data =3D data; + entry[i].irq =3D i; + + irq_set_chained_handler_and_data(data->irq[i], + dc_ic_irq_handler, &entry[i]); + } + + return 0; +} + +static void +dc_ic_unbind(struct device *dev, struct device *master, void *master_data) +{ + struct dc_ic_data *data =3D dev_get_drvdata(dev); + int i; + + for (i =3D 0; i < IRQ_COUNT; i++) { + if (i =3D=3D IRQ_RESERVED) + continue; + + irq_set_chained_handler_and_data(data->irq[i], NULL, NULL); + } + + irq_domain_remove(data->domain); + + pm_runtime_put_sync(dev); +} + +static const struct component_ops dc_ic_ops =3D { + .bind =3D dc_ic_bind, + .unbind =3D dc_ic_unbind, +}; + +static int dc_ic_probe(struct platform_device *pdev) +{ + int ret; + + ret =3D component_add(&pdev->dev, &dc_ic_ops); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to add component\n"); + + return 0; +} + +static void dc_ic_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dc_ic_ops); +} + +static int dc_ic_runtime_suspend(struct device *dev) +{ + struct dc_ic_data *data =3D dev_get_drvdata(dev); + + clk_disable_unprepare(data->clk_axi); + + return 0; +} + +static int dc_ic_runtime_resume(struct device *dev) +{ + struct dc_ic_data *data =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(data->clk_axi); + if (ret) + dev_err(dev, "failed to enable AXI clock: %d\n", ret); + + return ret; +} + +static const struct dev_pm_ops dc_ic_pm_ops =3D { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + RUNTIME_PM_OPS(dc_ic_runtime_suspend, dc_ic_runtime_resume, NULL) +}; + +static const struct of_device_id dc_ic_dt_ids[] =3D { + { .compatible =3D "fsl,imx8qxp-dc-intc", }, + { /* sentinel */ } +}; + +struct platform_driver dc_ic_driver =3D { + .probe =3D dc_ic_probe, + .remove_new =3D dc_ic_remove, + .driver =3D { + .name =3D "imx8-dc-intc", + .of_match_table =3D dc_ic_dt_ids, + .pm =3D pm_sleep_ptr(&dc_ic_pm_ops), + }, +}; --=20 2.34.1