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Date: Thu, 4 Jul 2024 15:29:54 +0800 Message-Id: <20240704072958.27876-2-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This driver currently only applies to one panel. Modify it to be compatible with other panels. Signed-off-by: Zhaoxiong Lv --- .../drm/panel/panel-boe-th101mb31ig002-28a.c | 40 +++++++++++++++---- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers= /gpu/drm/panel/panel-boe-th101mb31ig002-28a.c index 763e9f8342d3..159e401ad0e6 100644 --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -17,11 +17,21 @@ #include #include =20 +struct panel_desc { + const struct drm_display_mode *modes; + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + const struct panel_init_cmd *init_cmds; + unsigned int lanes; +}; + struct boe_th101mb31ig002 { struct drm_panel panel; =20 struct mipi_dsi_device *dsi; =20 + const struct panel_desc *desc; + struct regulator *power; struct gpio_desc *enable; struct gpio_desc *reset; @@ -161,7 +171,10 @@ static int boe_th101mb31ig002_prepare(struct drm_panel= *panel) gpiod_set_value_cansleep(ctx->enable, 1); msleep(50); boe_th101mb31ig002_reset(ctx); - boe_th101mb31ig002_enable(panel); + + ret =3D ctx->desc->init(ctx); + if (ret) + return ret; =20 return 0; } @@ -181,6 +194,16 @@ static const struct drm_display_mode boe_th101mb31ig00= 2_default_mode =3D { .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, }; =20 +static const struct panel_desc boe_th101mb31ig002_desc =3D { + .modes =3D &boe_th101mb31ig002_default_mode, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .mode_flags =3D MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_MODE_LPM, + .init_cmds =3D boe_th101mb31ig002_enable, +}; + static int boe_th101mb31ig002_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -237,6 +260,7 @@ static const struct drm_panel_funcs boe_th101mb31ig002_= funcs =3D { static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi_device *dsi) { struct boe_th101mb31ig002 *ctx; + const struct panel_desc *desc; int ret; =20 ctx =3D devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL); @@ -246,11 +270,11 @@ static int boe_th101mb31ig002_dsi_probe(struct mipi_d= si_device *dsi) mipi_dsi_set_drvdata(dsi, ctx); ctx->dsi =3D dsi; =20 - dsi->lanes =3D 4; - dsi->format =3D MIPI_DSI_FMT_RGB888; - dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_NO_EOT_PACKET | - MIPI_DSI_MODE_LPM; + desc =3D of_device_get_match_data(&dsi->dev); + dsi->lanes =3D desc->lanes; + dsi->format =3D desc->format; + dsi->mode_flags =3D desc->mode_flags; + ctx->desc =3D desc; =20 ctx->power =3D devm_regulator_get(&dsi->dev, "power"); if (IS_ERR(ctx->power)) @@ -302,7 +326,9 @@ static void boe_th101mb31ig002_dsi_remove(struct mipi_d= si_device *dsi) } =20 static const struct of_device_id boe_th101mb31ig002_of_match[] =3D { - { .compatible =3D "boe,th101mb31ig002-28a", }, + { .compatible =3D "boe,th101mb31ig002-28a", + .data =3D &boe_th101mb31ig002_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_th101mb31ig002_of_match); --=20 2.17.1 From nobody Mon Feb 9 18:21:59 2026 Received: from mail-il1-f179.google.com (mail-il1-f179.google.com [209.85.166.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449101A2FCF for ; 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Thu, 04 Jul 2024 00:30:22 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6a8dbb2fsm7735699a12.31.2024.07.04.00.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 00:30:21 -0700 (PDT) From: Zhaoxiong Lv To: neil.armstrong@linaro.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, airlied@gmail.com, daniel@ffwll.ch, mripard@kernel.org, dianders@google.com, hsinyi@google.com, awarnecke002@hotmail.com, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 2/5] drm/panel: boe-th101mb31ig002: switch to devm_gpiod_get_optional() for reset_gpio Date: Thu, 4 Jul 2024 15:29:55 +0800 Message-Id: <20240704072958.27876-3-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Switch the driver to use devm_gpiod_get_optional() on reset_gpio to avoid driver probe issues when reset line is not specified. Signed-off-by: Zhaoxiong Lv --- drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers= /gpu/drm/panel/panel-boe-th101mb31ig002-28a.c index 159e401ad0e6..9f225c15b21c 100644 --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -286,7 +286,7 @@ static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi= _device *dsi) return dev_err_probe(&dsi->dev, PTR_ERR(ctx->enable), "Failed to get enable GPIO\n"); =20 - ctx->reset =3D devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_HIGH); + ctx->reset =3D devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_HIGH= ); if (IS_ERR(ctx->reset)) return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset), "Failed to get reset GPIO\n"); --=20 2.17.1 From nobody Mon Feb 9 18:21:59 2026 Received: from mail-oi1-f177.google.com (mail-oi1-f177.google.com [209.85.167.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5600B1A254F for ; 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Thu, 04 Jul 2024 00:30:27 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6a8dbb2fsm7735699a12.31.2024.07.04.00.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 00:30:27 -0700 (PDT) From: Zhaoxiong Lv To: neil.armstrong@linaro.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, airlied@gmail.com, daniel@ffwll.ch, mripard@kernel.org, dianders@google.com, hsinyi@google.com, awarnecke002@hotmail.com, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 3/5] drm/panel: boe-th101mb31ig002: use wrapped MIPI DCS functions Date: Thu, 4 Jul 2024 15:29:56 +0800 Message-Id: <20240704072958.27876-4-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/enable/exit code. Convert the hex in init_code from UPPERCASE to lowercase. Signed-off-by: Zhaoxiong Lv Reviewed-by: Neil Armstrong --- .../drm/panel/panel-boe-th101mb31ig002-28a.c | 143 ++++++++---------- 1 file changed, 63 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers= /gpu/drm/panel/panel-boe-th101mb31ig002-28a.c index 9f225c15b21c..736bfba607cf 100644 --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -17,11 +17,13 @@ #include #include =20 +struct boe_th101mb31ig002; + struct panel_desc { const struct drm_display_mode *modes; unsigned long mode_flags; enum mipi_dsi_pixel_format format; - const struct panel_init_cmd *init_cmds; + int (*init)(struct boe_th101mb31ig002 *ctx); unsigned int lanes; }; =20 @@ -49,74 +51,61 @@ static void boe_th101mb31ig002_reset(struct boe_th101mb= 31ig002 *ctx) usleep_range(5000, 6000); } =20 -static int boe_th101mb31ig002_enable(struct drm_panel *panel) +static int boe_th101mb31ig002_enable(struct boe_th101mb31ig002 *ctx) { - struct boe_th101mb31ig002 *ctx =3D container_of(panel, - struct boe_th101mb31ig002, - panel); - struct mipi_dsi_device *dsi =3D ctx->dsi; - struct device *dev =3D &dsi->dev; - int ret; - - mipi_dsi_dcs_write_seq(dsi, 0xE0, 0xAB, 0xBA); - mipi_dsi_dcs_write_seq(dsi, 0xE1, 0xBA, 0xAB); - mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x10, 0x01, 0x47, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x0C, 0x14, 0x04, 0x50, 0x50, 0x14); - mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x56, 0x53, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x33, 0x30, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xB6, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x10, - 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x7C, 0x65, 0x55, 0x49, 0x46, 0x36, - 0x3B, 0x24, 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, - 0x55, 0x47, 0x46, 0x39, 0x26, 0x06, 0x7C, - 0x65, 0x55, 0x49, 0x46, 0x36, 0x3B, 0x24, - 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, 0x55, 0x47, - 0x46, 0x39, 0x26, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0x00, 0xFF, 0x87, 0x12, 0x34, 0x44, 0x44, - 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0F, - 0x00, 0x00, 0xC1); - mipi_dsi_dcs_write_seq(dsi, 0xC1, 0x54, 0x94, 0x02, 0x85, 0x9F, 0x00, - 0x7F, 0x00, 0x54, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11, - 0x22, 0x20, 0x44, 0xFF, 0x18, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC3, 0x86, 0x46, 0x05, 0x05, 0x1C, 0x1C, - 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, - 0x0F, 0x0F, 0x0D, 0x0D, 0x13, 0x13, 0x11, - 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC4, 0x07, 0x07, 0x04, 0x04, 0x1C, 0x1C, - 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, - 0x0E, 0x0E, 0x0C, 0x0C, 0x12, 0x12, 0x10, - 0x10, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC6, 0x2A, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0xC8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16); - mipi_dsi_dcs_write_seq(dsi, 0xCA, 0xCB, 0x43); - mipi_dsi_dcs_write_seq(dsi, 0xCD, 0x0E, 0x4B, 0x4B, 0x20, 0x19, 0x6B, - 0x06, 0xB3); - mipi_dsi_dcs_write_seq(dsi, 0xD2, 0xE3, 0x2B, 0x38, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xD4, 0x00, 0x01, 0x00, 0x0E, 0x04, 0x44, - 0x08, 0x10, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xE6, 0x80, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xF0, 0x12, 0x03, 0x20, 0x00, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xF3, 0x00); - - ret =3D mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - - msleep(120); - - ret =3D mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set panel on: %d\n", ret); - return ret; - } - - return 0; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50= , 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00= , 0x10, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x48= , 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x65, 0x55, 0x49, 0x46= , 0x36, + 0x3b, 0x24, 0x3d, 0x3c, 0x3d, 0x5c, 0x4c, + 0x55, 0x47, 0x46, 0x39, 0x26, 0x06, 0x7c, + 0x65, 0x55, 0x49, 0x46, 0x36, 0x3b, 0x24, + 0x3d, 0x3c, 0x3d, 0x5c, 0x4c, 0x55, 0x47, + 0x46, 0x39, 0x26, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0xff, 0x87, 0x12, 0x34, 0x44= , 0x44, + 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0f, + 0x00, 0x00, 0xc1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x54, 0x94, 0x02, 0x85, 0x9f= , 0x00, + 0x7f, 0x00, 0x54, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x17, 0x09, 0x08, 0x89, 0x08= , 0x11, + 0x22, 0x20, 0x44, 0xff, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x86, 0x46, 0x05, 0x05, 0x1c= , 0x1c, + 0x1d, 0x1d, 0x02, 0x1f, 0x1f, 0x1e, 0x1e, + 0x0f, 0x0f, 0x0d, 0x0d, 0x13, 0x13, 0x11, + 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x07, 0x07, 0x04, 0x04, 0x1c= , 0x1c, + 0x1d, 0x1d, 0x02, 0x1f, 0x1f, 0x1e, 0x1e, + 0x0e, 0x0e, 0x0c, 0x0c, 0x12, 0x12, 0x10, + 0x10, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc6, 0x2a, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x21, 0x00, 0x31, 0x42, 0x34= , 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x0e, 0x4b, 0x4b, 0x20, 0x19= , 0x6b, + 0x06, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2, 0xe3, 0x2b, 0x38, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x00, 0x01, 0x00, 0x0e, 0x04= , 0x44, + 0x08, 0x10, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x80, 0x01, 0xff, 0xff, 0xff= , 0xff, + 0xff, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x12, 0x03, 0x20, 0x00, 0xff= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + return dsi_ctx.accum_err; } =20 static int boe_th101mb31ig002_disable(struct drm_panel *panel) @@ -124,21 +113,15 @@ static int boe_th101mb31ig002_disable(struct drm_pane= l *panel) struct boe_th101mb31ig002 *ctx =3D container_of(panel, struct boe_th101mb31ig002, panel); - struct mipi_dsi_device *dsi =3D ctx->dsi; - struct device *dev =3D &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; =20 - ret =3D mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(dev, "Failed to set panel off: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); =20 - msleep(120); + mipi_dsi_msleep(&dsi_ctx, 120); =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); =20 - return 0; + return dsi_ctx.accum_err; } =20 static int boe_th101mb31ig002_unprepare(struct drm_panel *panel) @@ -201,7 +184,7 @@ static const struct panel_desc boe_th101mb31ig002_desc = =3D { .mode_flags =3D MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_MODE_LPM, - .init_cmds =3D boe_th101mb31ig002_enable, + .init =3D boe_th101mb31ig002_enable, }; =20 static int boe_th101mb31ig002_get_modes(struct drm_panel *panel, --=20 2.17.1 From nobody Mon Feb 9 18:21:59 2026 Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com [209.85.210.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF85E1A4F02 for ; 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Thu, 04 Jul 2024 00:30:33 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6a8dbb2fsm7735699a12.31.2024.07.04.00.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 00:30:32 -0700 (PDT) From: Zhaoxiong Lv To: neil.armstrong@linaro.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, airlied@gmail.com, daniel@ffwll.ch, mripard@kernel.org, dianders@google.com, hsinyi@google.com, awarnecke002@hotmail.com, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 4/5] dt-bindings: display: panel: Add compatible for starry-er88577 Date: Thu, 4 Jul 2024 15:29:57 +0800 Message-Id: <20240704072958.27876-5-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The starry-er88577 is a 10.1" WXGA TFT-LCD panel. Hence, we=20 add a new compatible with panel specific config. Signed-off-by: Zhaoxiong Lv Acked-by: Conor Dooley --- Changes between V5 and V4: - 1. We are compatible with starry-er88577 panels in the boe-th101mb31ig002 - driver, so add it to the "boe,th101mb31ig002-28a.yaml". v4: https://lore.kernel.org/all/20240620115245.31540-2-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V4 and V3: - 1. Move positions to keep the list sorted. v3: https://lore.kernel.org/all/20240614145609.25432-2-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V3 and V2: - 1. Separate the Starry bindings from kingdisplay, and add it to panel-si= mple-dsi.yaml v2: https://lore.kernel.org/all/20240601084528.22502-4-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V2 and V1: - 1. Add compatible for Starry er88577 in Kingdisplay kd101ne3 dt-bindings. --- .../bindings/display/panel/boe,th101mb31ig002-28a.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,th101mb31i= g002-28a.yaml b/Documentation/devicetree/bindings/display/panel/boe,th101mb= 31ig002-28a.yaml index 32df26cbfeed..2f251703a121 100644 --- a/Documentation/devicetree/bindings/display/panel/boe,th101mb31ig002-28= a.yaml +++ b/Documentation/devicetree/bindings/display/panel/boe,th101mb31ig002-28= a.yaml @@ -17,6 +17,8 @@ properties: enum: # BOE TH101MB31IG002-28A 10.1" WXGA TFT LCD panel - boe,th101mb31ig002-28a + # The Starry-er88577 is a 10.1" WXGA TFT-LCD panel + - starry,er88577 =20 reg: true backlight: true --=20 2.17.1 From nobody Mon Feb 9 18:21:59 2026 Received: from mail-ot1-f46.google.com (mail-ot1-f46.google.com [209.85.210.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DB011A2C0E for ; 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Thu, 04 Jul 2024 00:30:37 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6a8dbb2fsm7735699a12.31.2024.07.04.00.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jul 2024 00:30:37 -0700 (PDT) From: Zhaoxiong Lv To: neil.armstrong@linaro.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, airlied@gmail.com, daniel@ffwll.ch, mripard@kernel.org, dianders@google.com, hsinyi@google.com, awarnecke002@hotmail.com, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 5/5] drm/panel: :boe-th101mb31ig002: Support for starry-er88577 MIPI-DSI panel Date: Thu, 4 Jul 2024 15:29:58 +0800 Message-Id: <20240704072958.27876-6-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240704072958.27876-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The init_code of the starry-er88577 panel is very similar to the panel-boe-th101mb31ig002-28a.c driver, so we make it compatible with the panel-boe-th101mb31ig002-28a.c driver Signed-off-by: Zhaoxiong Lv Reviewed-by: Neil Armstrong --- Changes between V5 and V4: - 1. Compatible with starry-er88577 panel in panel-boe-th101mb31ig002-28a.= c driver,. v4: https://lore.kernel.org/all/20240620115245.31540-3-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V4 and V3: - 1. Adjust the ".clock" assignment format. v3: https://lore.kernel.org/all/20240614145609.25432-3-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V3 and V2: - Separate Starry-er88577 from the panel-kingdisplay-kd101ne3 driver. - Use mipi_dsi_dcs_set_display_on_multi(). - Use mipi_dsi_dcs_exit_sleep_mode_multi() and mipi_dsi_msleep(). v2: https://lore.kernel.org/all/20240601084528.22502-5-lvzhaoxiong@huaqin.c= orp-partner.google.com/ Changes between V2 and V1: - Add compatible for Starry er88577 in panel-kingdisplay-kd101ne3 drivers. --- .../drm/panel/panel-boe-th101mb31ig002-28a.c | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers= /gpu/drm/panel/panel-boe-th101mb31ig002-28a.c index 736bfba607cf..c103236cc970 100644 --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -25,6 +25,12 @@ struct panel_desc { enum mipi_dsi_pixel_format format; int (*init)(struct boe_th101mb31ig002 *ctx); unsigned int lanes; + bool lp11_before_reset; + unsigned int vcioo_to_lp11_delay_ms; + unsigned int lp11_to_reset_delay_ms; + unsigned int backlight_off_to_display_off_delay_ms; + unsigned int enter_sleep_to_reset_down_delay_ms; + unsigned int power_off_delay_ms; }; =20 struct boe_th101mb31ig002 { @@ -108,6 +114,65 @@ static int boe_th101mb31ig002_enable(struct boe_th101m= b31ig002 *ctx) return dsi_ctx.accum_err; } =20 +static int starry_er88577_init_cmd(struct boe_th101mb31ig002 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + msleep(70); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50= , 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00= , 0x10, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x40= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x61, 0x4f, 0x42, 0x3e= , 0x2d, + 0x31, 0x1a, 0x33, 0x33, 0x33, 0x52, 0x40, + 0x47, 0x38, 0x34, 0x26, 0x0e, 0x06, 0x7c, + 0x61, 0x4f, 0x42, 0x3e, 0x2d, 0x31, 0x1a, + 0x33, 0x33, 0x33, 0x52, 0x40, 0x47, 0x38, + 0x34, 0x26, 0x0e, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0xcc, 0x76, 0x12, 0x34, 0x44= , 0x44, + 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0f, + 0x00, 0x00, 0xc1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x54, 0x94, 0x02, 0x85, 0x9f= , 0x00, + 0x6f, 0x00, 0x54, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x17, 0x09, 0x08, 0x89, 0x08= , 0x11, + 0x22, 0x20, 0x44, 0xff, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x87, 0x47, 0x05, 0x05, 0x1c= , 0x1c, + 0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f, + 0x0f, 0x0f, 0x0d, 0x0d, 0x13, 0x13, 0x11, + 0x11, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x06, 0x06, 0x04, 0x04, 0x1c= , 0x1c, + 0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f, + 0x0e, 0x0e, 0x0c, 0x0c, 0x12, 0x12, 0x10, + 0x10, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x21, 0x00, 0x31, 0x42, 0x34= , 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x0e, 0x4b, 0x4b, 0x20, 0x19= , 0x6b, + 0x06, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2, 0xe3, 0x2b, 0x38, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x00, 0x01, 0x00, 0x0e, 0x04= , 0x44, + 0x08, 0x10, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x80, 0x09, 0xff, 0xff, 0xff= , 0xff, + 0xff, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x12, 0x03, 0x20, 0x00, 0xff= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); + + return dsi_ctx.accum_err; +} + static int boe_th101mb31ig002_disable(struct drm_panel *panel) { struct boe_th101mb31ig002 *ctx =3D container_of(panel, @@ -115,12 +180,18 @@ static int boe_th101mb31ig002_disable(struct drm_pane= l *panel) panel); struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; =20 + if (ctx->desc->backlight_off_to_display_off_delay_ms) + mipi_dsi_msleep(&dsi_ctx, ctx->desc->backlight_off_to_display_off_delay_= ms); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); =20 mipi_dsi_msleep(&dsi_ctx, 120); =20 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); =20 + if (ctx->desc->enter_sleep_to_reset_down_delay_ms) + mipi_dsi_msleep(&dsi_ctx, ctx->desc->enter_sleep_to_reset_down_delay_ms); + return dsi_ctx.accum_err; } =20 @@ -134,6 +205,9 @@ static int boe_th101mb31ig002_unprepare(struct drm_pane= l *panel) gpiod_set_value_cansleep(ctx->enable, 0); regulator_disable(ctx->power); =20 + if(ctx->desc->power_off_delay_ms) + msleep(ctx->desc->power_off_delay_ms); + return 0; } =20 @@ -151,6 +225,18 @@ static int boe_th101mb31ig002_prepare(struct drm_panel= *panel) return ret; } =20 + if (ctx->desc->vcioo_to_lp11_delay_ms) + msleep(ctx->desc->vcioo_to_lp11_delay_ms); + + if (ctx->desc->lp11_before_reset) { + ret =3D mipi_dsi_dcs_nop(ctx->dsi); + if (ret) + return ret; + } + + if (ctx->desc->lp11_to_reset_delay_ms) + msleep(ctx->desc->lp11_to_reset_delay_ms); + gpiod_set_value_cansleep(ctx->enable, 1); msleep(50); boe_th101mb31ig002_reset(ctx); @@ -187,6 +273,36 @@ static const struct panel_desc boe_th101mb31ig002_desc= =3D { .init =3D boe_th101mb31ig002_enable, }; =20 +static const struct drm_display_mode starry_er88577_default_mode =3D { + .clock =3D (800 + 25 + 25 + 25) * (1280 + 20 + 4 + 12) * 60 / 1000, + .hdisplay =3D 800, + .hsync_start =3D 800 + 25, + .hsync_end =3D 800 + 25 + 25, + .htotal =3D 800 + 25 + 25 + 25, + .vdisplay =3D 1280, + .vsync_start =3D 1280 + 20, + .vsync_end =3D 1280 + 20 + 4, + .vtotal =3D 1280 + 20 + 4 + 12, + .width_mm =3D 135, + .height_mm =3D 216, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc starry_er88577_desc =3D { + .modes =3D &starry_er88577_default_mode, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init =3D starry_er88577_init_cmd, + .lp11_before_reset =3D true, + .vcioo_to_lp11_delay_ms =3D 5, + .lp11_to_reset_delay_ms =3D 50, + .backlight_off_to_display_off_delay_ms =3D 100, + .enter_sleep_to_reset_down_delay_ms =3D 100, + .power_off_delay_ms =3D 1000, +}; + static int boe_th101mb31ig002_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -312,6 +428,9 @@ static const struct of_device_id boe_th101mb31ig002_of_= match[] =3D { { .compatible =3D "boe,th101mb31ig002-28a", .data =3D &boe_th101mb31ig002_desc }, + { .compatible =3D "starry,er88577", + .data =3D &starry_er88577_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_th101mb31ig002_of_match); --=20 2.17.1