From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 688871DA30D; Thu, 4 Jul 2024 11:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.136.128.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720092713; cv=none; b=aQWAo/9WjLC13eBWEK1nbK7BDfM0hHSMkAZbbI/ywAGjn1QWa1L3EVg2RujQuNhOUsrVWXvXt8jEzfNfA39nyiKQG6gqEH0peu42710JPRonyjnXubhoXwOCyuEbY7J+vY1oRsfogVGOE8J9G0QRMCLbdAYzPLPusIwhhmeC8SA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720092713; c=relaxed/simple; bh=9Sh3tAClsJyJKcGbDy+P6ZvkeV1elIlxANmbsLEcOjE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RaCehui79TqX5SLHiEabO6oLJMbTAsvVD6hGsMxNSy54MgyvMO2HAuikcKS/Ri48LO9AKHMrwlB54EtUsiG6Xrg8SdTN+6HKXk2CLfpp6WwSTcs4++URDXxyyHyZ+ERzXwCpL/ZmnAWNwcwI7pS2ymuszbmyWXJBBeUtO1bDjVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tecnico.ulisboa.pt; spf=pass smtp.mailfrom=tecnico.ulisboa.pt; dkim=pass (1024-bit key) header.d=tecnico.ulisboa.pt header.i=@tecnico.ulisboa.pt header.b=jjGxKYR8; arc=none smtp.client-ip=193.136.128.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=tecnico.ulisboa.pt Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tecnico.ulisboa.pt Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=tecnico.ulisboa.pt header.i=@tecnico.ulisboa.pt header.b="jjGxKYR8" Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp1.tecnico.ulisboa.pt (Postfix) with ESMTP id 6BCA86003430; Thu, 4 Jul 2024 12:31:41 +0100 (WEST) X-Virus-Scanned: by amavis-2.13.0 (20230106) (Debian) at tecnico.ulisboa.pt Received: from smtp1.tecnico.ulisboa.pt ([127.0.0.1]) by localhost (smtp1.tecnico.ulisboa.pt [127.0.0.1]) (amavis, port 10025) with LMTP id qyvXNto7vnsP; Thu, 4 Jul 2024 12:31:39 +0100 (WEST) Received: from mail1.tecnico.ulisboa.pt (mail1.ist.utl.pt [IPv6:2001:690:2100:1::b3dd:b9ac]) by smtp1.tecnico.ulisboa.pt (Postfix) with ESMTPS id 1CD016002C0D; Thu, 4 Jul 2024 12:31:39 +0100 (WEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tecnico.ulisboa.pt; s=mail; t=1720092699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sCLopPBocst09FhM/r2fltj1mn3/NPUqAr8ZWKtnZbg=; b=jjGxKYR8jUOY3okQCqJY9eSjhryazPVVTm6320He9Txoa4w9j2EWsbpCeVQYowLdUGGCIX fpyvDy6vOzr5oo8sjmR4+foVXD50++HHZdOunj6DyllsTtfsSGzKOKH41DtrgB1SSJ8OlN g+J3au7T2M1OS66CMrCCHGkV2u5KPLc= Received: from [192.168.1.53] (unknown [IPv6:2a01:14:8073:1e10:c362:ff08:aa85:54c6]) (Authenticated sender: ist187313) by mail1.tecnico.ulisboa.pt (Postfix) with ESMTPSA id F393D3600D4; Thu, 4 Jul 2024 12:31:38 +0100 (WEST) From: Diogo Ivo Date: Thu, 04 Jul 2024 12:31:20 +0100 Subject: [PATCH v4 1/7] memory: tegra: Remove periodic compensation duplicate calls Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-1-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=2068; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=9Sh3tAClsJyJKcGbDy+P6ZvkeV1elIlxANmbsLEcOjE=; b=AD0ZaqL8Q7gWiEQXRkTfsiNcXhyEX9gCb9A7PvBXNa68vSkVti4ijjA1wgJsT+l/LLQzH9Ugp F9qRjw2vvQNDXokwg5Gi7s6Ye8ObC9JN8CzBTfe/GXr/D9oNfj0FasE X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Prior to calling periodic_compensation_handler() the code is doing one extra DRAM delay reading which is unnecessary as this is already done in periodic_compensation_handler(), so remove these extra calls. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index 4cb608c71ead..9ec49ced8f91 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -492,7 +492,6 @@ static u32 tegra210_emc_r21021_periodic_compensation(st= ruct tegra210_emc *emc) }; struct tegra210_emc_timing *last =3D emc->last; unsigned int items =3D ARRAY_SIZE(list), i; - unsigned long delay; =20 if (last->periodic_training) { emc_dbg(emc, PER_TRAIN, "Periodic training starting\n"); @@ -530,18 +529,9 @@ static u32 tegra210_emc_r21021_periodic_compensation(s= truct tegra210_emc *emc) /* * 2. osc kick off - this assumes training and dvfs have set * correct MR23. - */ - tegra210_emc_start_periodic_compensation(emc); - - /* + * * 3. Let dram capture its clock tree delays. - */ - delay =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - delay *=3D 1000; - delay /=3D last->rate + 1; - udelay(delay); - - /* + * * 4. Check delta wrt previous values (save value if margin * exceeds what is set in table). */ @@ -734,11 +724,6 @@ static void tegra210_emc_r21021_set_clock(struct tegra= 210_emc *emc, u32 clksrc) EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK, 0); =20 - tegra210_emc_start_periodic_compensation(emc); - - delay =3D 1000 * tegra210_emc_actual_osc_clocks(last->run_clocks); - udelay((delay / last->rate) + 2); - value =3D periodic_compensation_handler(emc, DVFS_SEQUENCE, fake, next); value =3D (value * 128 * next->rate / 1000) / 1000000; --=20 2.45.2 From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60DFD1946C0; Thu, 4 Jul 2024 11:31:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.136.128.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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a=ed25519-sha256; t=1720092698; l=2349; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=CI423+U23IsxyiSFSw3zvfaqgjcWc651AKG92P0aInQ=; b=AzLrkKCPpGRnk35aAFGHqaFYvushJIsmhC5oOVPKuhjsUNFSlZilYer1NBaaOnHhaU3ShCfLE 3K/nTFzlUikBDjkBFoDZOXw0ptTDYr8rQPoDbdF38No4moW7Rjtkv3o X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Move the calls that instruct the RAM to capture its clock tree delays to update_clock_tree_delay() in order to avoid code duplication. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 25 +++++++++++------------= -- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index 9ec49ced8f91..a3525f3b8145 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -123,10 +123,19 @@ static u32 update_clock_tree_delay(struct tegra210_em= c *emc, int type) bool dvfs_update =3D type =3D=3D DVFS_UPDATE; s32 tdel =3D 0, tmdel =3D 0, adel =3D 0; bool dvfs_pt1 =3D type =3D=3D DVFS_PT1; + u32 temp[2][2], value, delay_us; unsigned long cval =3D 0; - u32 temp[2][2], value; unsigned int i; =20 + if (dvfs_pt1 || periodic_training_update) { + delay_us =3D tegra210_emc_actual_osc_clocks(last->run_clocks); + delay_us *=3D 1000; + delay_us =3D 2 + (delay_us / last->rate); + + tegra210_emc_start_periodic_compensation(emc); + udelay(delay_us); + } + /* * Dev0 MSB. */ @@ -409,11 +418,6 @@ static u32 periodic_compensation_handler(struct tegra2= 10_emc *emc, u32 type, (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) =20 u32 i, adel =3D 0, samples =3D next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; - u32 delay; - - delay =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - delay *=3D 1000; - delay =3D 2 + (delay / last->rate); =20 if (!next->periodic_training) return 0; @@ -447,9 +451,6 @@ static u32 periodic_compensation_handler(struct tegra21= 0_emc *emc, u32 type, __MOVAVG(next, C1D1U1) =3D 0; =20 for (i =3D 0; i < samples; i++) { - tegra210_emc_start_periodic_compensation(emc); - udelay(delay); - /* * Generate next sample of data. */ @@ -465,12 +466,8 @@ static u32 periodic_compensation_handler(struct tegra2= 10_emc *emc, u32 type, adel =3D update_clock_tree_delay(emc, DVFS_UPDATE); } =20 - if (type =3D=3D PERIODIC_TRAINING_SEQUENCE) { - tegra210_emc_start_periodic_compensation(emc); - udelay(delay); - + if (type =3D=3D PERIODIC_TRAINING_SEQUENCE) adel =3D update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); - } =20 return adel; } --=20 2.45.2 From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8F9F1A4F1C; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-3-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=1381; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=NQo0bPEs1AJu1S28vtyG+gQwwEcVWxxTjFT08hacRNI=; b=kGbfaCNOI5OSmLIu4rbJhaTP+0UwPUcNJf5PeLjLNIxaGdWZrMpbmeamkh8Q5NYJ8K4gt6Mwp WOP2HTH7d+iC3MhDgOcG5Z9YzE3og+5/UHJeVpoW8bzkodZUrYvku18 X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Fix incorrect comment on periodic_compensation_handler() as the call update_clock_tree_delay() with DVFS_UPDATE is responsible for dividing the samples accumulated up to that point and comparing the computed values with the currently programmed ones. While at it fix the indentation of a nearby comment. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index a3525f3b8145..a9e19dfa9856 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -451,18 +451,12 @@ static u32 periodic_compensation_handler(struct tegra= 210_emc *emc, u32 type, __MOVAVG(next, C1D1U1) =3D 0; =20 for (i =3D 0; i < samples; i++) { - /* - * Generate next sample of data. - */ + /* Generate next sample of data. */ adel =3D update_clock_tree_delay(emc, DVFS_PT1); } } =20 - /* - * Seems like it should be part of the - * 'if (last_timing->periodic_training)' conditional - * since is already done for the else clause. - */ + /* Do the division part of the moving average */ adel =3D update_clock_tree_delay(emc, DVFS_UPDATE); } =20 --=20 2.45.2 From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8FF01A4F39; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-4-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=3449; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=P+VIsBaToqSuZyn3oqMxbEdInj19YTcNks4MOjE3Qlo=; b=MvFk2edALOhCM64OHDzkRNHza86+WDyIOJczMKtYmRcVJWcw3KLxXRRF+2StYnuwSrjJA/n6B 7FFrKOvs2rZB10Tapg1Bb+gGiTebFMSYm5pQTCtBy4z0Yohd1QKmuYv X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Convert the macros that manipulate the delay values to interpret their index parameter as an integer to allow the introduction of loops. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 33 +++++++++--------------= ---- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index a9e19dfa9856..bfb01918270e 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -75,29 +75,29 @@ enum { * The division portion of the average operation. */ #define __AVERAGE_PTFV(dev) \ - ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] =3D \ - next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \ + ({ next->ptfv_list[(dev)] =3D \ + next->ptfv_list[(dev)] / \ next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) =20 /* * Convert val to fixed point and add it to the temporary average. */ #define __INCREMENT_PTFV(dev, val) \ - ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] +=3D \ + ({ next->ptfv_list[(dev)] +=3D \ ((val) * MOVAVG_PRECISION_FACTOR); }) =20 /* * Convert a moving average back to integral form and return the value. */ #define __MOVAVG_AC(timing, dev) \ - ((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \ + ((timing)->ptfv_list[(dev)] / \ MOVAVG_PRECISION_FACTOR) =20 /* Weighted update. */ #define __WEIGHTED_UPDATE_PTFV(dev, nval) \ do { \ int w =3D PTFV_MOVAVG_WEIGHT_INDEX; \ - int dqs =3D PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX; \ + int dqs =3D (dev); \ \ next->ptfv_list[dqs] =3D \ ((nval * MOVAVG_PRECISION_FACTOR) + \ @@ -111,7 +111,7 @@ enum { =20 /* Access a particular average. */ #define __MOVAVG(timing, dev) \ - ((timing)->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX]) + ((timing)->ptfv_list[(dev)]) =20 static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) { @@ -418,6 +418,7 @@ static u32 periodic_compensation_handler(struct tegra21= 0_emc *emc, u32 type, (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) =20 u32 i, adel =3D 0, samples =3D next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; + u32 idx; =20 if (!next->periodic_training) return 0; @@ -431,24 +432,12 @@ static u32 periodic_compensation_handler(struct tegra= 210_emc *emc, u32 type, * calibration then we can reuse the previous * frequencies EMA data. */ - __COPY_EMA(next, last, C0D0U0); - __COPY_EMA(next, last, C0D0U1); - __COPY_EMA(next, last, C1D0U0); - __COPY_EMA(next, last, C1D0U1); - __COPY_EMA(next, last, C0D1U0); - __COPY_EMA(next, last, C0D1U1); - __COPY_EMA(next, last, C1D1U0); - __COPY_EMA(next, last, C1D1U1); + for (idx =3D 0; idx < DRAM_CLKTREE_NUM; idx++) + __COPY_EMA(next, last, idx); } else { /* Reset the EMA.*/ - __MOVAVG(next, C0D0U0) =3D 0; - __MOVAVG(next, C0D0U1) =3D 0; - __MOVAVG(next, C1D0U0) =3D 0; - __MOVAVG(next, C1D0U1) =3D 0; - __MOVAVG(next, C0D1U0) =3D 0; - __MOVAVG(next, C0D1U1) =3D 0; - __MOVAVG(next, C1D1U0) =3D 0; - __MOVAVG(next, C1D1U1) =3D 0; + for (idx =3D 0; idx < DRAM_CLKTREE_NUM; idx++) + __MOVAVG(next, idx) =3D 0; =20 for (i =3D 0; i < samples; i++) { /* Generate next sample of data. */ --=20 2.45.2 From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E12C1ACE60; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-5-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=10608; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=ptSwvTf4aqcxvxz2kptb09DlC2bH1xV5LSnAO/py5O0=; b=fw1DeoEtrmKuzmNPNXAe+0aORA87N9g9X8MD38Kn0QCdliU/gpCTEtFLy2e9Bcd9SaUZjHCJ/ mz8U2lkjGWTALqrObR8HNvvUEoXUbTS/Gk9EGhn6pOqnMRjkuo8tMoI X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= As the current form of this function in a completely unrolled loop over the RAM channels roll it up two levels to improve readability. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 322 ++++++----------------= ---- 1 file changed, 67 insertions(+), 255 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index bfb01918270e..9262da658189 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -125,7 +125,7 @@ static u32 update_clock_tree_delay(struct tegra210_emc = *emc, int type) bool dvfs_pt1 =3D type =3D=3D DVFS_PT1; u32 temp[2][2], value, delay_us; unsigned long cval =3D 0; - unsigned int i; + unsigned int c, d, idx; =20 if (dvfs_pt1 || periodic_training_update) { delay_us =3D tegra210_emc_actual_osc_clocks(last->run_clocks); @@ -136,276 +136,88 @@ static u32 update_clock_tree_delay(struct tegra210_e= mc *emc, int type) udelay(delay_us); } =20 - /* - * Dev0 MSB. - */ - if (dvfs_pt1 || periodic_training_update) { - value =3D tegra210_emc_mrr_read(emc, 2, 19); - - for (i =3D 0; i < emc->num_channels; i++) { - temp[i][0] =3D (value & 0x00ff) << 8; - temp[i][1] =3D (value & 0xff00) << 0; - value >>=3D 16; - } - - /* - * Dev0 LSB. - */ - value =3D tegra210_emc_mrr_read(emc, 2, 18); - - for (i =3D 0; i < emc->num_channels; i++) { - temp[i][0] |=3D (value & 0x00ff) >> 0; - temp[i][1] |=3D (value & 0xff00) >> 8; - value >>=3D 16; - } - } - - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[0][0]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C0D0U0, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C0D0U0); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C0D0U0, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C0D0U0] - - __MOVAVG_AC(next, C0D0U0); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C0D0U0] =3D - __MOVAVG_AC(next, C0D0U0); - } - - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[0][1]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C0D0U1, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C0D0U1); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C0D0U1, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C0D0U1] - - __MOVAVG_AC(next, C0D0U1); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C0D0U1] =3D - __MOVAVG_AC(next, C0D0U1); - } - - if (emc->num_channels > 1) { - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[1][0]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C1D0U0, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C1D0U0); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C1D0U0, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C1D0U0] - - __MOVAVG_AC(next, C1D0U0); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C1D0U0] =3D - __MOVAVG_AC(next, C1D0U0); - } - + for (d =3D 0; d < emc->num_devices; d++) { if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[1][1]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C1D0U1, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C1D0U1); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C1D0U1, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C1D0U1] - - __MOVAVG_AC(next, C1D0U1); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; + /* Dev[d] MSB */ + value =3D tegra210_emc_mrr_read(emc, 2 - d, 19); =20 - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C1D0U1] =3D - __MOVAVG_AC(next, C1D0U1); - } - } - - if (emc->num_devices < 2) - goto done; - - /* - * Dev1 MSB. - */ - if (dvfs_pt1 || periodic_training_update) { - value =3D tegra210_emc_mrr_read(emc, 1, 19); - - for (i =3D 0; i < emc->num_channels; i++) { - temp[i][0] =3D (value & 0x00ff) << 8; - temp[i][1] =3D (value & 0xff00) << 0; - value >>=3D 16; - } - - /* - * Dev1 LSB. - */ - value =3D tegra210_emc_mrr_read(emc, 1, 18); - - for (i =3D 0; i < emc->num_channels; i++) { - temp[i][0] |=3D (value & 0x00ff) >> 0; - temp[i][1] |=3D (value & 0xff00) >> 8; - value >>=3D 16; - } - } - - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[0][0]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C0D1U0, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C0D1U0); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C0D1U0, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C0D1U0] - - __MOVAVG_AC(next, C0D1U0); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C0D1U0] =3D - __MOVAVG_AC(next, C0D1U0); - } + for (c =3D 0; c < emc->num_channels; c++) { + temp[c][0] =3D (value & 0x00ff) << 8; + temp[c][1] =3D (value & 0xff00) << 0; + value >>=3D 16; + } =20 - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[0][1]; - } + /* Dev[d] LSB */ + value =3D tegra210_emc_mrr_read(emc, 2 - d, 18); =20 - if (dvfs_pt1) - __INCREMENT_PTFV(C0D1U1, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C0D1U1); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C0D1U1, cval); - - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C0D1U1] - - __MOVAVG_AC(next, C0D1U1); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C0D1U1] =3D - __MOVAVG_AC(next, C0D1U1); - } - - if (emc->num_channels > 1) { - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[1][0]; + for (c =3D 0; c < emc->num_channels; c++) { + temp[c][0] |=3D (value & 0x00ff) >> 0; + temp[c][1] |=3D (value & 0xff00) >> 8; + value >>=3D 16; + } } =20 - if (dvfs_pt1) - __INCREMENT_PTFV(C1D1U0, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C1D1U0); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C1D1U0, cval); + for (c =3D 0; c < emc->num_channels; c++) { + /* C[c]D[d]U[0] */ + idx =3D c * 4 + d * 2; =20 - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C1D1U0] - - __MOVAVG_AC(next, C1D1U0); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; + if (dvfs_pt1 || periodic_training_update) { + cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); + cval *=3D 1000000; + cval /=3D last_timing_rate_mhz * 2 * temp[c][0]; + } =20 - if (tmdel > adel) + if (dvfs_pt1) + __INCREMENT_PTFV(idx, cval); + else if (dvfs_update) + __AVERAGE_PTFV(idx); + else if (periodic_training_update) + __WEIGHTED_UPDATE_PTFV(idx, cval); + + if (dvfs_update || periodic_training_update) { + tdel =3D next->current_dram_clktree[idx] - + __MOVAVG_AC(next, idx); + tmdel =3D (tdel < 0) ? -1 * tdel : tdel; adel =3D tmdel; =20 - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C1D1U0] =3D - __MOVAVG_AC(next, C1D1U0); - } - - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[1][1]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(C1D1U1, cval); - else if (dvfs_update) - __AVERAGE_PTFV(C1D1U1); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(C1D1U1, cval); + if (tmdel * 128 * next_timing_rate_mhz / 1000000 > + next->tree_margin) + next->current_dram_clktree[idx] =3D + __MOVAVG_AC(next, idx); + } =20 - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[C1D1U1] - - __MOVAVG_AC(next, C1D1U1); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; + /* C[c]D[d]U[1] */ + idx++; =20 - if (tmdel > adel) - adel =3D tmdel; + if (dvfs_pt1 || periodic_training_update) { + cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); + cval *=3D 1000000; + cval /=3D last_timing_rate_mhz * 2 * temp[c][1]; + } =20 - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[C1D1U1] =3D - __MOVAVG_AC(next, C1D1U1); + if (dvfs_pt1) + __INCREMENT_PTFV(idx, cval); + else if (dvfs_update) + __AVERAGE_PTFV(idx); + else if (periodic_training_update) + __WEIGHTED_UPDATE_PTFV(idx, cval); + + if (dvfs_update || periodic_training_update) { + tdel =3D next->current_dram_clktree[idx] - + __MOVAVG_AC(next, idx); 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Thu, 4 Jul 2024 12:31:39 +0100 (WEST) From: Diogo Ivo Date: Thu, 04 Jul 2024 12:31:25 +0100 Subject: [PATCH v4 6/7] memory: tegra: Move compare/update current delay values to a function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-6-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=6345; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=bQEGDdoI+NjnJMt3qiyjwS6JKLzg2rKDWTES38rPr/0=; b=b/3OqKGN3ea2S2QH/ajIQJhkkZ7fj6Oet7SHnugEVZqhaaTkvGueRwmBvi44nSolIqCpQMQrV XBFeSqu9qGsAZtTHSlzy6vg10aKF142BklhyyzjrHaWWXyjjlAufOMg X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Separate the comparison/updating of the measured delay values with the values currently programmed into a separate function to simplify the code. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 86 ++++++++++++-----------= ---- 1 file changed, 39 insertions(+), 47 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index 9262da658189..a8a217502f0c 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -113,19 +113,35 @@ enum { #define __MOVAVG(timing, dev) \ ((timing)->ptfv_list[(dev)]) =20 -static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) +static bool tegra210_emc_compare_update_delay(struct tegra210_emc_timing *= timing, + u32 measured, u32 idx) +{ + u32 *curr =3D &timing->current_dram_clktree[idx]; + u32 rate_mhz =3D timing->rate / 1000; + u32 tmdel; + + tmdel =3D abs(*curr - measured); + + if (tmdel * 128 * rate_mhz / 1000000 > timing->tree_margin) { + *curr =3D measured; + return true; + } + + return false; +} + +static bool update_clock_tree_delay(struct tegra210_emc *emc, int type) { bool periodic_training_update =3D type =3D=3D PERIODIC_TRAINING_UPDATE; struct tegra210_emc_timing *last =3D emc->last; struct tegra210_emc_timing *next =3D emc->next; u32 last_timing_rate_mhz =3D last->rate / 1000; - u32 next_timing_rate_mhz =3D next->rate / 1000; bool dvfs_update =3D type =3D=3D DVFS_UPDATE; - s32 tdel =3D 0, tmdel =3D 0, adel =3D 0; bool dvfs_pt1 =3D type =3D=3D DVFS_PT1; u32 temp[2][2], value, delay_us; unsigned long cval =3D 0; unsigned int c, d, idx; + bool over =3D false; =20 if (dvfs_pt1 || periodic_training_update) { delay_us =3D tegra210_emc_actual_osc_clocks(last->run_clocks); @@ -174,17 +190,9 @@ static u32 update_clock_tree_delay(struct tegra210_emc= *emc, int type) else if (periodic_training_update) __WEIGHTED_UPDATE_PTFV(idx, cval); =20 - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[idx] - - __MOVAVG_AC(next, idx); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[idx] =3D - __MOVAVG_AC(next, idx); - } + if (dvfs_update || periodic_training_update) + over |=3D tegra210_emc_compare_update_delay(next, + __MOVAVG_AC(next, idx), idx); =20 /* C[c]D[d]U[1] */ idx++; @@ -202,34 +210,25 @@ static u32 update_clock_tree_delay(struct tegra210_em= c *emc, int type) else if (periodic_training_update) __WEIGHTED_UPDATE_PTFV(idx, cval); =20 - if (dvfs_update || periodic_training_update) { - tdel =3D next->current_dram_clktree[idx] - - __MOVAVG_AC(next, idx); - tmdel =3D (tdel < 0) ? -1 * tdel : tdel; - - if (tmdel > adel) - adel =3D tmdel; - - if (tmdel * 128 * next_timing_rate_mhz / 1000000 > - next->tree_margin) - next->current_dram_clktree[idx] =3D - __MOVAVG_AC(next, idx); - } + if (dvfs_update || periodic_training_update) + over |=3D tegra210_emc_compare_update_delay(next, + __MOVAVG_AC(next, idx), idx); } } =20 - return adel; + return over; } =20 -static u32 periodic_compensation_handler(struct tegra210_emc *emc, u32 typ= e, - struct tegra210_emc_timing *last, - struct tegra210_emc_timing *next) +static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 ty= pe, + struct tegra210_emc_timing *last, + struct tegra210_emc_timing *next) { #define __COPY_EMA(nt, lt, dev) \ ({ __MOVAVG(nt, dev) =3D __MOVAVG(lt, dev) * \ (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) =20 - u32 i, adel =3D 0, samples =3D next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; + u32 i, samples =3D next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; + bool over =3D false; u32 idx; =20 if (!next->periodic_training) @@ -253,23 +252,23 @@ static u32 periodic_compensation_handler(struct tegra= 210_emc *emc, u32 type, =20 for (i =3D 0; i < samples; i++) { /* Generate next sample of data. */ - adel =3D update_clock_tree_delay(emc, DVFS_PT1); + update_clock_tree_delay(emc, DVFS_PT1); } } =20 /* Do the division part of the moving average */ - adel =3D update_clock_tree_delay(emc, DVFS_UPDATE); + over =3D update_clock_tree_delay(emc, DVFS_UPDATE); } =20 if (type =3D=3D PERIODIC_TRAINING_SEQUENCE) - adel =3D update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); + over =3D update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); =20 - return adel; + return over; } =20 static u32 tegra210_emc_r21021_periodic_compensation(struct tegra210_emc *= emc) { - u32 emc_cfg, emc_cfg_o, emc_cfg_update, del, value; + u32 emc_cfg, emc_cfg_o, emc_cfg_update, value; static const u32 list[] =3D { EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1, @@ -327,15 +326,12 @@ static u32 tegra210_emc_r21021_periodic_compensation(= struct tegra210_emc *emc) * 4. Check delta wrt previous values (save value if margin * exceeds what is set in table). */ - del =3D periodic_compensation_handler(emc, - PERIODIC_TRAINING_SEQUENCE, - last, last); - + if (periodic_compensation_handler(emc, PERIODIC_TRAINING_SEQUENCE, + last, last)) { /* * 5. Apply compensation w.r.t. trained values (if clock tree * has drifted more than the set margin). */ - if (last->tree_margin < ((del * 128 * (last->rate / 1000)) / 1000000)) { for (i =3D 0; i < items; i++) { value =3D tegra210_emc_compensate(last, list[i]); emc_dbg(emc, EMA_WRITES, "0x%08x <=3D 0x%08x\n", @@ -516,11 +512,7 @@ static void tegra210_emc_r21021_set_clock(struct tegra= 210_emc *emc, u32 clksrc) EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK, 0); =20 - value =3D periodic_compensation_handler(emc, DVFS_SEQUENCE, fake, - next); - value =3D (value * 128 * next->rate / 1000) / 1000000; - - if (next->periodic_training && value > next->tree_margin) + if (periodic_compensation_handler(emc, DVFS_SEQUENCE, fake, next)) compensate_trimmer_applicable =3D true; } =20 --=20 2.45.2 From nobody Mon Feb 9 19:55:40 2026 Received: from smtp1.tecnico.ulisboa.pt (smtp1.tecnico.ulisboa.pt [193.136.128.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CA21ACE7B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240704-tegra210_emcfreq-v4-7-3e450503c555@tecnico.ulisboa.pt> References: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> In-Reply-To: <20240704-tegra210_emcfreq-v4-0-3e450503c555@tecnico.ulisboa.pt> To: Krzysztof Kozlowski , Thierry Reding , Jonathan Hunter Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, Diogo Ivo X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1720092698; l=6209; i=diogo.ivo@tecnico.ulisboa.pt; s=20240529; h=from:subject:message-id; bh=g+KvgiUFmd9xrj0l0ct8gTjWVRQg4/KONtBXm9V0EdM=; b=o3h1BP1nd1LimKWsCKyCJHCy8F6a2OxrF5lvQgCYApWu3yxhYXFs+kPO4/QIJAVGkfwGTVOMb VgkMa7kMm1XBc3iOhietfWvBdlOUUiSMVSPo5SAIv2eY/hXogdGeocE X-Developer-Key: i=diogo.ivo@tecnico.ulisboa.pt; a=ed25519; pk=BRGXhMh1q5KDlZ9y2B8SodFFY8FGupal+NMtJPwRpUQ= Further streamline this function by moving the delay post-processing to the callers, leaving it only with the task of returning the measured delay values. Signed-off-by: Diogo Ivo --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 122 ++++++++++------------= ---- 1 file changed, 48 insertions(+), 74 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory= /tegra/tegra210-emc-cc-r21021.c index a8a217502f0c..a30a646ec468 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -105,7 +105,7 @@ enum { next->ptfv_list[w])) / \ (next->ptfv_list[w] + 1); \ \ - emc_dbg(emc, EMA_UPDATES, "%s: (s=3D%lu) EMA: %u\n", \ + emc_dbg(emc, EMA_UPDATES, "%s: (s=3D%u) EMA: %u\n", \ __stringify(dev), nval, next->ptfv_list[dqs]); \ } while (0) =20 @@ -130,93 +130,53 @@ static bool tegra210_emc_compare_update_delay(struct = tegra210_emc_timing *timing return false; } =20 -static bool update_clock_tree_delay(struct tegra210_emc *emc, int type) +static void tegra210_emc_get_clktree_delay(struct tegra210_emc *emc, + u32 delay[DRAM_CLKTREE_NUM]) { - bool periodic_training_update =3D type =3D=3D PERIODIC_TRAINING_UPDATE; - struct tegra210_emc_timing *last =3D emc->last; - struct tegra210_emc_timing *next =3D emc->next; - u32 last_timing_rate_mhz =3D last->rate / 1000; - bool dvfs_update =3D type =3D=3D DVFS_UPDATE; - bool dvfs_pt1 =3D type =3D=3D DVFS_PT1; - u32 temp[2][2], value, delay_us; - unsigned long cval =3D 0; + struct tegra210_emc_timing *curr =3D emc->last; + u32 rate_mhz =3D curr->rate / 1000; + u32 msb, lsb, dqsosc, delay_us; unsigned int c, d, idx; - bool over =3D false; + unsigned long clocks; =20 - if (dvfs_pt1 || periodic_training_update) { - delay_us =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - delay_us *=3D 1000; - delay_us =3D 2 + (delay_us / last->rate); + clocks =3D tegra210_emc_actual_osc_clocks(curr->run_clocks); + delay_us =3D 2 + (clocks / rate_mhz); =20 - tegra210_emc_start_periodic_compensation(emc); - udelay(delay_us); - } + tegra210_emc_start_periodic_compensation(emc); + udelay(delay_us); =20 for (d =3D 0; d < emc->num_devices; d++) { - if (dvfs_pt1 || periodic_training_update) { - /* Dev[d] MSB */ - value =3D tegra210_emc_mrr_read(emc, 2 - d, 19); - - for (c =3D 0; c < emc->num_channels; c++) { - temp[c][0] =3D (value & 0x00ff) << 8; - temp[c][1] =3D (value & 0xff00) << 0; - value >>=3D 16; - } - - /* Dev[d] LSB */ - value =3D tegra210_emc_mrr_read(emc, 2 - d, 18); - - for (c =3D 0; c < emc->num_channels; c++) { - temp[c][0] |=3D (value & 0x00ff) >> 0; - temp[c][1] |=3D (value & 0xff00) >> 8; - value >>=3D 16; - } - } + /* Read DQSOSC from MRR18/19 */ + msb =3D tegra210_emc_mrr_read(emc, 2 - d, 19); + lsb =3D tegra210_emc_mrr_read(emc, 2 - d, 18); =20 for (c =3D 0; c < emc->num_channels; c++) { /* C[c]D[d]U[0] */ idx =3D c * 4 + d * 2; =20 - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[c][0]; - } - - if (dvfs_pt1) - __INCREMENT_PTFV(idx, cval); - else if (dvfs_update) - __AVERAGE_PTFV(idx); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(idx, cval); + dqsosc =3D (msb & 0x00ff) << 8; + dqsosc |=3D (lsb & 0x00ff) >> 0; =20 - if (dvfs_update || periodic_training_update) - over |=3D tegra210_emc_compare_update_delay(next, - __MOVAVG_AC(next, idx), idx); + /* Check for unpopulated channels */ + if (dqsosc) + delay[idx] =3D (clocks * 1000000) / + (rate_mhz * 2 * dqsosc); =20 /* C[c]D[d]U[1] */ idx++; =20 - if (dvfs_pt1 || periodic_training_update) { - cval =3D tegra210_emc_actual_osc_clocks(last->run_clocks); - cval *=3D 1000000; - cval /=3D last_timing_rate_mhz * 2 * temp[c][1]; - } + dqsosc =3D (msb & 0xff00) << 0; + dqsosc |=3D (lsb & 0xff00) >> 8; =20 - if (dvfs_pt1) - __INCREMENT_PTFV(idx, cval); - else if (dvfs_update) - __AVERAGE_PTFV(idx); - else if (periodic_training_update) - __WEIGHTED_UPDATE_PTFV(idx, cval); + /* Check for unpopulated channels */ + if (dqsosc) + delay[idx] =3D (clocks * 1000000) / + (rate_mhz * 2 * dqsosc); =20 - if (dvfs_update || periodic_training_update) - over |=3D tegra210_emc_compare_update_delay(next, - __MOVAVG_AC(next, idx), idx); + msb >>=3D 16; + lsb >>=3D 16; } } - - return over; } =20 static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 ty= pe, @@ -228,8 +188,8 @@ static bool periodic_compensation_handler(struct tegra2= 10_emc *emc, u32 type, (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) =20 u32 i, samples =3D next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; + u32 delay[DRAM_CLKTREE_NUM], idx; bool over =3D false; - u32 idx; =20 if (!next->periodic_training) return 0; @@ -252,16 +212,30 @@ static bool periodic_compensation_handler(struct tegr= a210_emc *emc, u32 type, =20 for (i =3D 0; i < samples; i++) { /* Generate next sample of data. */ - update_clock_tree_delay(emc, DVFS_PT1); + tegra210_emc_get_clktree_delay(emc, delay); + + for (idx =3D 0; idx < DRAM_CLKTREE_NUM; idx++) + __INCREMENT_PTFV(idx, delay[idx]); } } =20 - /* Do the division part of the moving average */ - over =3D update_clock_tree_delay(emc, DVFS_UPDATE); + for (idx =3D 0; idx < DRAM_CLKTREE_NUM; idx++) { + /* Do the division part of the moving average */ + __AVERAGE_PTFV(idx); + over |=3D tegra210_emc_compare_update_delay(next, + __MOVAVG_AC(next, idx), idx); + } } =20 - if (type =3D=3D PERIODIC_TRAINING_SEQUENCE) - over =3D update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); + if (type =3D=3D PERIODIC_TRAINING_SEQUENCE) { + tegra210_emc_get_clktree_delay(emc, delay); + + for (idx =3D 0; idx < DRAM_CLKTREE_NUM; idx++) { + __WEIGHTED_UPDATE_PTFV(idx, delay[idx]); + over |=3D tegra210_emc_compare_update_delay(next, + __MOVAVG_AC(next, idx), idx); + } + } =20 return over; } --=20 2.45.2