From nobody Fri Dec 19 14:13:29 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B80C173359 for ; Wed, 3 Jul 2024 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002564; cv=none; b=rvWhWBmR1i5ibqi4Od4KYwg97oHmrhsdjGDmItoDSMIr07gMdfusil0w7hvv07fozxNEIklnP9dqms4Fou+YkX/Shp1q96SQLYXGeoqF89RoUXxUMCSdPWkywYBpt5GalrpuIGQadmTnq3UNCjxSDlPoVlfFsI05/sHfzKKLQv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002564; c=relaxed/simple; bh=3rEXWlY0rh1GCbsY2rROmJ2mJJST1jTZne/ZMrfSbeU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wc//g+V7IpDBH1bIm7lAX8W1DdfuLuF8qJbVW8y0mSB4d5api415pNNi9ZNQ8gaHut9J55oaZ9yCSlZykItWBTnbcLoSNo2nNeohvCmis24zcgnX3KcwIOeCqZKNYsjDGhJ5+KdrvhMJ2e0y7RC+4/VhWv7LDLKDsro+gywwiEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=A4jUYjYL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="A4jUYjYL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002563; x=1751538563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3rEXWlY0rh1GCbsY2rROmJ2mJJST1jTZne/ZMrfSbeU=; b=A4jUYjYLwf/kvIvjtohMLVX3GyybVj5MsztojQKSY6xuJJRTCaDv05Xc O0QZ/pQCLQ2VSruQVw1T/S5FJww6dFDNfOnGrWNbRIC6CRwbrwcXg0QWr rRBXzSl5oA1AGXLsc9VQuFuB2tg4UdfaHXyJn4foUdhnfjutAH425ZBj+ Xj8EkH7oAkV3wPegARniDf9Imi/X6r0TNHBmT3ysT7NAwrXMax5j+iys9 yFCS9sazz7L3b+QutBJNv8Ofy/0gZsq2fVS2rueQFjJO+8D2FbI+0l6Sz C5cdThuqIaOxiHInMSr0k/ZKcGjDwhvJRnPei9I3fph7Y0/HFdGd1RFnf w==; X-CSE-ConnectionGUID: fwe4YiXZSfmRHS8m80mboA== X-CSE-MsgGUID: szejZaXRRciAKp6ys2/ufA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414919" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:15 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:12 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v5 23/27] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Wed, 3 Jul 2024 15:59:09 +0530 Message-ID: <20240703102909.196459-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add config flag for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Removed the unused SDRAMC flag --- arch/arm/mach-at91/Kconfig | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..344f5305f69a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,27 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC =20 +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" =20 config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +171,7 @@ config ATMEL_CLOCKSOURCE_PIT =20 config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SO= C_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +182,7 @@ config ATMEL_CLOCKSOURCE_TCB =20 config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or --=20 2.25.1