From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED411143744; Wed, 3 Jul 2024 10:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002406; cv=none; b=Tolw7GdsZhA5doVyPVenI7g0vVU34X+Kk8z0xdbuYfKY+XC1qn0UI3Qh+ZDcejooK4QA4CJ/zkbtSSHNLJj2Pz9ghWG8j/Alc7u8z16xsGXq71MA5zBsAZsX1qZ5AtEG+Y8y5ModjVrfIPhNzYnAZ5kX/VTubZunMiOlqb21Huk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002406; c=relaxed/simple; bh=OZONZC0L9/k87HW5rUnW1mTWkoq/e2Ggm9W9MinqYHw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K6J1iMFgvtucXFebDbZzDxfsE3bv44QavH5iEVAwAosbFLC770fKXtH6fl6TLFzocpa3uuxR/eCdmNI3RTXLbxtUNwABNVCKt7BfOcnJr8641ZQZZn93+f5wf2eA66LKkh3b75DOArHnnGFUFUkQbiniOFV0QlpIhGhnQD/F7IE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=z7WlH21t; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="z7WlH21t" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002404; x=1751538404; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OZONZC0L9/k87HW5rUnW1mTWkoq/e2Ggm9W9MinqYHw=; b=z7WlH21tUt2SfUpQcvO7Q7/l3PoLJuno4QXrn2MGP/lA3yRIvZPGs0yQ UcZpoDwM8bkYhW2K8K+eQfXWbVFbbh5ZwrarXCVuPwL7fOYqOu/o5O79B THcrhX8Q+MD6tKNHPTxtlxUxmE12Wahs3Ocd9nBoJOoMJFeN/mocXxFsC 2+iZytJj7fMu0oEFtoE+YYGOksUJkIZ2ZMMauGWH1ZGtzoN+NNzFRkgQj B8DJuEbN7K7IZK+tMF2muicXwmGKA4+Os4CIPaqytd1rE+TFkuKG7o58p uwIFZS2IaUIbpWR+dx154aEplCBYUfmfrot51c3owdCylS58fvdfN0tgl Q==; X-CSE-ConnectionGUID: Pkzf6S+tQ2Ka0F87qiXpUQ== X-CSE-MsgGUID: tETn17lJQ2yW9FQYd1PnBQ== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414851" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:26:43 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:26:30 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:26:26 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v5 01/27] dt-bindings: atmel-sysreg: add sam9x7 Date: Wed, 3 Jul 2024 15:56:21 +0530 Message-ID: <20240703102621.195333-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add RAM controller & SFR DT bindings. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Docu= mentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..1339298203c6 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,8 @@ PIT Timer required properties: shared across all System Controller members. =20 PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or + "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", - "microchip,sama7g5-uddrc" + "microchip,sama7g5-uddrc", + "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc". - reg: Should contain registers location and length =20 Examples: @@ -63,6 +65,7 @@ required properties: "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon". - reg: Should contain registers location and length =20 sfr@f0038000 { --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAFD9142904; Wed, 3 Jul 2024 10:27:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002433; cv=none; b=JYUSyTr63WCKcTKJZFC6yiVnp0S3xi0o5BUco4XWSRhL0Sf77hOQHLj+TUgiFjTp+7eG+j2H6LVUef2Dc/v1vV0AFolUbTpM1K8vHfL5TIfSUgjUFRjHxqg1kFPzyMq0ssPRZ+D8FHXmR3mCSgirALiZUxxjg9CfPlh4dJDH6+4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002433; c=relaxed/simple; bh=xw6HVneEx8JYTYqdGhN1CmrkEfyjnYCH2FyHmFQQEfw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oWCkpEG1YDiN9un0P2SLPrM3W5Xj8yAuthNdx+2qxuP2dnOTWu582haatgcvWTB8TlDhABCkrO+BwwlwDD79zxYoJKdcyhF9viJsLAexP4/wboZ2KAuqGtHbl5KpZvtSXJg0s1nYs3N1SREd3y6F0vqCVJ0lEXMFOrVqkNI1KmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hWkPTwx3; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hWkPTwx3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002432; x=1751538432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xw6HVneEx8JYTYqdGhN1CmrkEfyjnYCH2FyHmFQQEfw=; b=hWkPTwx366GCT5D0J9SbwUpJeu0ZYwwFvDLxiMvIYTkVaOFaBN0gFtZN qCEfzvNuaToheqrv+RMQ5Y5ImXN02madsKUawxk+mGlr8PHUT0UC7eb+9 HOOBbf55hCrYHcO9V0UI2lo0jOXuhRTQVT3yglqv3pG2JUNQTw0V8kSiw UkLxWdkQWlr1j+iNNwmP3nslv+YZs8RkVLAqHTfEhUhdaq6cUHZSg1/+l DdPdZX4WTAQfdeEOK6RfVqdhECR6EYQDqhgN2NthD13/93WdQhTyKtn6C RL4w0uIQFBL0YwU1wG5kJVullAhdp74vz2oKNxFHFvoKS9MiJxs7BH+Ss Q==; X-CSE-ConnectionGUID: w0yhcqfIRYGSYZjuOSPU/g== X-CSE-MsgGUID: Q9GYbNYbSfqnPTiWe75Yzw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804703" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:26:40 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:26:36 -0700 From: Varshini Rajendran To: , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v5 02/27] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc Date: Wed, 3 Jul 2024 15:56:30 +0530 Message-ID: <20240703102630.195382-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add microchip,sam9x7-ssc to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documen= tation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ =20 Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9660156F28; Wed, 3 Jul 2024 10:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002436; cv=none; b=KftILbeyW1yq+p3n/inD0QWUkTP7ULS1kCPj6NcrR41o8TdEzcaB9MCA5iY4/hnsYBWOwJAVy2tIVkMDonkfv3nPow1gPAgp4QbbzA7JcKjtGzAWfIUxCSEGy9wSv4344iWZ3uFK24R3W+HO30xRO3zfqQ+S8fRYtm4gWz1q8GM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002436; c=relaxed/simple; bh=CFC7z8WmsZSF958vPpbokrnZvgzbxwMA/ZoZqH+Ywdg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TIIGyAdN0+trO9gyj70Q87MWerBsxCMoVt58ikoCHOC5xyKd5VdlOFNEV8DpDVK9ZBj+/Tea7QPHGGnwwyv3zHVLaCpo2yXwpqf2HCF+5qWH8XjZQ40kqpUWg29cJrilrLezkVqtm7ytimc1wWg+DGlS6H54865VOBEyGADy7n0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OKjcONkG; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OKjcONkG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002435; x=1751538435; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CFC7z8WmsZSF958vPpbokrnZvgzbxwMA/ZoZqH+Ywdg=; b=OKjcONkGY4C+S9PqeXUtlNFafYuCBOzdwuiUVM3GCrNI3Tq1WeXn/1PS K1TXcghMg32mjTRGAJcShayIc1ADZtBVibu7Sw0xyTmJ8fHQmrD7Hoh2P fzMpUl86BV1ZIOt9u4tELph2ljzCdccJYZIaYvZGRO2JXRoZJrmSIeJKF 8TNEgwVMHs/sbO/YyqsNzqSy3iVPb/vbmSl9jgteqZaTx7k8cozJ1uYm6 F2+0ncGJn9BOZG87oOgP3qhELyF7o6ZmuBLu2njVbiNq6eWfMSbNgnroD FvDYvYz7y+XDCdWVxLp267OW2Q28pdzhyGExZwhhe3WhBKIor3CCUAL5o g==; X-CSE-ConnectionGUID: O6jm4qbsRBydYsAuvGKY7w== X-CSE-MsgGUID: gkzCGrK9TGucj+i2z/6ZOA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28772333" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:26:52 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:26:47 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , CC: Subject: [PATCH v5 03/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7. Date: Wed, 3 Jul 2024 15:56:40 +0530 Message-ID: <20240703102640.195431-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sam9x7 compatible to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v5: - Corrected the order of bindings. - sam9x60 bindings in the dts and dt documentation in future series. --- .../devicetree/bindings/serial/atmel,at91-usart.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index eb2992a447d7..f466c38518c4 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -23,13 +23,20 @@ properties: - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart - items: - - const: microchip,sam9x60-usart + - enum: + - microchip,sam9x60-usart + - microchip,sam9x7-usart - const: atmel,at91sam9260-usart - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart - const: atmel,at91sam9260-dbgu - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x7-dbgu + - const: atmel,at91sam9260-dbgu + - const: microchip,sam9x7-usart + - const: atmel,at91sam9260-usart =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A87B15CD7A for ; Wed, 3 Jul 2024 10:27:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002452; cv=none; b=QMHikbJ0saMWQSznl0M28R4FwwaWHcdVKDco88xjO0Bob46P6RnOE7cyA+lBsJAuJb2AadEts5TMkFQkzUvD8b9QYrnwvJzo5S0mTZMZtpGg7DRtyzt7z9b+NSfMM6uEhrBdfRJUl+25KSUrV+mGPbuPy2fg67xJHUgv+dU3v4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002452; c=relaxed/simple; bh=tF97RZEDc1Pj4JTtRtwDGPy7ecJ57nNiFKkGjXuJBrc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jufaX9bQUO7q8rTXpbJlQRsdG+JmmcBSNgFb/VR91dayX+SHOcmfUWD53yjbywgxSxSaLzKsRh0fuLTdO2UGPa0wO/7ASCSQatNlRFq6vvinXJZ3HDr1p6kPb2CMLsNtBs4p0uqnPSpNkNB0feUc37HIAg95Hb5DFegMrefwAek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sfc73m6k; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sfc73m6k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002451; x=1751538451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tF97RZEDc1Pj4JTtRtwDGPy7ecJ57nNiFKkGjXuJBrc=; b=sfc73m6kQFhVY7SzM9JMNo9J0tDNyjKuyaAT74sNGxkU762mkQaDMOJ8 68lB4IEt5L2oaanGOmXc3Od8+yd4KXrZiYz0eqGNgpxasFCL3HgMOcDTI xf0VHuo4OoaNYJ+hC+Ao/IeIxFGXLcysKRyKwNGWI5x0tTxVrvZUR+ABB SMvjauTLHyPzTiGnPV7TGrZw8MoeQbL6+alHpyJC+KgNoPX/AK9F28NqB /ZvVoDqSKYg+H3j/9610Aj+ZRaK1zM1eNlrbctGRaHi/gsZinm6j7MOCI sqketoxeu4hsiI1P2nPaMFrM2pDUuTH3ZGIbRuDOaw1xBo8TI1iPKMp/Q Q==; X-CSE-ConnectionGUID: sY2/M6/DSDaC/EbwViKWug== X-CSE-MsgGUID: rdX+l/tcQMyaUKXtMabirg== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414857" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:02 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:26:59 -0700 From: Varshini Rajendran To: , , , , , CC: , Claudiu Beznea Subject: [PATCH v5 04/27] ARM: at91: pm: add support for sam9x7 SoC family Date: Wed, 3 Jul 2024 15:56:53 +0530 Message-ID: <20240703102653.195483-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support and pm init config for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Removed usb related ids. - Added sam9x7 specific rtc, rtt compatibles instead of sam9x60. - Removed gmac id. - Removed a blank line. --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 345b91dc6627..c0c861e1b8c1 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -233,6 +233,13 @@ static const struct of_device_id sama7g5_ws_ids[] =3D { { /* sentinel */ } }; =20 +static const struct of_device_id sam9x7_ws_ids[] =3D { + { .compatible =3D "microchip,sam9x7-rtc", .data =3D &ws_info[1] }, + { .compatible =3D "microchip,sam9x7-rtt", .data =3D &ws_info[4] }, + { .compatible =3D "microchip,sam9x7-gem", .data =3D &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1362,6 +1369,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, + { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, { /* sentinel */ }, }; =20 @@ -1499,6 +1507,27 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; } =20 +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst =3D { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + ret =3D at91_dt_ramc(false); + if (ret) + return; + + at91_pm_init(NULL); + + soc_pm.ws_ids =3D sam9x7_ws_ids; + soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; +} + void __init at91sam9_pm_init(void) { int ret; --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1D6B16F84F for ; Wed, 3 Jul 2024 10:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002439; cv=none; b=Zjzb14L/Qqk5NFIes4V7wn8uurWmQeoH3YEwEHRy6kjgkMs2xPjanlAg/bQNDYlGk5SCO8Nx1TG2T6H7K0PyVaOwB8sbh7kbzgjjEYWZ6RagUxpJhW4KHvHG8V9eTYWdlD+Jz417hR0dVVIKRaSDaqsqpJK5eYOuftlYOByDPf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002439; c=relaxed/simple; bh=Lv0sEaA8F2c8HiyRvT8WYHleiLqbWNB02c+WFOle1GY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TLRWEvGt/TBHt2SkhwDN/UfqWa68SL8qBhIlKfR34TzIYEEqbkiKjfGq6ObZjMNCiw3BDJShMOCT+XvFFQjKOyaitImFIFEU3HNwk0p+AMWckYNTAfPqAYX8lM1vpf4BaRZmJNiZXxl3Hs0NPlOpucaBGmf3JpS+cV9vMYdAFyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=XxkdtgM7; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="XxkdtgM7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002436; x=1751538436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lv0sEaA8F2c8HiyRvT8WYHleiLqbWNB02c+WFOle1GY=; b=XxkdtgM7fvcat09cgdO4MlmqijBW8QyI1coXQ2qc1g0AOe0PwP/SPNKX rDbJ78+A5J9tCMLrGYPGs1OwLjXVJ5j+jjY1310CkFu0M9YYDHZbhY/Mj sYVZsmx+fkhlHpf6JXKV7DIVlY8QxCNBIwSV/HHwlXsB6/B8WUrfGUIKT ZS+thcaxnewhiVjUudLMG3PR4XhKVY0nvgyKNH0YgN7MM1dcD8MvgyqlP SZRWPTRdlwFdgrCKFv4XdRJHHBEHcV6YJviDt9q8crNwU+z57Q7Ym6apI zoC54EhZ7iCVCloRtP6+z83rOC3845CRGtd8Qs7pJSqAZwJH4NSj1ntBc A==; X-CSE-ConnectionGUID: O6jm4qbsRBydYsAuvGKY7w== X-CSE-MsgGUID: LzxUdgSRQ8uM9Ewfl3OogQ== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28772336" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:08 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:05 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v5 05/27] ARM: at91: pm: add sam9x7 SoC init config Date: Wed, 3 Jul 2024 15:57:02 +0530 Message-ID: <20240703102702.195564-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SoC init config for sam9x7 family. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Removed unnecessary header file. - Added a space in the return type for clarity. --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) +=3D at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5) +=3D sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) +=3D sama7.o obj-$(CONFIG_SOC_SAMV7) +=3D samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..e1ff30b5b09b --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x7_pm_init(); +} + +static const char * const sam9x7_dt_board_compat[] __initconst =3D { + "microchip,sam9x7", + NULL +}; + +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7") + /* Maintainer: Microchip */ + .init_machine =3D sam9x7_init, + .dt_compat =3D sam9x7_dt_board_compat, +MACHINE_END --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 670AA167DBD for ; Wed, 3 Jul 2024 10:27:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002455; cv=none; b=bxWxc5DpGf5/MqUq6zSCQ01lkTP2ro6z9bB40kC3Hxl+0xgkZdgWVQonUritT7MertTEY3T5gE+FgeNro7kFF1h53bWScIuTPUfjMr4PFb0S9VXIA/gWpLoC11xApsOWU0ttCiWedMpRA3s8hNTMV4nN3i6x0S4CzUkVQdDAiCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002455; c=relaxed/simple; bh=3KQ5c+sR4gULel13+dJgDCHrPyjdJPoEAjnMltcY90w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Qv02e5CVTYZdoTeKP530V4DUTzijnPA2telUUV75EYfsJI2qxhAQDkrTz4vhMSLKsiRn4uYQtdmtWMCFBPA1ViHYxSDY/zXoEez0qsIWzkKRkUJedUS5Qah4C/gdCJTIwGteAS9ygwWnJIivMurkYIT6u6BooAUYpTpob+/Qp74= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NFQO5vSX; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NFQO5vSX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002454; x=1751538454; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3KQ5c+sR4gULel13+dJgDCHrPyjdJPoEAjnMltcY90w=; b=NFQO5vSXLAxaAf20TAuXHJ2TkzRd4vkOF0G4kKyLbTp0m2mHyGgA0vxJ YQdBHl5BvkvP5mZBwl6WO3utKtDsqyOz0SbrRrdpWcNSTdjaE8Q8dAWiZ ZJgYa9TnG56P/Ae+gvOl0CTxfCXaiBYWl/DISewjgD4IoqGSyvzW7Ciqz mcD8P7s77F/n3XVvqviGm6imCAVwUviTTZBVx2z+DMITBTpEjA4swDi8e 7cWkKmcg6t2L5FwBmH1rJeAiLLe/PDIK7LcALTEJty9dBzbF8au7MpiZY zXP2KmWBXbKQYdk7MNNSju7ohg2BB/pezq13Vi2G6JJYySZsCscwr2Kaw g==; X-CSE-ConnectionGUID: 6if5lKZrRRahkqLSM+7f7Q== X-CSE-MsgGUID: 5SgJzZHDRgi7Lm5DfMZR1Q== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="196197029" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:33 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:14 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:11 -0700 From: Varshini Rajendran To: , , , , , CC: Claudiu Beznea Subject: [PATCH v5 06/27] ARM: at91: add support in SoC driver for new sam9x7 Date: Wed, 3 Jul 2024 15:57:08 +0530 Message-ID: <20240703102708.195612-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for SAM9X7 SoC in the SoC driver. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Changed the RAM size in bytes. - Alphanumerically sorted the entries. - Sorted SoC entries by name and size. --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..2a42b28931c9 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst =3D { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 16MB DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 64MB DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 125MB DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 250MB DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..2c78e54255f7 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 +#define SAM9X7_CIDR_MATCH 0x09750020 #define SAMA7G5_CIDR_MATCH 0x00162100 =20 #define AT91SAM9M11_EXID_MATCH 0x00000001 @@ -66,6 +67,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAM9X60_D1G_EXID_MATCH 0x00000010 #define SAM9X60_D6K_EXID_MATCH 0x00000011 =20 +#define SAM9X70_EXID_MATCH 0x00000005 +#define SAM9X72_EXID_MATCH 0x00000004 +#define SAM9X75_D1G_EXID_MATCH 0x00000018 +#define SAM9X75_D2G_EXID_MATCH 0x00000020 +#define SAM9X75_D1M_EXID_MATCH 0x00000003 +#define SAM9X75_D5M_EXID_MATCH 0x00000010 +#define SAM9X75_EXID_MATCH 0x00000000 + #define SAMA7G51_EXID_MATCH 0x3 #define SAMA7G52_EXID_MATCH 0x2 #define SAMA7G53_EXID_MATCH 0x1 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E84F8172773; Wed, 3 Jul 2024 10:27:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002457; cv=none; b=R91ArcQK+/Jd71V788OT2qLmXiUMR4bKwo316fZGf94EZSisGLLfpYCfti404k4c/QmtWLH3a1VrPoo3KrO43RmX3ztt2Rc8UC5ZXAIWil94pzlTXn8GhZYgcbClOGIMKv1l8kU4Xjjfv6RgpCyukFlW5/vXX25bqzP7bb3RPkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002457; c=relaxed/simple; bh=oXxCxXX+oZh8HsttkMvFbmyP3JdiAor+JVZTWRVjC28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dAYGivqGpRvoiEuZjrIHI0w7kajBPpjnUYVp9jKtDU9PDTu1Im6kj37leIHb3IiXml5eXZB6NE8nR4CTlc2UsMwyzO4UAxSUn/LNAjyP9grGLJ/z2TZdhcxJj0se3eB9LcKcarDfQ/QE3BPgS5KUKfiYzpAKge5cWo2+6H9l1mM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=VvMmnWfc; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="VvMmnWfc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002455; x=1751538455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oXxCxXX+oZh8HsttkMvFbmyP3JdiAor+JVZTWRVjC28=; b=VvMmnWfc9AlC/HVwcFQ/t5jctJl//cBnq05TJxK/KWXtnVb9mJvwfGB9 69Og4yLSrFAa86GYUr37Q5KjG6987YgPJ11N/iX91pvMJncu0jeWGO/nm 0azDVXZsipdCK+r73oJax434bHTSVwpVBOtJ1yPMJpSb4RIFCeXZCXSz/ hgqW0P9lBAQkjak4yZ4HxYlBdy1IHn2TPHBHFXV+5iJLg+e934QkINZNT 2bMXsrGnJ9uG0AxwTyI1U844z5p0UvcJpaYpsSjlyfaplfLwn1nqs56SF 3R62Moy79nimfgw8SOYeqQtTKXimuhoSyQDWuQtCs6fKhVaNeUQpbPfLM A==; X-CSE-ConnectionGUID: 6if5lKZrRRahkqLSM+7f7Q== X-CSE-MsgGUID: ufnVsza6TNa7T767oet9bw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="196197031" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:27:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:22 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:17 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v5 07/27] dt-bindings: clocks: atmel,at91sam9x5-sckc Date: Wed, 3 Jul 2024 15:57:14 +0530 Message-ID: <20240703102714.195661-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for SAM9X7's slow clock controller. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: - Changed subject according to suggestion. - Alphanumerically sorted entries. - Updated Acked-by tag. --- .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.= yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml index 7be29877e6d2..c2283cd07f05 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml @@ -18,7 +18,9 @@ properties: - atmel,sama5d4-sckc - microchip,sam9x60-sckc - items: - - const: microchip,sama7g5-sckc + - enum: + - microchip,sam9x7-sckc + - microchip,sama7g5-sckc - const: microchip,sam9x60-sckc =20 reg: --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0914015B54B; Wed, 3 Jul 2024 10:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002487; cv=none; b=sMUKWIDl2LNG9LH3p3LCg8Gzx/K+B48kVQizhajyOcMg3hXzg/aCsZe/Dwm6Ds5veStHBsDbwSU48P7W4fhoXVE4MyVlvrWkV8ljXwE+aA/MiZ9FtziXozA6GcauOtOvtRYg65wjUQBIwObR3CTI3oTsDz9FTZEsXfSp1aXtKA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002487; c=relaxed/simple; bh=h2IyvQyiSXx4uAiLjaRknaqtBfAOw8HI2r50csPsnJE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NWIO28OP7xjpk8Cnsgozzptbd5yQ/JzLvB9d5mZUgv0+yZ73bNL9tAz59ky1newfVLu9Py8YXNtnLJC2F1+1p91qp4BWQCp7wvKRRPIAVcfW+AhHk6lH8ijVvGLphvgKSjZ/41PBFYPXyXfuAEAqy2ZXFd2uux/3apo64lTXixM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ARZw2sJx; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ARZw2sJx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002486; x=1751538486; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h2IyvQyiSXx4uAiLjaRknaqtBfAOw8HI2r50csPsnJE=; b=ARZw2sJxdi4/dP9vyFD50DhQG6o2uBtFwmaqFqbaFfikoajzH1PiFnZ8 2m5Gvk+PdXYt+0VCdPDCrfrecLM4B8/Gacd8i4StMdXL50/i38VeASikA azc8omj2V2k36rVWHj9kZGi208OVUuSRREYzCRp+mZKBKwGqtHv7GKIjA wMGWIuU4LTWjARqW2EZo5159T7T8l2FS1OOoEulU/iYnp0MhOXYZO7dRW /h1U3TF0Ijtf9DHymKIFOxfXBXdSxtQzvFzjxDWjngpC8EtANJ2x7bDy/ zc/UaDkra0mb4PoWDyIctpTVKtKHV3ApzKQjGtY+lp2GvFjAuxBl5DWOd g==; X-CSE-ConnectionGUID: C1sswkSrQy+pa1d+oVi69g== X-CSE-MsgGUID: cyF5/onQSqOBeMdYZP9aHw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441486" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:29 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:24 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: , Conor Dooley Subject: [PATCH v5 08/27] dt-bindings: clocks: atmel,at91rm9200-pmc Date: Wed, 3 Jul 2024 15:57:22 +0530 Message-ID: <20240703102722.195709-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for SAM9X7's pmc. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: - Changed subject according to suggestion. - Alphanumerically sorted entries. - Updated Acked-by tag. --- .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.y= aml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index c1bdcd9058ed..c9eb60776b4d 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -42,6 +42,7 @@ properties: - atmel,sama5d3-pmc - atmel,sama5d4-pmc - microchip,sam9x60-pmc + - microchip,sam9x7-pmc - microchip,sama7g5-pmc - const: syscon =20 @@ -88,6 +89,7 @@ allOf: contains: enum: - microchip,sam9x60-pmc + - microchip,sam9x7-pmc - microchip,sama7g5-pmc then: properties: --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4F2816EBEA; Wed, 3 Jul 2024 10:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002489; cv=none; b=qxlO7xUBjU+ffob1iiSKl1zQhVtoQ2iZyT0QeMmKOy9VE8DppJ9tOs2qocxvJDdhpqr0PJdLIcUdL9G9ap8ilu5Ah+/lwZF4+5Xos1UJaR7G3Z6uyuCZtlpk1xvZ6dCdSD1UjNmYOO2Jbu6RKItTQk5885Ot10DSrKOl4GlwU24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002489; c=relaxed/simple; bh=yupO65VLUPyZffIc75hdCj1FpXzK+t+KpMhOK2JtQgw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qzuKrp1VSbq/TmGBzwQtkMOfRZQIEJOXRU41vcrOiBNRBzkkDQDhaMmuadD0kW8AvszP4LOLM+BIxjPJjOgj5Q4TZh9EFXZUN2BZ3pmcQdJtsRGynkxdZKuLhTf1kbjrbHkxv4nGNoC0hmaQ2lngfnpbJy32FexwY89lleXowCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=U139RsV4; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="U139RsV4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002487; x=1751538487; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=yupO65VLUPyZffIc75hdCj1FpXzK+t+KpMhOK2JtQgw=; b=U139RsV4AJCge9LASACOAmMpBnxFtwppuwEDX+B1dKHAAFMyvp0bnyBr 8KsQmvGBP8ILHpkx4langQsdNs9cIvAkQ1MXHmtcM4B8dF4RFwN8QKR6c fFl7bPo+MXuFE6moykz315GT8Agp2Gf4XL26atuU8Tdtgb6RUhhmo5AC5 nSWWYm1FvSrQg2qVBscjqTbOeiGuzQMKUjbOVdy/Mr5XZgiVeUcdLeVc2 INABIcTsM+qmldrifhVwzJ/XKRa5FedohiB4vuj2BhIdRlEFO7/WaKJtf GTTJO6gulrjaSqLN8uNSoTj3o8cP3V1+oRbll3tv2eL2Xflwld8Ikgk8G Q==; X-CSE-ConnectionGUID: C1sswkSrQy+pa1d+oVi69g== X-CSE-MsgGUID: weBXOmxqS9y2iz1EjDTvlQ== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441488" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:33 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v5 09/27] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Date: Wed, 3 Jul 2024 15:57:29 +0530 Message-ID: <20240703102729.195762-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SAM9X7 SoC family supports different core output frequencies for different PLL IDs. To handle the same in the PLL driver, a separate parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers are aligned to the PLL driver by adding the core output freq range in the PLL characteristics configurations. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index ff65f7b916f0..b0314dfd7393 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) =20 -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 =20 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, unsigned long nmul =3D 0; unsigned long nfrac =3D 0; =20 - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; =20 /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, } =20 /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; =20 if (update) { @@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, goto free; } =20 - ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw =3D ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0f52e80bcd49..bb9da35198d9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index e309cbf3cb9a..db6db9e2073e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(plla_outputs), .output =3D plla_outputs, + .core_output =3D core_outputs, }; =20 static const struct clk_range upll_outputs[] =3D { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characte= ristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(upll_outputs), .output =3D upll_outputs, + .core_output =3D core_outputs, .upll =3D true, }; =20 diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 91b5c6f14819..e6eb5afba93d 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(cpu_pll_outputs), .output =3D cpu_pll_outputs, + .core_output =3D core_outputs, }; =20 /* PLL characteristics. */ @@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_charact= eristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(pll_outputs), .output =3D pll_outputs, + .core_output =3D core_outputs, }; =20 /* --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27FDD171085; Wed, 3 Jul 2024 10:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002489; cv=none; b=u7jPDLvy5ELxZtDCot9VmqAVK1nPkxbBK6RmrGrzRpFxMtP2e+5QnF4I2iPTWgljkHvqC4MqYoDu5GpCmVXGyodymDAMOWsSO3RULi77yQF1eBY0JCiKQiS8RW/xMMjmZ7TxHoYnuQkfsJbUgPvSbLJD9GHyVxUZurc1D5YyoyU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002489; c=relaxed/simple; bh=NycM/6GqLRtFrGB/KY1v7hoKxrqUj+TND0uXU/YfnHk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l8CM2kX7p60k/BVxX52MBJuMY3v6Kf8UVw+qp/Fk763dgKWHF+OxdyQj3HF2HBsCHMCqXwBeN5KO8d/jkkjamRDBtyLbbrNin6qBtBPuU5YbBillUrsBGAHNSauzWvokVs02QMEw8/Qxv0PpFh+jAVXHusCUlnIND+r42hfDIC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=lMn+lhYg; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="lMn+lhYg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002488; x=1751538488; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=NycM/6GqLRtFrGB/KY1v7hoKxrqUj+TND0uXU/YfnHk=; b=lMn+lhYgsMtRyqGxUevQSScM1siVVACqznmjgX4IML/Iebm951qQzpWs nQJ2TvwhLvoA7GO/Pi9Dyok7KGZiTWXz+kEJ8vf1GpG07gXfxyKcwGiD9 bKuWB07i/QnhH0gbn+/DVv8V/C3bUXjkQ89/d7X7oNtyI1PL0GLJJFQ85 PMeHK6zkMxCZDeG2TyaRHEsEOROzXyXB3iQauovtHDNzPR4J3Ecrc1Ykg if+dWFNtO4gOQ54KqHl0foRPlJ04F0XdARlaa4rz65lkqSAmPs3g5+4om 4OWVqdcBUJc/3vMeWuOgMYXpUv+MAcUqFUaL4NDE6yqo8h177h69o92to w==; X-CSE-ConnectionGUID: C1sswkSrQy+pa1d+oVi69g== X-CSE-MsgGUID: 542unQ1TRLOWZ3Tvaz8tKQ== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441489" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:05 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:43 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:39 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v5 10/27] clk: at91: sam9x7: add support for HW PLL freq dividers Date: Wed, 3 Jul 2024 15:57:36 +0530 Message-ID: <20240703102736.195810-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and 4 respectively, both have a hardware divider /2. This has to be taken into account in the software to obtain the right frequencies. Support for the same is added in the PLL driver. fcorepllack -----> HW Div =3D 2 -+--> fpllack | +--> HW Div =3D 2 ---> fplladiv2ck In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz after the hardware divider and the plladiv2 freq is 400 MHz after the hardware divider (given that the DIVPMC is 0). Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Corrected typos in commit message. - Rewrote the conditional statement. --- drivers/clk/at91/clk-sam9x60-pll.c | 30 ++++++++++++++++++++++++++++-- drivers/clk/at91/pmc.h | 1 + 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index b0314dfd7393..fda041102224 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct= clk_hw *hw, { struct sam9x60_pll_core *core =3D to_sam9x60_pll_core(hw); struct sam9x60_frac *frac =3D to_sam9x60_frac(core); + unsigned long freq; =20 - return parent_rate * (frac->mul + 1) + + freq =3D parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>=3D 1; + + return freq; } =20 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struc= t clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } =20 +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = =3D { .restore_context =3D sam9x60_div_pll_restore_context, }; =20 +static const struct clk_ops sam9x60_fixed_div_pll_ops =3D { + .prepare =3D sam9x60_div_pll_prepare, + .unprepare =3D sam9x60_div_pll_unprepare, + .is_prepared =3D sam9x60_div_pll_is_prepared, + .recalc_rate =3D sam9x60_fixed_div_pll_recalc_rate, + .round_rate =3D sam9x60_div_pll_round_rate, + .save_context =3D sam9x60_div_pll_save_context, + .restore_context =3D sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -725,10 +747,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, s= pinlock_t *lock, else init.parent_names =3D &parent_name; init.num_parents =3D 1; - if (flags & CLK_SET_RATE_GATE) + + if (layout->div2) + init.ops =3D &sam9x60_fixed_div_pll_ops; + else if (flags & CLK_SET_RATE_GATE) init.ops =3D &sam9x60_div_pll_ops; else init.ops =3D &sam9x60_div_pll_ops_chg; + init.flags =3D flags; =20 div->core.id =3D id; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index bb9da35198d9..91d1c6305d95 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -64,6 +64,7 @@ struct clk_pll_layout { u8 frac_shift; u8 div_shift; u8 endiv_shift; + u8 div2; }; =20 extern const struct clk_pll_layout at91rm9200_pll_layout; --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B130617554E; Wed, 3 Jul 2024 10:28:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002493; cv=none; b=P2qyjjvGjyrD7fo456er43ZIwAPCPP+OzEj5HFC/HmfZ1+BsbSpbywtO8Rl3+oTOSdWCFSXslrHXHb8FUnwdCBp2nZVyv7EMr7euTpRemLcZ5IGyPG7aI22y4vWvu4/UcRuuI/EEffeBIHFq0O02lCM9q4/poSY9grDkASC5kf8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002493; c=relaxed/simple; bh=f1dps+oGiDe/KHzYb18t8lFz4154pwNNCSulv4GCbrs=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AHaNIe/F5KjMlvVGO89oj+MFySkWlbbx0Vaz0MhP4Q4i96HiMWkT9/GG9AcYzWhzFsp8Y2Yc7MmtnlQa8ATF8qXI5piik31jqNMCK5kvXOQxYuIlKDxVtNjHz/1OWLbZpnFRnYfZnf7oAd9r2KpJBRrdNH8sNLJ1drymcSFv2rE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hHUkGnc4; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hHUkGnc4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002492; x=1751538492; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=f1dps+oGiDe/KHzYb18t8lFz4154pwNNCSulv4GCbrs=; b=hHUkGnc4oCaZJIu56QKUqICQDqofEIYNAFEvXdqrvNy+1s+uPdob1I1+ ZfzVvAWkS25w2VT1snMCWWrGLRNx0jkGX7sUXyEm6Up5sjXLynNNxxDIL l1EN0oQ0CM1xImgNWJVSlWLs60RD0GUoTQ58pNlLEtUzJKhF475bGUQKn cv1zLnWHxdAFGcbn1A3+itVpXfIg91t6+0SSDi/hIiZN4RDuGV7xT6oqV 20/xISbNpAdQWwj8FvK7I/7Uez/AiMJo5zRaHmA60kZV8x5m9H7+uaEML aL9QSwfHDrCtooRS37tmVqoMo4z/e62fCodQHw4cxow7Ou/R4/HlYofK4 g==; X-CSE-ConnectionGUID: zAkMoDX+T3uCd+MLD1u0xA== X-CSE-MsgGUID: IM/BieWZRxmhDsd3pr44FA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804743" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:11 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:27:49 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:46 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v5 11/27] clk: at91: sama7g5: move mux table macros to header file Date: Wed, 3 Jul 2024 15:57:43 +0530 Message-ID: <20240703102743.195858-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the mux table init and fill macro function definitions from the sama7g5 pmc driver to the pmc.h header file since they will be used by other SoC's pmc drivers as well like sam9x7. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- drivers/clk/at91/pmc.h | 16 ++++++++++++++++ drivers/clk/at91/sama7g5.c | 35 ++++++++++------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 91d1c6305d95..4fb29ca111f7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -121,6 +121,22 @@ struct at91_clk_pms { =20 #define ndck(a, s) (a[s - 1].id + 1) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1) + +#define PMC_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) \ + (_table)[_i] =3D _i; \ + } while (0) + +#define PMC_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) { \ + (_to)[_i] =3D (_from)[_i]; \ + } \ + } while (0) + struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsyste= m, unsigned int nperiph, unsigned int ngck, unsigned int npck); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e6eb5afba93d..6706d1305baa 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -16,21 +16,6 @@ =20 #include "pmc.h" =20 -#define SAMA7G5_INIT_TABLE(_table, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) \ - (_table)[_i] =3D _i; \ - } while (0) - -#define SAMA7G5_FILL_TABLE(_to, _from, _count) \ - do { \ - u8 _i; \ - for (_i =3D 0; _i < (_count); _i++) { \ - (_to)[_i] =3D (_from)[_i]; \ - } \ - } while (0) - static DEFINE_SPINLOCK(pmc_pll_lock); static DEFINE_SPINLOCK(pmc_mck0_lock); static DEFINE_SPINLOCK(pmc_mckX_lock); @@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, + sama7g5_mckx[i].ep_count); for (j =3D 0; j < sama7g5_mckx[i].ep_count; j++) { u8 pll_id =3D sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7g5_mckx[i].ep[j].pll_compid; =20 tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_mckx[i].ep_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, num_parents, NULL, parent_hws, mux_table, @@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) if (!mux_table) goto err_free; =20 - SAMA7G5_INIT_TABLE(mux_table, 3); - SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); + PMC_INIT_TABLE(mux_table, 3); + PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, + sama7g5_gck[i].pp_count); for (j =3D 0; j < sama7g5_gck[i].pp_count; j++) { u8 pll_id =3D sama7g5_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7g5_gck[i].pp[j].pll_compid; =20 tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; } - SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_gck[i].pp_count); + PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, + sama7g5_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0E0143C6B; Wed, 3 Jul 2024 10:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002490; cv=none; b=BS4+RVtUxYM6UlfTq9b1BDKIoyuJezF5K+pNf/a4JgZYXgMrhIJPHmw1emMrJqBO55aei2wry7VWSZjG0SqRUf4aJB+7rwmofBrRWRuqb3cP7h6yMMH/ekqYItbxoNxH+QvgSDJsqVq+FWxdnglm7SY4Co1qlAUqQJ2+Gip2cxM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002490; c=relaxed/simple; bh=d+NaFbiFI1ORWu1Rz4SBsOdh7lHDtqOtupPY4l7As28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QrZNBjt8QEFXcpuI8GPnAhkXo1t5mCs9X7hibVGmZd0rJwHT3Vo2NEC/zcB0EttKFLiUQ+GAx7fwJFQgYPLTqMHOsChWzog+/jCntYZPX0NB2DEWYqL/DYGW0AA0u1ut2v20OqfLQYNAzDqaR4PaYfK2Cp+TeHh+bo/w9lEDjzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Z+jLPCfU; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Z+jLPCfU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002489; x=1751538489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d+NaFbiFI1ORWu1Rz4SBsOdh7lHDtqOtupPY4l7As28=; b=Z+jLPCfUvSL0/kAR+CKGB+no0hlBjsP3P9ZxIdcUHSw1wTZw/EkRC3xe sRtAZkyZbeB8NOTLH9ihaMXMvqpI/gGdaAuTT0JqSWd2FCPNZl9VFAyJZ 9yx3eQL58lXfuOQRNY3lyoxk2by/xZLRB1HuHrcZX/D3d1OkqhOk+aaHc Hd+qnidB7c+YPa8ML/F5r7tr2yBrmH6qTYQk96rO4iyoKDZBXiO/Vk2sM qnVpF/GRGj+TRhxblKeU6rdF61tbWaisk3WVGVLCMWpE/7c9Xr907adLp 3QmO0PeMlydBLxU92WWcytdFQn/WZU5nclHBJHAr7rFWcLh1MnIyFYTae w==; X-CSE-ConnectionGUID: C1sswkSrQy+pa1d+oVi69g== X-CSE-MsgGUID: 7GR4o5dbRZOp2O0MfqxJVw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441491" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:05 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:00 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:27:55 -0700 From: Varshini Rajendran To: , , , , , , , , , , , CC: Subject: [PATCH v5 12/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT Date: Wed, 3 Jul 2024 15:57:49 +0530 Message-ID: <20240703102749.195907-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT for sam9x7 SoC family. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Changes in v5: - Updated Acked-by tag. --- include/dt-bindings/clock/at91.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/a= t91.h index 3e3972a814c1..6ede88c3992d 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -38,6 +38,10 @@ #define PMC_CPU (PMC_MAIN + 9) #define PMC_MCK1 (PMC_MAIN + 10) =20 +/* SAM9X7 */ +#define PMC_PLLADIV2 (PMC_MAIN + 11) +#define PMC_LVDSPLL (PMC_MAIN + 12) + #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51FD7176AB8; Wed, 3 Jul 2024 10:28:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002495; cv=none; b=ZrpDMNkCssB3GL29nNVHcx/TWW2w0YiKyA+kd/4tdtQAhkxzvucsaHa5xAZXu8qkf6qSeLdQiEjpX9607e9A45xUWztP157vvZmkLCwaLSKk4gba//MZIa5AegrSjEd0suQmfC3/cGgoiq1HtY1c77r7yGkPxpt2Jv5v+yrSPIY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002495; c=relaxed/simple; bh=4duUfAeKHQ1N80KuivEzZ4JcMo7IQQjE6NMjrtNiFVo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bCwFAn3t5nlNzAN2+NK2ru4HuXPha35JsBBNOFUei2pvt0ayhff8H5D9p/MwKhvB5SEDtjymxo9l/xdTezMFNgqy1K6yyMBi5p0GKZYp9th2pQnS5lhyvoECSeOwBq96l1B2ZmKdscrDX0SjzLQaFwLynoRO7rrhbZNA6UEXO94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NqawKuMk; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NqawKuMk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002494; x=1751538494; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=4duUfAeKHQ1N80KuivEzZ4JcMo7IQQjE6NMjrtNiFVo=; b=NqawKuMkIbqa+gD+fzDRt5LAAH1PIZn3c7pwYWtRVludS1mAJsR44ByL D3K1WympMDWwaRNyfiYJK1Dg9PC8O7HEkuMjgOu9JYq3Q9ASQ3DJKLRVX zW9+nwOWiv0pzTy9bjHxwHcD3R5j0e+TnNVrSwu4EUTBN9B+E4yoyTUvN +ipdsqQilfyRukO3f98DfdtTMXhC0MNuC0i1CzGbh3/As0wozgBPjuTvy AMoAC6zDKKiWC20Dsr50aU6tAJNJSdYQ/Cb3noUM95/PqCYqBosTpFib3 702qZkIjkCKol52UGUpNqzeey5S1LndiTht+gPpklI59g0wZlX/c/mLc7 w==; X-CSE-ConnectionGUID: zAkMoDX+T3uCd+MLD1u0xA== X-CSE-MsgGUID: 278iSfmzRcqVTs5Im3KW+Q== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804744" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:12 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:06 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:02 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver Date: Wed, 3 Jul 2024 15:58:00 +0530 Message-ID: <20240703102800.195957-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 947 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9260.o at91sam9rl.= o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) +=3D sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) +=3D sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) +=3D sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..b031280bbb32 --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics =3D { + .output =3D { .min =3D 32000000, .max =3D 266666667 }, + .divisors =3D { 1, 2, 4, 3, 5}, + .have_div3_pres =3D 1, +}; + +static const struct clk_master_layout sam9x7_master_layout =3D { + .mask =3D 0x373, + .pres_shift =3D 4, + .offset =3D 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] =3D { + { .min =3D 732421, .max =3D 800000000 }, +}; + +static const struct clk_range upll_outputs[] =3D { + { .min =3D 300000000, .max =3D 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] =3D { + { .min =3D 366210, .max =3D 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plla_outputs), + .output =3D plla_outputs, + .core_output =3D plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(upll_outputs), + .output =3D upll_outputs, + .core_output =3D upll_core_outputs, + .upll =3D true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(lvdspll_outputs), + .output =3D lvdspll_outputs, + .core_output =3D lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(audiopll_outputs), + .output =3D audiopll_outputs, + .core_output =3D audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plladiv2_outputs), + .output =3D plladiv2_outputs, + .core_output =3D plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, + .div2 =3D 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, + .div2 =3D 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout =3D { + .div_mask =3D GENMASK(19, 12), + .endiv_mask =3D BIT(30), + .div_shift =3D 12, + .endiv_shift =3D 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: clock flags + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][PLL_ID_MAX] =3D { + [PLL_ID_PLLA] =3D { + { + .n =3D "plla_fracck", + .p =3D "mainck", + .l =3D &plla_frac_layout, + .t =3D PLL_TYPE_FRAC, + /* + * This feeds plla_divpmcck which feeds CPU. It should + * not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plla_characteristics, + }, + + { + .n =3D "plla_divpmcck", + .p =3D "plla_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + /* This feeds CPU. It should not be disabled */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid =3D PMC_PLLACK, + .c =3D &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] =3D { + { + .n =3D "upll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .t =3D PLL_TYPE_FRAC, + .f =3D CLK_SET_RATE_GATE, + .c =3D &upll_characteristics, + }, + + { + .n =3D "upll_divpmcck", + .p =3D "upll_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid =3D PMC_UTMI, + .c =3D &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] =3D { + { + .n =3D "audiopll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "audiopll_divpmcck", + .p =3D "audiopll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOPMCPLL, + .t =3D PLL_TYPE_DIV, + }, + + { + .n =3D "audiopll_diviock", + .p =3D "audiopll_fracck", + .l =3D &pll_divio_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .eid =3D PMC_AUDIOIOPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] =3D { + { + .n =3D "lvdspll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &lvdspll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "lvdspll_divpmcck", + .p =3D "lvdspll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &lvdspll_characteristics, + .eid =3D PMC_LVDSPLL, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] =3D { + { + .n =3D "plla_div2pmcck", + .p =3D "plla_fracck", + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { + .pres_mask =3D 0xff, + .pres_shift =3D 8, + .css_mask =3D 0x1f, + .have_slck_mck =3D 0, + .is_pres_direct =3D 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout =3D { + .offset =3D 0x88, + .cmd =3D BIT(31), + .gckcss_mask =3D GENMASK(12, 8), + .pid_mask =3D GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] =3D { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, + { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, + { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, + { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: clock flags + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] =3D { + { .n =3D "pioA_clk", .id =3D 2, }, + { .n =3D "pioB_clk", .id =3D 3, }, + { .n =3D "pioC_clk", .id =3D 4, }, + { .n =3D "flex0_clk", .id =3D 5, }, + { .n =3D "flex1_clk", .id =3D 6, }, + { .n =3D "flex2_clk", .id =3D 7, }, + { .n =3D "flex3_clk", .id =3D 8, }, + { .n =3D "flex6_clk", .id =3D 9, }, + { .n =3D "flex7_clk", .id =3D 10, }, + { .n =3D "flex8_clk", .id =3D 11, }, + { .n =3D "sdmmc0_clk", .id =3D 12, }, + { .n =3D "flex4_clk", .id =3D 13, }, + { .n =3D "flex5_clk", .id =3D 14, }, + { .n =3D "flex9_clk", .id =3D 15, }, + { .n =3D "flex10_clk", .id =3D 16, }, + { .n =3D "tcb0_clk", .id =3D 17, }, + { .n =3D "pwm_clk", .id =3D 18, }, + { .n =3D "adc_clk", .id =3D 19, }, + { .n =3D "dma0_clk", .id =3D 20, }, + { .n =3D "uhphs_clk", .id =3D 22, }, + { .n =3D "udphs_clk", .id =3D 23, }, + { .n =3D "macb0_clk", .id =3D 24, }, + { .n =3D "lcd_clk", .id =3D 25, }, + { .n =3D "sdmmc1_clk", .id =3D 26, }, + { .n =3D "ssc_clk", .id =3D 28, }, + { .n =3D "can0_clk", .id =3D 29, }, + { .n =3D "can1_clk", .id =3D 30, }, + { .n =3D "flex11_clk", .id =3D 32, }, + { .n =3D "flex12_clk", .id =3D 33, }, + { .n =3D "i2s_clk", .id =3D 34, }, + { .n =3D "qspi_clk", .id =3D 35, }, + { .n =3D "gfx2d_clk", .id =3D 36, }, + { .n =3D "pit64b0_clk", .id =3D 37, }, + { .n =3D "trng_clk", .id =3D 38, }, + { .n =3D "aes_clk", .id =3D 39, }, + { .n =3D "tdes_clk", .id =3D 40, }, + { .n =3D "sha_clk", .id =3D 41, }, + { .n =3D "classd_clk", .id =3D 42, }, + { .n =3D "isi_clk", .id =3D 43, }, + { .n =3D "pioD_clk", .id =3D 44, }, + { .n =3D "tcb1_clk", .id =3D 45, }, + { .n =3D "dbgu_clk", .id =3D 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "mpddr_clk", .id =3D 49, .f =3D CLK_IS_CRITICAL }, + { .n =3D "csi2dc_clk", .id =3D 52, }, + { .n =3D "csi4l_clk", .id =3D 53, }, + { .n =3D "dsi4l_clk", .id =3D 54, }, + { .n =3D "lvdsc_clk", .id =3D 56, }, + { .n =3D "pit64b1_clk", .id =3D 58, }, + { .n =3D "puf_clk", .id =3D 59, }, + { .n =3D "gmactsu_clk", .id =3D 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] =3D { + { + .n =3D "flex0_gclk", + .id =3D 5, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex1_gclk", + .id =3D 6, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex2_gclk", + .id =3D 7, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex3_gclk", + .id =3D 8, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex6_gclk", + .id =3D 9, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex7_gclk", + .id =3D 10, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex8_gclk", + .id =3D 11, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc0_gclk", + .id =3D 12, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex4_gclk", + .id =3D 13, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex5_gclk", + .id =3D 14, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex9_gclk", + .id =3D 15, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex10_gclk", + .id =3D 16, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb0_gclk", + .id =3D 17, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "adc_gclk", + .id =3D 19, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "lcd_gclk", + .id =3D 25, + .r =3D { .max =3D 75000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc1_gclk", + .id =3D 26, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan0_gclk", + .id =3D 29, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan1_gclk", + .id =3D 30, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex11_gclk", + .id =3D 32, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex12_gclk", + .id =3D 33, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "i2s_gclk", + .id =3D 34, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "qspi_gclk", + .id =3D 35, + .r =3D { .max =3D 200000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b0_gclk", + .id =3D 37, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "classd_gclk", + .id =3D 42, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb1_gclk", + .id =3D 45, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "dbgu_gclk", + .id =3D 47, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mipiphy_gclk", + .id =3D 55, + .r =3D { .max =3D 27000000 }, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b1_gclk", + .id =3D 58, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "gmac_gclk", + .id =3D 67, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range =3D CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **clk_mux_buffer =3D NULL; + int clk_mux_buffer_size =3D 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i =3D of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name =3D of_clk_get_parent_name(np, i); + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc =3D pmc_data_allocate(PMC_LVDSPLL + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + clk_mux_buffer =3D kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!clk_mux_buffer) + goto err_free; + + hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw =3D hw; + + parent_names[0] =3D "main_rc_osc"; + parent_names[1] =3D "main_osc"; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] =3D hw; + + for (i =3D 0; i < PLL_ID_MAX; i++) { + for (j =3D 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw =3D main_osc_hw; + else + parent_hw =3D __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw =3D sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw =3D sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, NULL, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; + } + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D "mainck"; + parent_names[2] =3D "plla_divpmcck"; + parent_names[3] =3D "upll_divpmcck"; + hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", NULL, &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] =3D hw; + + parent_names[0] =3D "plla_divpmcck"; + parent_names[1] =3D "upll_divpmcck"; + parent_names[2] =3D "main_osc"; + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + parent_names[4] =3D "plla_divpmcck"; + parent_names[5] =3D "upll_divpmcck"; + parent_names[6] =3D "audiopll_divpmcck"; + for (i =3D 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw =3D at91_clk_register_programmable(regmap, name, + parent_names, NULL, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, NULL, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", NULL, + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + PMC_INIT_TABLE(mux_table, 4); + PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, NULL, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] =3D hw; + clk_mux_buffer[clk_mux_buffer_size++] =3D mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + kfree(clk_mux_buffer); + + return; + +err_free: + if (clk_mux_buffer) { + for (i =3D 0; i < clk_mux_buffer_size; i++) + kfree(clk_mux_buffer[i]); + kfree(clk_mux_buffer); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C022C15B984; Wed, 3 Jul 2024 10:28:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002526; cv=none; b=ayKRvT+1HWz1jpgGM2wptDExjPfVLGKk4UVrq0X1e3EGYAt2DrdicYPxjTS+6FavKEqeepaOAWX9WWB5E3c21TO35108S6qWSWmn1XEaszvh/nY3I1uIQXIVuHUm8rYdtac/0H8wXBXGOojzbLzDbRkzNiAtL4+8mM/ocSM0mmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002526; c=relaxed/simple; bh=CmJesmNxIPY2fznL1g2fgRBGnbSimFBYGTSZFAcUZo0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i3adS5tXgX75FetBLwd0/O7gZ7y2Ot4xxM+SZfKBGbVf651XXIrLNcRqS7EcQgR/s8ahSK1a6NDB+EdKEyZc9ZMTv7iDaJDU2/fo1wezcnGXKOY+bb20NFxfpAHYbQnR1fHqCwziOh80uItKeFBq/1Auq5ER/PoFoQmqzL3yWxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ubmXMT7B; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ubmXMT7B" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002525; x=1751538525; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CmJesmNxIPY2fznL1g2fgRBGnbSimFBYGTSZFAcUZo0=; b=ubmXMT7BifY0adHoC884usACQDVGp+dHWzMeRY8OssbCXoEdc2AXNpoS tYUZhlaEWsa8QnQJZDmPzLjJ3YCr+1W86Tx1P4rca7oe5rMWidr8b6Bzk oRfKFd3j8adW87AoGtR2306hrlnOENks/hlljIpS/3BnC6jB7ANa+uuYF U3SVLqInLPeePmDyRWd1tFc7R883a+3Xb9A4yeFoC5rnE9Iji2J6FhmWC RB2tlnE8+qsZfD7UOybbcq+/wsrd5Qr+A+WVWSUlvi84fwgs4fM0zW/RA uXDTexOisT8C+Gp8jh21tb8UT0wkwTXMRVohX0JPES25EX7VyZPtKt9QM A==; X-CSE-ConnectionGUID: ywlN1IFORca1IOesWlMguw== X-CSE-MsgGUID: jnuJLQ9cSDe1Ka2QVXOd1A== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804765" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:44 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:14 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:09 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v5 14/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic Date: Wed, 3 Jul 2024 15:58:06 +0530 Message-ID: <20240703102806.196014-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- Changes in v5: - Adapted the patch to the new yaml file. - Removed the Acked-by tag due to the TXT to schema change. --- .../bindings/interrupt-controller/atmel,aic.yaml | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.= yaml index d4658fe3867c..9c5af9dbcb6e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -17,12 +17,16 @@ description: =20 properties: compatible: - enum: - - atmel,at91rm9200-aic - - atmel,sama5d2-aic - - atmel,sama5d3-aic - - atmel,sama5d4-aic - - microchip,sam9x60-aic + oneOf: + - enum: + - atmel,at91rm9200-aic + - atmel,sama5d2-aic + - atmel,sama5d3-aic + - atmel,sama5d4-aic + - microchip,sam9x60-aic + - items: + - const: microchip,sam9x7-aic + - const: microchip,sam9x60-aic =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5793B16F0DD; Wed, 3 Jul 2024 10:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002527; cv=none; b=J/xqD/4cixTheV+Ex16uP8/joMYVk/qyLZ9v1NoyXsPnF/2YYbsP4UYzZKn0iUu2zAyhcmCFLCP4CzuZr6kDZ0Awa0b6HXRsCfOTMtvUqXV9xe2ZamEG0/IjtSKUbA7z85RE805aLt2//wt+ls6hRjMBncp+kqg8Aui7bq+E55c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002527; c=relaxed/simple; bh=YbocINexu7W/LW3dxzi0XE7KHqeUdFUgZnMRwDmW0kE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p8Mkmp3fwUrwI6U/YKBnvUIZ+ien5GdfwBy0cMWad54HQO5peSADXTBckRdlDDTYBFxxmdoqWnqbi410WJ/hz0ZBE0eEFaO5gzxQMwAEkHF9V8oS79nqICaS72ewZsFAG4vD5FOOyrDocU7P06rZ6dnyoEFPD1523zJOV169XNw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GMuuaTYQ; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GMuuaTYQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002527; x=1751538527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YbocINexu7W/LW3dxzi0XE7KHqeUdFUgZnMRwDmW0kE=; b=GMuuaTYQ/a0IaK4HgSl+QfxtPWJlKLnDZmQjIRcTruPG5kK2OoRCJ4In fjWWPBuA2gioGxgeMBNWbH3I82xHg0iYPiuOQn8eUiniVyj8mCD10N87w 05yLJNkii7Qtmek4qXMWasuUC75SXw/IldHvpBjNapL8CH2KWMdC2RARD 14+pF8ZgfHiuilLGPBB/Ty9Cyl0hrdQQ/Bf2jo33Ji/oDiUo7zJWEzCVe EZvN8/tJBqGPpZGitXDWwWh4rmcyztLElXDqoImpDscHWCL0RXMjvk8A4 yYfXY/B/T4S9T/5tqv9I9gmXvpN1/yWQ+4F/+EEeNNCjY1ZhjjMeaB4S+ w==; X-CSE-ConnectionGUID: ywlN1IFORca1IOesWlMguw== X-CSE-MsgGUID: V6OkUdLkTRSruK8jHMM+cw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804766" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:21 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:17 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs Date: Wed, 3 Jul 2024 15:58:14 +0530 Message-ID: <20240703102814.196063-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the description and conditions to the device tree documentation for the property microchip,nr-irqs. Signed-off-by: Varshini Rajendran --- .../bindings/interrupt-controller/atmel,aic.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.= yaml index 9c5af9dbcb6e..06e5f92e7d53 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -54,6 +54,10 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array description: u32 array of external irqs. =20 + microchip,nr-irqs: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: u32 array of nr_irqs. + allOf: - $ref: /schemas/interrupt-controller.yaml# - if: @@ -71,6 +75,14 @@ allOf: atmel,external-irqs: minItems: 1 maxItems: 1 + - if: + properties: + compatible: + contains: + const: microchip,sam9x7-aic + then: + required: + - microchip,nr-irqs =20 required: - compatible --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D020516F0E6 for ; Wed, 3 Jul 2024 10:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002528; cv=none; b=RaQyDKqNEFSn6rFnDo92CKUamBfh3RQ2suSoeN63J+qhtUx/GDCEkVmFNf5iLpwVfaf/xW8du/pqfOER+WMBJFSX+Qmqcf1AQz2CIoyOpVAZfxituLH85O10lL96kP2h4pPKuOCVRjrXEEc9FvpxLztUELjil/xZy3ZAi5Nfunw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002528; c=relaxed/simple; bh=XD4Q7cZLicWEz0JXcKOPLuwfCe9wBLZj9EmkWqD4OZA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RqJzb59ldRLL4tw7x2/q5oOFZDYXJhiuONtJJYd1zyDdH5awpebhxEBA+KKaTNWcGueYyQ9vw4N8kuPxHmu3V31aYW3FMDjHUJjhJ/AtzLFM07f0kpEwP6ocvnEmB9ngBHxECwUIPlCs/qQuNCiAaq3yq0QN6L7DtuVvF0Xv6UM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=u0dJ5i4p; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="u0dJ5i4p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002527; x=1751538527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XD4Q7cZLicWEz0JXcKOPLuwfCe9wBLZj9EmkWqD4OZA=; b=u0dJ5i4p8XG+fWIOUjdio20VhQEDvSge1zInwGxZmuoBTbGV2qggMnTY rVGTtlIU6O+Isc2LcjJ7jprxLE3wR/HGjNHNKBCMMfc11rluJ3vdVCJqY DBm4gkcrGKnlXMbAxpZ3/IQJpfS1k7AXwcJco9TNBLi9oW3J7WriSsmMA NzzdB1KRFuJOrHA/qGoFkiPV/1yXEZmOKATYrn57tO6dEroiExPf0Wzym qDrmT+iGdONsZc+1SvhzPbCNObLWkVPdmGK7qvUhdnpAyAYUY5dYjWuVO SQoSYdSqKA+KpA/Qp+Exqf9HwxhIBm6uLLybmBxzEAyxHrvjK0qdKDZbF Q==; X-CSE-ConnectionGUID: ywlN1IFORca1IOesWlMguw== X-CSE-MsgGUID: PL6zp7yMQlaYofmNGkNlPA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804768" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:28 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:25 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v5 16/27] irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 & sam9x7 Date: Wed, 3 Jul 2024 15:58:21 +0530 Message-ID: <20240703102821.196112-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to get number of IRQs from the respective DT node for sam9x60 and sam9x7 devices. Since only this factor differs between the two SoCs, this patch adds support for the same. The macro is still used as a fallback for the sake of old sam9x60 DTs to work so that there is no ABI breakage. The property is a enforced as a requirement for sam9x7 alone. Signed-off-by: Varshini Rajendran --- Changes in v5: - Changed the ABI breaking code. - Added sam9x60 NR_IRQ as fallback for older DTS to work. --- drivers/irqchip/irq-atmel-aic5.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-a= ic5.c index 145535bd7560..164b5a9b0f9b 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -403,6 +403,12 @@ IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sam= a5d4_aic5_of_init); static int __init sam9x60_aic5_of_init(struct device_node *node, struct device_node *parent) { - return aic5_of_init(node, parent, NR_SAM9X60_IRQS); + int ret, nr_irqs; + + ret =3D of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs); + if (ret) + return aic5_of_init(node, parent, NR_SAM9X60_IRQS); + + return aic5_of_init(node, parent, nr_irqs); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_ini= t); --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C854D172BCE; Wed, 3 Jul 2024 10:28:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002529; cv=none; b=Yg0KgV96shtLxXXYegdDgaXmMu7vnePJz0yK/jmH0J3J7mvtMgYGD7DW9DxlT/+9KtANZdqdbFFB4Oy/biayg2zM4QhyojmYjtx2Yl1M5I2/SvyMzBBQ2sReY0u3rSWj7hmfMNwApJzS7O5iFVgrE7tBxYWKKlH49BGMD/YaJ+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002529; c=relaxed/simple; bh=iW4nEYVeIC+sXQd4/K8zgIRVxXurmIFqKqfAT9zN62o=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V0RVvLaZ7vgP04PhZJg0GxDA/NuO9ydKMl7U3LCfaxVZF3Px6jjqJf0HS9l5/AcibNsPpQ1UNi0wOkJ5kK0xk3CN98HnXJAky4fz+sYW1e+RqrCKvNxPR0OKl8O5UMP0M5wnKJ1gBD2eQHF/qx/+1+RYu3+Ru5Teyru1QkrQMAE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=LlNmUIWB; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="LlNmUIWB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002528; x=1751538528; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=iW4nEYVeIC+sXQd4/K8zgIRVxXurmIFqKqfAT9zN62o=; b=LlNmUIWB+TLtecwUUGb1SQXnZ3/fTKiz+ROWTZ6NUdpUqZOwSxj4Fz9D Z74FbL2f7bWfft+YLs6K0rv+DWKxODzrKomYxD7JhtAzb54haECXl+UqC dOMkbUl5lrxEFjtAPHwGW6EJnXICToV0v8212+VVQIJbR1ad6G+r0dk+p 7OG3Ke+w+DqZs8P6RMJVc5JXB3atGytS28FfwkJvxn68WwQb5vZp9VtQU sDRzPK0FLH0yDTbRM7HKAGPdEj2H+C+LbHLddC696xGDzE+3IerTW9ST6 K6DrYvD/L+//TVMQRnl+TpVkGkRAfKx/u+4AnkYkfGNc2aVHBm/UrVoVE Q==; X-CSE-ConnectionGUID: ywlN1IFORca1IOesWlMguw== X-CSE-MsgGUID: 7KTdyXrOTBuQuZ1ZGgEHHA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804769" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:34 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:31 -0700 From: Varshini Rajendran To: , , , , , , , , Subject: [PATCH v5 17/27] ARM: dts: at91: sam9x60: Add nirqs property in the dt node Date: Wed, 3 Jul 2024 15:58:28 +0530 Message-ID: <20240703102828.196160-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the microchip,nr-irqs property in the DT node and set the value for the driver to get the value from the DT instead of a hardcoded macro. Signed-off-by: Varshini Rajendran --- Changes in v5: - Separated the patch from the DT bindings. --- arch/arm/boot/dts/microchip/sam9x60.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/m= icrochip/sam9x60.dtsi index 291540e5d81e..7dbe34b7587a 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -1201,6 +1201,7 @@ aic: interrupt-controller@fffff100 { interrupt-controller; reg =3D <0xfffff100 0x100>; atmel,external-irqs =3D <31>; + microchip,nr-irqs =3D <50>; }; =20 dbgu: serial@fffff200 { --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E72561741F0; Wed, 3 Jul 2024 10:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002577; cv=none; b=Fsi55pmko+nR/CuMinPg8U3hshn2fLLwt3afX1PUa1Iup4AQ3Zk9EtF2f7Tww2Vj5hgRNOup9gBAZtcgdIQWar1qeLFX8WjNJVsG5xqLntmSf6HFew9Eq1QyQsQZ9lt5RcQwZKpsnW07+Andm41IgrK2LwEBaHO2lpAq7Bzrdn8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002577; c=relaxed/simple; bh=2rxZwmpesmt4gYw7ZgNbsdv6cjopR4CadPApkuByy7M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oP1KpNPCArmZVfDvPM6cR9PFGdEwhbbusdPCVh1DAXhazntoN580HUvnaZObtuExrq0lhqUIG3pj+ElXkidxhuIlk8BCzPWdHmN1Q5FyqHqL054QiQG7Ibv+KKy62pxZAtBlFI6ytyD2nBINaXIYoDUGYrtTIP3bEIsYFJdw0s0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=rRHx6x6L; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="rRHx6x6L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002576; x=1751538576; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2rxZwmpesmt4gYw7ZgNbsdv6cjopR4CadPApkuByy7M=; b=rRHx6x6Lp4PHaqckxBUUZOW98cKUltBvGi3fF2X8DyyZxvd8eEprvpyT MSCDTPvwFjjw8bsJWVP9axtv/RvCRAKxXT3wV0hIl/GE+w/Ob+w4+7bpt WMpLahmNmbP6Xbd587lv+O4OtGCCHX8fQ+t0FEPKf1jth/R3mZvjba3Ea 2FzAbRwihX0z2wUktJFAeFs2M0qGKODI6uifrds9I2YoYjYnK83js2iQD 1WIOee6DdFvV+zIhVDTPaX/mk83P2+wBExR6rgF6RIKFwLnZTBy3DTVXn VxiOTQCBVOBin3XGx0oE69H2uKiACU2R4n8b1fDLYfnKEIyjBWamvrWXK g==; X-CSE-ConnectionGUID: JwvaHmRMTXaAt14ps6TIkA== X-CSE-MsgGUID: /JArwzt0QaSX4MdAWneEAA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441553" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:43 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:38 -0700 From: Varshini Rajendran To: , , , , , , CC: , Sebastian Reichel Subject: [PATCH v5 18/27] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Wed, 3 Jul 2024 15:58:34 +0530 Message-ID: <20240703102834.196209-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use sam9x7 pmc's compatible to lookup for in the SHDWC driver. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index 959ce0dbe91d..2121d7e74e12 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F293B16B3A1; Wed, 3 Jul 2024 10:29:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002552; cv=none; b=Ksd68LUGShiV/gVe7CkKI1PbmeX4F/c6khMYhxA4jfKHCIKqG/a3Vk6twj9gcnTTXGc77apLl5CMJwHR907a0C5Sgx+Ow0g9SZ0AP3HL5V0PMBtY3vJ+qOk4Et2IZPErsxP7ME8Idb0jkXXTD1VHf30qfUgSIfQGftSpxaBlUaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002552; c=relaxed/simple; bh=OQ3DquxxckfkYxfIhdDEQe/+9PiGWGIXHlCGBn7IixI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oBJ9HyjbDlWFWwUOtzqQ9JiOwEmwV90EIP14k/5z01SP8iLc+y4awqF2MFd3rRCl+lBsz/zLV6Ik+MJ//tRz3rFgrgkQblwKSBs06I5vZyHHUbTs6ZkzRQxTgdQaLoC4f6wzLEND30kj9fTKju4Gt2Jq9ZklRc8CrNT9XOc7WPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=J6bOeN93; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="J6bOeN93" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002550; x=1751538550; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OQ3DquxxckfkYxfIhdDEQe/+9PiGWGIXHlCGBn7IixI=; b=J6bOeN93MgSTuX67wLO+e+PqSFMobynPxVfxGHTyv316Cmv6a+EWnlnf bMfalvzc0izmm9jPxzG7dlaYwQg3v3QCCcupI+55mIt5N/+0y9hZ76KXI 5gEIHDPfpmkxtcvN89/DEEi8hR/fQwB+v4H26U8pc9/88a+OdomvYOIeE hLeakidnNXTXVK11MrjhQ4eZAe+1UXFoETMJwMuaX7+Uwf0QOaCkYRdA6 S7yqbO6bx72Wl1D4/bhnjAcdgV7bAVeEA5/2LJidZFNXb/xuEfI1LLtq5 n42zWmQptvhrYmg+ef9DGpCu7fUHD68oWf4v04tI1MyMPhxDvnu+D4qTc g==; X-CSE-ConnectionGUID: n3BwhiapRjCNKuOiIdXemA== X-CSE-MsgGUID: NmNsCLHURH2IguhwouDY+w== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414906" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:49 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:46 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel Subject: [PATCH v5 19/27] power: reset: at91-reset: add reset support for sam9x7 SoC Date: Wed, 3 Jul 2024 15:58:43 +0530 Message-ID: <20240703102843.196257-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power reset support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index fece990af4a7..e3ebebc1f80d 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 474E21741D0; Wed, 3 Jul 2024 10:29:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002563; cv=none; b=oSiQnKpaR/8+wfCYarGUTSc4I5BGqsjj3wxl+vB/YXg1G1czyZ1PCMTEhMrEt+L9tljjD/tmql7Wu/D0miwG+2yFRWYU3T3VMz4eqtTGm+tWv8vQWlAMlYo8fFiTzdp+exOOcgrg+1ByHcdABTGPtZoTLZrX6RH9HXwtucJb+PE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002563; c=relaxed/simple; bh=f48C0WPPIxyQ/j5gPukOm6INa/bMMCH6vCkVjKj3zZA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mN1ap4gQ4xuFk7IwpGtlb6N3Lw4ehLGLMIOWkFYphUI1bTJSx+QWZ5rzcM9PHGe9jq6kMETtFTm/KA4zmInhSmriBwvY/SiQFD3jR9ymfwzPz/4tZwIx4CZoqEqmreUiU4jajK1xlsfXamO7r8ukzXnbefz4AyUhedIRZf+VeU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=tnKzEs+e; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tnKzEs+e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002561; x=1751538561; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f48C0WPPIxyQ/j5gPukOm6INa/bMMCH6vCkVjKj3zZA=; b=tnKzEs+essMT/1CTF/eXuiT5LovX2b+ZlgOWbVQHp0q9J2luxW7JPR/+ I6rtkNh20rbJWbdqaxLnkCzj9pF7Xp2eCBeP1z7ksHvfXAxbnys5d/RWt p879ZxX4jxtgYBlrI5KE6YsIdYiTM5l4xVq1lvsBTYlTx0SOetGfsK0gs YkmWi3hgtaZb+M2YNoiT9JFWVLjIq+2isxMhb6RItTzH4JK0bsczd44KK cnuyewH5Ki3aUWNvi0Wa89UpfFxLifUYHk8P4Gk+sQ2X0WZVbwGIPd7xp pvcB6Xy0OfZa+pZFI++muuTo36EBW0d+1XB8ipbxnCEAHCU/aIVuQZZno g==; X-CSE-ConnectionGUID: fwe4YiXZSfmRHS8m80mboA== X-CSE-MsgGUID: ubwmUnY4S2OAISBYSf6Dnw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414918" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:54 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:52 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel Subject: [PATCH v5 20/27] power: reset: at91-reset: add sdhwc support for sam9x7 SoC Date: Wed, 3 Jul 2024 15:58:49 +0530 Message-ID: <20240703102849.196305-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index e3ebebc1f80d..dafb0126f683 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E151176FA0; Wed, 3 Jul 2024 10:30:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002614; cv=none; b=BSXXbrUvlfi4mMgQBYvXUiLeqVMAjrLkz6wRl90iCe9clVXIpOL/hRUehwiuN+cuwCYx0w5xf0yp+cRKahgBU+NxfZeRvy0SfCtVf1rBozJQSRrNBJ21dyyGSEvhQ6MMIE9Q/QgwBwti97bXQuORqlKT04bMkY9/FR9NbnU6oew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002614; c=relaxed/simple; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D1qJ9gJwQDqhyzWBP+ezFaax9+FeSVUrcf4ZFCBKOmesnjErgxg0jO3evbEgY78VKbv3Bh5rR6UfU6pHioU/dFnlJjbeR6F2Bjm1+nyAjxElGuwREfxDDzXj0qjpdSd3/Z/2SCeG6yoUx3PWgUhErs59RTuBEkWP2gBRv5nNi1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Wldcbtw6; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Wldcbtw6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002613; x=1751538613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; b=Wldcbtw6Iec00tl8VArPbQgqOkfbLgXcCFJlnxKxTO3EFEriO42rZols voecWQASntRhv0udOIMhXqw/JBDwH7KuXxE34G6h3LNMeqGt0EVXBZMwL LnDjdOBzCLqAv2gWZAcU5sBFAi/Gmkg3HX7EgD9YXcGuON28UXWnJCNwQ TfwSu0dLAZx5rRZDDSFQ6Wm0Rkd/p+krbn/KU7IcJ3HjFiuUkDyMYSrlH QJTJQINdVfeb3iOeZbps1eoUxLmC1udJcDDBrawEh8QtR2kOVMO0yVRtQ 06H06smCbRayqbKLoNaVJyliL2HwTG3uRUKzqXBNkU28EG5XRveKdXiQJ w==; X-CSE-ConnectionGUID: hLLhwY7cQcOyno5TMnxZqQ== X-CSE-MsgGUID: vS98msG8QLSgNJkd/SwUsQ== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441574" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:30:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:02 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:57 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v5 21/27] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Date: Wed, 3 Jul 2024 15:58:54 +0530 Message-ID: <20240703102854.196354-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-rese= t.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.ya= ml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc =20 reg: minItems: 1 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E7831741CF; Wed, 3 Jul 2024 10:29:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002562; cv=none; b=plng3GkSr3yBU9G0kBHQd56Z3YQb4MJEO1jODnc9lTfiHw8fIW+DZUBoRdRmgYu4dQ7OKiu9V6OE3wCVaz+CteiuFpTefpLPyoRLoTP34kFQkdczDzTsiRYN2vy8fliYFNMsBLiseuV8KuNO53rnl2T0TlGZcwdwMUb5mWcxAKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002562; c=relaxed/simple; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GLzJ4RfoVfw/DzkMkLjTO+YRK0vULr8UKAU1crXo1wwNxblpHYfRQkQWHvibFBsgtHB1NslFhj1MDAJO3ZKJKmfG+p2wQIfhRn1vLXaeisLgdxCcUNBZmcO45xX8Ggy3hLWpe4Zb3azi0RcGdMHsxmgIXFD2U7ncf3i0WtQtkKA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hxvC0SL5; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hxvC0SL5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002562; x=1751538562; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; b=hxvC0SL5ERbvpzes7OtZdVWSR+R488fSPeb/fjD/nIQM7UTxwQ1QNsdr ZXUDSfQHfH5I2K0N9k1kb2PUgxH1IbwD5X1d4xZvauqhebd50cVihpM7A lofzAzn5FMFpds6+RJaxUjQbHyHraohuapRxgZdCmvlQtrhMib10h01D0 7GozbrjVRRl8921Lsb14WzaPsi2C0ysmC3FWyI8Lr6/vOecIv69dLRZnK LTVdFNaTcSks6ReW1u0MlmDLyE06wBINPB/9JC9TsH0brhtJ93z5h1Gc7 hAXJiER1I3ppQ6aa0NEHE9K3fwIS5cAMAgwXjCPmEG1trvHrd5TJgPd1y A==; X-CSE-ConnectionGUID: oB4ZDQLAQnSdyIMLfIgWpQ== X-CSE-MsgGUID: GC0AUHZYTDqJd9oYsIyo5Q== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="259682246" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:21 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:09 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:04 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski , Sebastian Reichel Subject: [PATCH v5 22/27] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7 Date: Wed, 3 Jul 2024 15:59:02 +0530 Message-ID: <20240703102902.196403-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller DT bindings. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B80C173359 for ; Wed, 3 Jul 2024 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002564; cv=none; b=rvWhWBmR1i5ibqi4Od4KYwg97oHmrhsdjGDmItoDSMIr07gMdfusil0w7hvv07fozxNEIklnP9dqms4Fou+YkX/Shp1q96SQLYXGeoqF89RoUXxUMCSdPWkywYBpt5GalrpuIGQadmTnq3UNCjxSDlPoVlfFsI05/sHfzKKLQv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002564; c=relaxed/simple; bh=3rEXWlY0rh1GCbsY2rROmJ2mJJST1jTZne/ZMrfSbeU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wc//g+V7IpDBH1bIm7lAX8W1DdfuLuF8qJbVW8y0mSB4d5api415pNNi9ZNQ8gaHut9J55oaZ9yCSlZykItWBTnbcLoSNo2nNeohvCmis24zcgnX3KcwIOeCqZKNYsjDGhJ5+KdrvhMJ2e0y7RC+4/VhWv7LDLKDsro+gywwiEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=A4jUYjYL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="A4jUYjYL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002563; x=1751538563; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3rEXWlY0rh1GCbsY2rROmJ2mJJST1jTZne/ZMrfSbeU=; b=A4jUYjYLwf/kvIvjtohMLVX3GyybVj5MsztojQKSY6xuJJRTCaDv05Xc O0QZ/pQCLQ2VSruQVw1T/S5FJww6dFDNfOnGrWNbRIC6CRwbrwcXg0QWr rRBXzSl5oA1AGXLsc9VQuFuB2tg4UdfaHXyJn4foUdhnfjutAH425ZBj+ Xj8EkH7oAkV3wPegARniDf9Imi/X6r0TNHBmT3ysT7NAwrXMax5j+iys9 yFCS9sazz7L3b+QutBJNv8Ofy/0gZsq2fVS2rueQFjJO+8D2FbI+0l6Sz C5cdThuqIaOxiHInMSr0k/ZKcGjDwhvJRnPei9I3fph7Y0/HFdGd1RFnf w==; X-CSE-ConnectionGUID: fwe4YiXZSfmRHS8m80mboA== X-CSE-MsgGUID: szejZaXRRciAKp6ys2/ufA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="31414919" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:15 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:12 -0700 From: Varshini Rajendran To: , , , , , CC: Subject: [PATCH v5 23/27] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Wed, 3 Jul 2024 15:59:09 +0530 Message-ID: <20240703102909.196459-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add config flag for sam9x7 SoC. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v5: - Removed the unused SDRAMC flag --- arch/arm/mach-at91/Kconfig | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index a8c022b4c053..344f5305f69a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,11 +141,27 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC =20 +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" =20 config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -155,7 +171,7 @@ config ATMEL_CLOCKSOURCE_PIT =20 config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SO= C_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a @@ -166,7 +182,7 @@ config ATMEL_CLOCKSOURCE_TCB =20 config MICROCHIP_CLOCKSOURCE_PIT64B bool "64-bit Periodic Interval Timer (PIT64B) support" - default SOC_SAM9X60 || SOC_SAMA7 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7 select MICROCHIP_PIT64B help Select this to get a high resolution clockevent (SAM9X60) or --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618A81741F5 for ; Wed, 3 Jul 2024 10:29:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002578; cv=none; b=sV+OGBkIOx2jTtnS/MjaZeVWpnLSfxTAwxbx9nh0h7v1iK8ihYZPoHlpnptf4AGcL8v9BRux0jEq0nvcNRPvTVt/9ds+NqEqy/9CzuWiM3OpdOixixV8w794/jCVO0xv3JlvdHzroZAs3BBTx2dTVKA/QNqxLcXt9TQkRhQPcAc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002578; c=relaxed/simple; bh=MzE6ItZ/794POonRjSZ60qB1SlzVtmy0+kfDCLFkHkw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mAjZXfL3UBiZc5eBPrFB+tPTTiHRtkioaFHZqTo0wz7iZVrtIxOPgRLJeZVSb35TQZlm5vJnGxOk3KjbbwnucyeoA8kXX3Co7/mx2OrCO61obwhCy9KXvNxjRa/N8CgsLCo3o9r//kTyAa83EKhnYz0yOdvZYlTsrmvPbP+O59Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0DzlE+mN; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0DzlE+mN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002577; x=1751538577; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=MzE6ItZ/794POonRjSZ60qB1SlzVtmy0+kfDCLFkHkw=; b=0DzlE+mNdluJ9Lm6QPlVwwvYIOtJSrf1N51+r8ZxRks/eyfHORy+ByHV tO5Pbr9sRqV4oVLCxCIkz9IigxBoyl9c9AqdMXTw4l5FzQVvAbU/mTODi lU2Jzd5bec5o717vbvLA+16yxzuBPPDWaiPhadt5fBTV0vyb2EYV4bpOg 40kgIciS2+s+822hE5AsUOo9/MH5nTm8iDmhd2DaDX76mNMMWja7mRY1k YUG4O1OUhKVtTekUduESqqlY1klKEc7LIEorLMm3CEyN8II7ZRSSrdR/H u71Gq/elR8mNbvK71ap93C3m/sWYUXp1J0uyXQGpPa0NkSrp6/brq36p0 w==; X-CSE-ConnectionGUID: JwvaHmRMTXaAt14ps6TIkA== X-CSE-MsgGUID: u43G7fYtRZCP/ke7nXEcxA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441555" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:29:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:23 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:18 -0700 From: Varshini Rajendran To: , , , , , , , , , , , Subject: [PATCH v5 24/27] ARM: configs: at91: enable config flags for sam9x7 SoC family Date: Wed, 3 Jul 2024 15:59:15 +0530 Message-ID: <20240703102915.196508-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable config flags for SAM9X7 SoC for the sam9x7 SoC family. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 1d53aec4c836..880f0c0f4cc3 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=3Dy CONFIG_SOC_AT91RM9200=3Dy CONFIG_SOC_AT91SAM9=3Dy CONFIG_SOC_SAM9X60=3Dy +CONFIG_SOC_SAM9X7=3Dy # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=3Dy CONFIG_UACCESS_WITH_MEMCPY=3Dy --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6224D16C448; Wed, 3 Jul 2024 10:30:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002603; cv=none; b=SdkD2M++goacgdYFpyLODDIv97Q0MBsHun1ko9XRuQ6GKJvWxZNlEAwLjQCuNKGln9A+IMbNrt+0HfRJVmBCtUTqXrwNWjifxcMIMFPEY8qzRHVydl6EcuCYkRwBrStoRdxW+0R2lduyejszDxc1WNPBX4tYSTvR3SYwsIBIlms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002603; c=relaxed/simple; bh=J8NFlqjyfqw1lwDqN0hOuLSyO+X5zXTDIy03xkaetco=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CSrDc9/XAgrqwtvn/50hh61h4oc2D54s2ewuGrK72gJr/iqWdhihJuoiTdFWqfpKMj/DMh/F1rldKnd3yzJQE/BHH7U31VcDR36eUaQl9WfzGMLyTEagg2dli5wTOLFUq1qjJ52/L1NlJTBp8aIpUxofYNc2a2YzZpMWr2jwKU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ZVgN1zEM; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ZVgN1zEM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002601; x=1751538601; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=J8NFlqjyfqw1lwDqN0hOuLSyO+X5zXTDIy03xkaetco=; b=ZVgN1zEMQcmP7AF5gA6lltA7jK1pLmxxLZSKGbxJaAtpMlGoW6/LJ2j2 TyhjueHGuzJsyisJKDjdYGtzkWPRtSXC3m0GjvQ/3XyePSqoy6u5W/aGy KxRhA27w2wmey34u256rX39wmXUk+4FDktrSAJ0hb/tCiXn7udnbQsCBz 7j0UwzxJDhKXMvemUmIJ2dnAi3MeTBqkpIWtR0pz4RBGeWqAgLjKZxAdD lo/cQBLboi9b/Teb0BOgMkPARPFvVmWldVb4Lxoz/Af3pWWj9f+M7FkTF EvIDiN28yhTNpDhENF+64cE/K0GPFfnuWlf/LRpJZ4xjEfnkYoR7RIMdq Q==; X-CSE-ConnectionGUID: WSWDYVd0Sief6o+XdEUAmQ== X-CSE-MsgGUID: xu/z4ZSATruu6Bok5Xu2Rw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="259682272" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:30:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:35 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:32 -0700 From: Varshini Rajendran To: , , , , , , Subject: [PATCH v5 25/27] ARM: dts: at91: sam9x7: add device tree for SoC Date: Wed, 3 Jul 2024 15:59:23 +0530 Message-ID: <20240703102923.196556-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran --- Changed in v5: - Sorted node properties according dts coding style. - Removed space before pwn status. - Fixed DT schema warnings related to usart. - Aligned <> braces. - Changed spaces to tabs. - Changed node names to generic names. - Corrected the typo in gpbr compatible. --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1226 +++++++++++++++++++++++ 1 file changed, 1226 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/mi= crochip/sam9x7.dtsi new file mode 100644 index 000000000000..0e3fb94f40b6 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Microchip SAM9X7 SoC"; + compatible =3D "microchip,sam9x7"; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&aic>; + + aliases { + serial0 =3D &dbgu; + gpio0 =3D &pioA; + gpio1 =3D &pioB; + gpio2 =3D &pioC; + gpio3 =3D &pioD; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,arm926ej-s"; + reg =3D <0>; + device_type =3D "cpu"; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + main_xtal: clock-mainxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + sram: sram@300000 { + compatible =3D "mmio-sram"; + reg =3D <0x300000 0x10000>; + ranges =3D <0 0x300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + ahb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + sdmmc0: mmc@80000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x80000000 0x300>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x90000000 0x300>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + }; + + apb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + flx4: flexcom@f0000000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0000000 0x200>; + ranges =3D <0x0 0xf0000000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + status =3D "disabled"; + + uart4: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi4: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0004000 0x200>; + ranges =3D <0x0 0xf0004000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible =3D "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg =3D <0xf0008000 0x1000>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names =3D "dma_clk"; + status =3D "disabled"; + }; + + ssc: ssc@f0010000 { + compatible =3D "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg =3D <0xf0010000 0x4000>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH 5>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names =3D "pclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + i2s: i2s@f001c000 { + compatible =3D "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg =3D <0xf001c000 0x100>; + interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0020000 0x200>; + ranges =3D <0x0 0xf0020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0024000 0x200>; + ranges =3D <0x0 0xf0024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible =3D "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xf002c000 0x100>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "sha_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names =3D "tx"; + }; + + trng: rng@f0030000 { + compatible =3D "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg =3D <0xf0030000 0x100>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + status =3D "disabled"; + }; + + aes: crypto@f0034000 { + compatible =3D "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xf0034000 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "aes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names =3D "tx", "rx"; + }; + + tdes: crypto@f0038000 { + compatible =3D "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg =3D <0xf0038000 0x100>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "tdes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names =3D "tx", "rx"; + }; + + classd: sound@f003c000 { + compatible =3D "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg =3D <0xf003c000 0x100>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names =3D "tx"; + status =3D "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0040000 0x100>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names =3D "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH 0>, + <68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 2= 9>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x3400 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + can1: can@f8004000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <30 IRQ_TYPE_LEVEL_HIGH 0>, + <69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 3= 0>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x7800 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + tcb: timer@f8008000 { + compatible =3D "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd"= , "syscon"; + reg =3D <0xf8008000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk= 32k 0>; + clock-names =3D "t0_clk", "gclk", "slow_clk"; + status =3D "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8010000 0x200>; + ranges =3D <0x0 0xf8010000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + status =3D "disabled"; + + uart6: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8014000 0x200>; + ranges =3D <0x0 0xf8014000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8018000 0x200>; + ranges =3D <0x0 0xf8018000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf801c000 0x200>; + ranges =3D <0x0 0xf801c000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + status =3D "disabled"; + + uart0: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8020000 0x200>; + ranges =3D <0x0 0xf8020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8024000 0x200>; + ranges =3D <0x0 0xf8024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8028000 0x200>; + ranges =3D <0x0 0xf8028000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible =3D "microchip,sam9x7-gem", "microchip,sama7g5-gem"; + reg =3D <0xf802c000 0x1000>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ + <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ + <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ + <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>= , <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names =3D "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 67>; + status =3D "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible =3D "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; + reg =3D <0xf8034000 0x300>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8040000 0x200>; + ranges =3D <0x0 0xf8040000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8044000 0x200>; + ranges =3D <0x0 0xf8044000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + atmel,usart-mode =3D ; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + sfr: sfr@f8050000 { + compatible =3D "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon= "; + reg =3D <0xf8050000 0x100>; + }; + + matrix: matrix@ffffde00 { + compatible =3D "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "s= yscon"; + reg =3D <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible =3D "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg =3D <0xffffe000 0x300>, <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible =3D "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg =3D <0xffffe800 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names =3D "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible =3D "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon= "; + reg =3D <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible =3D "microchip,sam9x7-aic", "microchip,sam9x60-aic"; + reg =3D <0xfffff100 0x100>; + #interrupt-cells =3D <3>; + interrupt-controller; + atmel,external-irqs =3D <31>; + microchip,nr-irqs =3D <70>; + }; + + dbgu: serial@fffff200 { + compatible =3D "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "micr= ochip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0xfffff200 0x200>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names =3D "tx", "rx"; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + compatible =3D "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl",= "simple-mfd"; + ranges =3D <0xfffff400 0xfffff400 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask =3D < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff400 0x200>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff600 0x200>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <26>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff800 0x200>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffffa00 0x200>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <22>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible =3D "microchip,sam9x7-pmc", "syscon"; + reg =3D <0xfffffc00 0x200>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells =3D <2>; + clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names =3D "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible =3D "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg =3D <0xfffffe00 0x10>; + clocks =3D <&clk32k 0>; + }; + + poweroff: poweroff@fffffe10 { + compatible =3D "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg =3D <0xfffffe10 0x10>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk32k 0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible =3D "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg =3D <0xfffffe20 0x20>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + clk32k: clock-controller@fffffe50 { + compatible =3D "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg =3D <0xfffffe50 0x4>; + clocks =3D <&slow_xtal>; + #clock-cells =3D <1>; + }; + + gpbr: syscon@fffffe60 { + compatible =3D "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "sysc= on"; + reg =3D <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible =3D "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg =3D <0xfffffea8 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible =3D "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg =3D <0xffffff80 0x24>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAEDB176AAF; Wed, 3 Jul 2024 10:30:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002605; cv=none; b=hsTg5n5TjRs4xrmqwjzFJfjk2V3dasG5yedfEP4YKIqNp9Sw3mDVM/bDhl25afPBzABt2R0N/UkwE06jxAGFbMrd6QCLoO4vOrz5J6V6noSH5z3BJomaVpwVIPIDkhTTQgu/wbgestaJy4WIHPc0fKn5GneMP7US8Ze6ZhPawgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002605; c=relaxed/simple; bh=xbdNDU83RLdASHMfHIv+diZ3brJ2+ZBeOGZRr9HKbWI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=exCVJ/FtNXxCIZGjGzyi11wnVnupRxmQ09RmDVkwh12GUZ4FYMFmoxJ65Vw+QBocxlMjQi/sWAyz8Mq2O+q3pfl2mQkji3DHOWXco6NaKrh16PcHOhD3PcXRjpcd+qN+yPoJzFG2fVQ9YkOQZ+nKeesjkljpICcMTQsWCz7zgNw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Yg6d5L+6; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Yg6d5L+6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002604; x=1751538604; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=xbdNDU83RLdASHMfHIv+diZ3brJ2+ZBeOGZRr9HKbWI=; b=Yg6d5L+6qHXJ1hdSpCpGVq70+8A6kQoUV3W3rHw8NeKRwF06tHaDm/yB 58eSOMwoTerl8TBnoTkWGd0sZyMSzT8OSy+OI/SCGr+hFuNqhYt4Hv4gb GjaaIOfKG+IrlpTC1WNyyyhhamf+LS3vhS7ZaYeox8gny4AbMyNQ9jsr0 LVuoAbnyee35o2MRqdToRZUZ5RsprHVpKB7eEPGITvSbYyjLItMk/6+8/ msD/ccrtqt6Y9+aYnv0wK1/b6UuiUEHnISRdPcGt362iGjoQ46mt41t8G HS0pl5ERSHsLT+qwy6rCzq1DTrnHaxy2D/9ON41pS4tpzlqRze2dNZ3GT g==; X-CSE-ConnectionGUID: WSWDYVd0Sief6o+XdEUAmQ== X-CSE-MsgGUID: pxtzhN7kRv2+NnrgAfezkw== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="259682274" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:30:01 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:43 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:38 -0700 From: Varshini Rajendran To: , , , , , , , , , , , Subject: [PATCH v5 26/27] dt-bindings: arm: add sam9x75 curiosity board Date: Wed, 3 Jul 2024 15:59:36 +0530 Message-ID: <20240703102936.196606-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Changes in v5: - Updated Acked-by tag. --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 82f37328cc69..7160ec80ac1b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -106,6 +106,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 =20 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 --=20 2.25.1 From nobody Fri Dec 19 12:29:58 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED31017BB34; Wed, 3 Jul 2024 10:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002616; cv=none; b=OKaqRe7LBAnJq0rtfRBR5uNuhauBbm3gN5JTTXwT5wLWPWld1WMCEDnm6nAAUBZbgUGlsW2qpZcKK8jcOn5isA8qd2IxxWGrrNwa5mY1Ig29qpSmnV1byseuacPnbiDjEpX4P01EFzusEV5dKBpxRuV7iJuvJbE8eBXw5GNLgy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720002616; c=relaxed/simple; bh=/15Y3Zpi8Var8QL6+W+Mio28E5cOyXXOEi36jOEbS04=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e7vvAQqZH9hY8M69SOAMKGVgbfEs5oLw2R6cwFaqMZgVYxp1mrulxFRh2zuDw1naEMSatEWzXF4yvR6XgiY4uESSgwAUwVqJs100WRvfFbl0oeTkYNIVqGKTN4ss1MLRG3ukXMIiDfipgOlRjoeMKhCuN2tU66MtOgslvp7hh6Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=fail smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=bCdsGAWJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="bCdsGAWJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002615; x=1751538615; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=/15Y3Zpi8Var8QL6+W+Mio28E5cOyXXOEi36jOEbS04=; b=bCdsGAWJWU53fCmYe2aFiLkzxu3/1nFdyBNG3qHNTFrPjkuEN4nwYmtq m9ZDxbTzNNKG9lkGqSdeKl6iQekYXDspSejsZ4V3X6V5jdkDXC4Er4beW eD97v/Z1l4BpBgtfEXPpIZDNIYO29cD/Zuq4vbPvkyXc+Aws5npS0yKxe UtM3MPFh2CZGQSIPrkWNuqI5VO2B2KWQOWtRAWxjtVjk/kGJ81hHxjET8 eOcI1TWMAHEvV4iN7NXjGbFQ/iyGFB7VDnpnOUb8C0y1zIxlK0J4nSDD5 jURXQXq5eIItb2lg0Ar48+DX/WijMOrl14VhtxKQXAOHorCtVFmBtijnR w==; X-CSE-ConnectionGUID: hLLhwY7cQcOyno5TMnxZqQ== X-CSE-MsgGUID: FghAYx1gRYSxDQ+Y/kzGpA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="29441576" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:30:12 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:29:50 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:29:46 -0700 From: Varshini Rajendran To: , , , , , , , , , , Subject: [PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board Date: Wed, 3 Jul 2024 15:59:43 +0530 Message-ID: <20240703102943.196655-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran --- Changes in v5: - Update commit message to match the directory structure. - Alphanumerically sorted Makefile entries. - Corrected VDDCore minimum voltage. - Enabled the i2s node. - Removed additional blank lines. - Enclosed each entry with separate <>. - Corrected pinctrl names to match Microchip convention. - Enabled slewrate in sdmmc node. - Corrected pinmux mask. - Added phandle to leds for ease of access with upcoming device entries. - Updated gpio pin number for red led. --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sam9x75_curiosity.dts | 312 ++++++++++++++++++ 2 files changed, 315 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/micro= chip/Makefile index 0c45c8d17468..470fe46433a9 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -2,6 +2,7 @@ # Enables support for device-tree overlays DTC_FLAGS_at91-sam9x60_curiosity :=3D -@ DTC_FLAGS_at91-sam9x60ek :=3D -@ +DTC_FLAGS_at91-sam9x75_curiosity :=3D -@ DTC_FLAGS_at91-sama5d27_som1_ek :=3D -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek :=3D -@ DTC_FLAGS_at91-sama5d29_curiosity :=3D -@ @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) +=3D \ dtb-$(CONFIG_SOC_SAM9X60) +=3D \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) +=3D \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) +=3D \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/= arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..4a4f14f13634 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Cur= iosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model =3D "Microchip SAM9X75 Curiosity"; + compatible =3D "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,= at91sam9"; + + aliases { + i2c0 =3D &i2c6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_key_gpio_default>; + + button-user { + label =3D "USER"; + gpios =3D <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led_red: led-red { + label =3D "red"; + gpios =3D <&pioC 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_red_led_gpio_default>; + }; + + led_green: led-green { + label =3D "green"; + gpios =3D <&pioC 21 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_green_led_gpio_default>; + }; + + led_blue: led-blue { + label =3D "blue"; + gpios =3D <&pioC 20 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_blue_led_gpio_default>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + memory@20000000 { + reg =3D <0x20000000 0x10000000>; + device_type =3D "memory"; + }; +}; + +&classd { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_classd_default>; + atmel,pwm-type =3D "diff"; + atmel,non-overlap-time =3D <10>; + status =3D "okay"; +}; + +&dbgu { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dbgu_default>; + status =3D "okay"; +}; + +&dma0 { + status =3D "okay"; +}; + +&flx6 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "okay"; + + pmic@5b { + compatible =3D "microchip,mcp16502"; + reg =3D <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name =3D "VDD_IO"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name =3D "VDD_DDR"; + regulator-min-microvolt =3D <1283000>; + regulator-max-microvolt =3D <1450000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1210000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name =3D "VDD_OTHER"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3600000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2s_default>; + #sound-dai-cells =3D <0>; + status =3D "okay"; +}; + +&main_xtal { + clock-frequency =3D <24000000>; +}; + +&pinctrl { + classd { + pinctrl_classd_default: classd-default { + atmel,pins =3D + , + ; + }; + }; + + dbgu { + pinctrl_dbgu_default: dbgu-default { + atmel,pins =3D , + ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-default { + atmel,pins =3D + , + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins =3D ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s-default { + atmel,pins =3D + , /* I2SCK */ + , /* I2SWS */ + , /* I2SDIN */ + , /* I2SDOUT */ + ; /* I2SMCK */ + }; + }; + + leds { + pinctrl_red_led_gpio_default: red-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_green_led_gpio_default: green-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_blue_led_gpio_default: blue-led-gpio-default { + atmel,pins =3D ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0-default { + atmel,pins =3D + , /* PA2 CK periph A with pullup */ + , /* PA1 CMD periph A with pullup = */ + , /* PA0 DAT0 periph A */ + , /* PA3 DAT1 periph A with pullup= */ + , /* PA4 DAT2 periph A with pullup= */ + ; /* PA5 DAT3 periph A with pullup= */ + }; + }; +}; /* pinctrl */ + +&rtt { + atmel,rtt-rtc-time-reg =3D <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc0_default>; + cd-gpios =3D <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status =3D "okay"; +}; + +&slow_xtal { + clock-frequency =3D <32768>; +}; + +&poweroff { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + +&trng { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.25.1