From nobody Fri Dec 19 09:10:50 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C425D1B4C2A for ; Tue, 2 Jul 2024 13:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719926507; cv=none; b=qVzStiNs40KHf1R33p2xGrHZVeATNvFcoLseqE3XXMXZtx/1JiA9SWom/49M2UrxclA5mF1ISWytLWfMEcoG3vFsW/WoPstI3YxzJAhDk0sR6MOnAQjQc1hJv9+YcaR66FMOdLfoP52bdJSPCtnbCQkzgdBI3hYuKdHLlu3GGhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719926507; c=relaxed/simple; bh=WzLgCcnAxpfAtzGdhmiECVNup9bFZxesCcTltcURVhs=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Cfnpclh0xp5M0Sn8TEtCdmu/FG39RkIkWYMF5JNCVZUu8Za5Uw1MonI/dYu9czbeNZ9+XIcxPWwUNSDU9lEGRLDkfB4B7TPT0RmXQEUgqlzzqTNx2oWl6vaHPezefpvDMX2i9M/zeGRrWeepyKjToN5//VW4iAxQIYvphWIKkcA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--yosryahmed.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ITw5Vyik; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--yosryahmed.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ITw5Vyik" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-650f766a1c6so27477b3.0 for ; Tue, 02 Jul 2024 06:21:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1719926505; x=1720531305; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=/1dVnzezxakkrWVDD24n/jxIBS1JtulZK9cr/kIqgsY=; b=ITw5VyikG4zvXRhP8UNTVWNYzi5s2Bq+mAVgygqs1A3srgP35jZmUD8OAqo9AEUXa9 CvFZYYtqauxu8/tJHL+6eMqnXgJ1/pUWEY6Embyd1jRJArhlv7+OlEjmobN9jzA+pZ58 y3OczPXZ79ptucOviX5jTswUtbnVNfAW2YQSspWvYl8jAxxCUPym3vt1MWF/4dq0pRxd 83o0h0JaHLeLq44udkV7ktpyFtGHvuBsI68mM4V6nGuihP/1YgG+kAZwA6BR+juZd6YI zWTmzL1EiZYvw+ru0hOobIRqUPhIG7dpySvJ/PAjdNm+/YWngLTevBZX68/g/0oZOrkK wLmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719926505; x=1720531305; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/1dVnzezxakkrWVDD24n/jxIBS1JtulZK9cr/kIqgsY=; b=kvOONOQm1FlS7zzxshIBXiAVVoFk/hU1yAPL3opu4Qra5Lz4+MgzQewL/6SA02BV1W 73b2lcy4q37lZyZL83vc2z5JtUcYLHCMALyt26FoV2vmuQWwVo5b5NGq1S5483rsCe2f pfo8AceIx6jW1XD4/Prjan6z2Qie8qn4ygFDwR3VGBW8K7ELDlKpFMrfRVeaWHoizCVh ZhnqM/1kA7VUnRF/JBRvoLFf+oba1VciZ4atkF9C9R9+wDVVuL4GHfpffnbMtacLsi9H hI7eTBauZSd+/uxIQpXNegdld5ETYwVkSQkCoPuivsjT2nopgoXzm81LdJ91h+VFPnxg Jfqw== X-Forwarded-Encrypted: i=1; AJvYcCWjRKueoGTLqG6JtRw3XWyHtedsgXgZ/nCoUdZx+P9qeQOd0IpFUf/byb+pXON7vJltKevGIBdEBmmFPP18FP9WzKvKAXUJ+pcGx4Qp X-Gm-Message-State: AOJu0Yzjz99ZMVlGnR4gi1TZ5+stq+01uKM4u7FDhw7MiJbG+NqbB0kX u0uO+6eGZI5b+Kaz7MS9s7QygJlu1/acRaI94JZv+8M8IoFnSagR7eyjjlbQ3TfbGEGpdOvF6Mu aozmGATsjkFeW3zm70A== X-Google-Smtp-Source: AGHT+IHghuJQ8nulRpb2JfS2RyKKlSW+eKRndDAd54bTQK3f3q6ozzQyqfLRhWOFhsZ+LsF1X/jGe3dnEw1HTZPM X-Received: from yosry.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:29b4]) (user=yosryahmed job=sendgmr) by 2002:a0d:e885:0:b0:61c:89a4:dd5f with SMTP id 00721157ae682-64c72b5434amr740227b3.0.1719926504753; Tue, 02 Jul 2024 06:21:44 -0700 (PDT) Date: Tue, 2 Jul 2024 13:21:37 +0000 In-Reply-To: <20240702132139.3332013-1-yosryahmed@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240702132139.3332013-1-yosryahmed@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240702132139.3332013-2-yosryahmed@google.com> Subject: [RESEND PATCH v3 1/3] x86/mm: Use IPIs to synchronize LAM enablement From: Yosry Ahmed To: x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , "Kirill A. Shutemov" , Rick Edgecombe , Andrew Morton , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Yosry Ahmed Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAM can only be enabled when a process is single-threaded. But _kernel_ threads can temporarily use a single-threaded process's mm. If LAM is enabled by a userspace process while a kthread is using its mm, the kthread will not observe LAM enablement (i.e. LAM will be disabled in CR3). This could be fine for the kthread itself, as LAM only affects userspace addresses. However, if the kthread context switches to a thread in the same userspace process, CR3 may or may not be updated because the mm_struct doesn't change (based on pending TLB flushes). If CR3 is not updated, the userspace thread will run incorrectly with LAM disabled, which may cause page faults when using tagged addresses. Example scenario: CPU 1 CPU 2 /* kthread */ kthread_use_mm() /* user thread */ prctl_enable_tagged_addr() /* LAM enabled on CPU 2 */ /* LAM disabled on CPU 1 */ context_switch() /* to CPU 1 */ /* Switching to user thread */ switch_mm_irqs_off() /* CR3 not updated */ /* LAM is still disabled on CPU 1 */ Synchronize LAM enablement by sending an IPI from prctl_enable_tagged_addr() to all CPUs running with the mm_struct to enable LAM. This makes sure LAM is enabled on CPU 1 in the above scenario before prctl_enable_tagged_addr() returns and userspace starts using tagged addresses, and before it's possible to run the userspace process on CPU 1. In switch_mm_irqs_off(), move reading the LAM mask until after mm_cpumask() is updated. This ensures that if an outdated LAM mask is written to CR3, an IPI is received to update it right after IRQs are re-enabled. Fixes: 82721d8b25d7 ("x86/mm: Handle LAM on context switch") Suggested-by: Andy Lutomirski Reviewed-by: Kirill A. Shutemov Change-Id: I7fd573a9db5fe5284d69bc46f9b3758f1f9fb467 Signed-off-by: Yosry Ahmed --- arch/x86/kernel/process_64.c | 13 +++++++++++-- arch/x86/mm/tlb.c | 7 +++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 6d3d20e3e43a9..e1ce0dfd24258 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -798,6 +798,16 @@ static long prctl_map_vdso(const struct vdso_image *im= age, unsigned long addr) =20 #define LAM_U57_BITS 6 =20 +static void enable_lam_func(void *__mm) +{ + struct mm_struct *mm =3D __mm; + + if (this_cpu_read(cpu_tlbstate.loaded_mm) =3D=3D mm) { + write_cr3(__read_cr3() | mm->context.lam_cr3_mask); + set_tlbstate_lam_mode(mm); + } +} + static int prctl_enable_tagged_addr(struct mm_struct *mm, unsigned long nr= _bits) { if (!cpu_feature_enabled(X86_FEATURE_LAM)) @@ -830,8 +840,7 @@ static int prctl_enable_tagged_addr(struct mm_struct *m= m, unsigned long nr_bits) return -EINVAL; } =20 - write_cr3(__read_cr3() | mm->context.lam_cr3_mask); - set_tlbstate_lam_mode(mm); + on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); set_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags); =20 mmap_write_unlock(mm); diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 44ac64f3a047c..a041d2ecd8380 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -503,9 +503,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, { struct mm_struct *prev =3D this_cpu_read(cpu_tlbstate.loaded_mm); u16 prev_asid =3D this_cpu_read(cpu_tlbstate.loaded_mm_asid); - unsigned long new_lam =3D mm_lam_cr3_mask(next); bool was_lazy =3D this_cpu_read(cpu_tlbstate_shared.is_lazy); unsigned cpu =3D smp_processor_id(); + unsigned long new_lam; u64 next_tlb_gen; bool need_flush; u16 new_asid; @@ -619,9 +619,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, cpumask_clear_cpu(cpu, mm_cpumask(prev)); } =20 - /* - * Start remote flushes and then read tlb_gen. - */ + /* Start receiving IPIs and then read tlb_gen (and LAM below) */ if (next !=3D &init_mm) cpumask_set_cpu(cpu, mm_cpumask(next)); next_tlb_gen =3D atomic64_read(&next->context.tlb_gen); @@ -633,6 +631,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, barrier(); } =20 + new_lam =3D mm_lam_cr3_mask(next); set_tlbstate_lam_mode(next); if (need_flush) { this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); --=20 2.45.2.803.g4e1b14247a-goog From nobody Fri Dec 19 09:10:50 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77BB1B4C2C for ; Tue, 2 Jul 2024 13:21:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719926509; cv=none; b=fHDBbOmyYeZBkc0cFnt7bu0mpRGNJj96PjR3WZ+8PrOsVokX1Cl81HYM2/e2JFxSb/criTOA0JMb5j4yYvo227p8DYS+iinmpS/pJxzYhbw5z1QAmO/L9BPoKC31n4LJeC6LHbkU2v0qF9QcPG+HZfAETcSX4wyGWz4DY5Z5RN0= ARC-Message-Signature: i=1; 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AJvYcCXSo8B45b2WZ2OKTq06fsWy31/KAId97vl5P2/ePYBDF0/QbGZydCrpOwiZ1RpYU8VSDZWMKRdxqW3wOwLtc5vNOme09APGeZjdKxho X-Gm-Message-State: AOJu0YwmHSdCTFsT/1QEQ4sPf7OnYc6QMAIXWwIifPKhx6pr6snr+Zb8 vLrIbmV+RdXsWAlM5F8lPSnH299oH4heW2BVMgv10KuJMGDEWSrA52APq9W01Jqa5rWyVIYgwgk /SLS7TqDPecwngFk9/A== X-Google-Smtp-Source: AGHT+IE5yOxXHFsN9w/WFqj9GD2Jlu4F+FUycVLVxC5570M2iHpzwIws1dqPsB11Seccelx0/1egw1GKNVlINZNd X-Received: from yosry.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:29b4]) (user=yosryahmed job=sendgmr) by 2002:a0d:e644:0:b0:62c:f623:3a4e with SMTP id 00721157ae682-64c6e5c126dmr289017b3.0.1719926506628; Tue, 02 Jul 2024 06:21:46 -0700 (PDT) Date: Tue, 2 Jul 2024 13:21:38 +0000 In-Reply-To: <20240702132139.3332013-1-yosryahmed@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240702132139.3332013-1-yosryahmed@google.com> X-Mailer: git-send-email 2.45.2.803.g4e1b14247a-goog Message-ID: <20240702132139.3332013-3-yosryahmed@google.com> Subject: [RESEND PATCH v3 2/3] x86/mm: Fix LAM inconsistency during context switch From: Yosry Ahmed To: x86@kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , "Kirill A. Shutemov" , Rick Edgecombe , Andrew Morton , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Yosry Ahmed Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAM can only be enabled when a process is single-threaded. But _kernel_ threads can temporarily use a single-threaded process's mm. That means that a context-switching kernel thread can race and observe the mm's LAM metadata (mm->context.lam_cr3_mask) change. The context switch code does two logical things with that metadata: populate CR3 and populate 'cpu_tlbstate.lam'. If it hits this race, 'cpu_tlbstate.lam' and CR3 can end up out of sync. This de-synchronization is currently harmless. But it is confusing and might lead to warnings or real bugs. Update set_tlbstate_lam_mode() to take in the LAM mask and untag mask instead of an mm_struct pointer, and while we are at it, rename it to cpu_tlbstate_update_lam(). This should also make it clearer that we are updating cpu_tlbstate. In switch_mm_irqs_off(), read the LAM mask once and use it for both the cpu_tlbstate update and the CR3 update. Reviewed-by: Kirill A. Shutemov Change-Id: I8bcf94bbf28ebdbbe75e3939e712246a029f84b6 Signed-off-by: Yosry Ahmed --- arch/x86/include/asm/mmu_context.h | 8 +++++++- arch/x86/include/asm/tlbflush.h | 9 ++++----- arch/x86/kernel/process_64.c | 6 ++++-- arch/x86/mm/tlb.c | 8 +++++--- 4 files changed, 20 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index 8dac45a2c7fcf..19091ebb86338 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -88,7 +88,13 @@ static inline void switch_ldt(struct mm_struct *prev, st= ruct mm_struct *next) #ifdef CONFIG_ADDRESS_MASKING static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) { - return mm->context.lam_cr3_mask; + /* + * When switch_mm_irqs_off() is called for a kthread, it may race with + * LAM enablement. switch_mm_irqs_off() uses the LAM mask to do two + * things: populate CR3 and populate 'cpu_tlbstate.lam'. Make sure it + * reads a single value for both. + */ + return READ_ONCE(mm->context.lam_cr3_mask); } =20 static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index 25726893c6f4d..69e79fff41b80 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -399,11 +399,10 @@ static inline u64 tlbstate_lam_cr3_mask(void) return lam << X86_CR3_LAM_U57_BIT; } =20 -static inline void set_tlbstate_lam_mode(struct mm_struct *mm) +static inline void cpu_tlbstate_update_lam(unsigned long lam, u64 untag_ma= sk) { - this_cpu_write(cpu_tlbstate.lam, - mm->context.lam_cr3_mask >> X86_CR3_LAM_U57_BIT); - this_cpu_write(tlbstate_untag_mask, mm->context.untag_mask); + this_cpu_write(cpu_tlbstate.lam, lam >> X86_CR3_LAM_U57_BIT); + this_cpu_write(tlbstate_untag_mask, untag_mask); } =20 #else @@ -413,7 +412,7 @@ static inline u64 tlbstate_lam_cr3_mask(void) return 0; } =20 -static inline void set_tlbstate_lam_mode(struct mm_struct *mm) +static inline void cpu_tlbstate_update_lam(unsigned long lam, u64 untag_ma= sk) { } #endif diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index e1ce0dfd24258..26a853328f2d4 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -801,10 +801,12 @@ static long prctl_map_vdso(const struct vdso_image *i= mage, unsigned long addr) static void enable_lam_func(void *__mm) { struct mm_struct *mm =3D __mm; + unsigned long lam; =20 if (this_cpu_read(cpu_tlbstate.loaded_mm) =3D=3D mm) { - write_cr3(__read_cr3() | mm->context.lam_cr3_mask); - set_tlbstate_lam_mode(mm); + lam =3D mm_lam_cr3_mask(mm); + write_cr3(__read_cr3() | lam); + cpu_tlbstate_update_lam(lam, mm_untag_mask(mm)); } } =20 diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index a041d2ecd8380..1fe9ba33c5805 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include #include @@ -632,7 +633,6 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, } =20 new_lam =3D mm_lam_cr3_mask(next); - set_tlbstate_lam_mode(next); if (need_flush) { this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); @@ -651,6 +651,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struc= t mm_struct *next, =20 this_cpu_write(cpu_tlbstate.loaded_mm, next); this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); + cpu_tlbstate_update_lam(new_lam, mm_untag_mask(next)); =20 if (next !=3D prev) { cr4_update_pce_mm(next); @@ -697,6 +698,7 @@ void initialize_tlbstate_and_flush(void) int i; struct mm_struct *mm =3D this_cpu_read(cpu_tlbstate.loaded_mm); u64 tlb_gen =3D atomic64_read(&init_mm.context.tlb_gen); + unsigned long lam =3D mm_lam_cr3_mask(mm); unsigned long cr3 =3D __read_cr3(); =20 /* Assert that CR3 already references the right mm. */ @@ -704,7 +706,7 @@ void initialize_tlbstate_and_flush(void) =20 /* LAM expected to be disabled */ WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)); - WARN_ON(mm_lam_cr3_mask(mm)); + WARN_ON(lam); =20 /* * Assert that CR4.PCIDE is set if needed. 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Peter Anvin" , Andy Lutomirski , Peter Zijlstra , "Kirill A. Shutemov" , Rick Edgecombe , Andrew Morton , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Yosry Ahmed Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are two separate checks in prctl_enable_tagged_addr() that nr_bits is in the correct range. The checks are arranged such the correct case is sandwiched between both error cases, which do exactly the same thing. Simplify the if condition and pull the correct case outside with the rest of the success code path. Reviewed-by: Kirill A. Shutemov Change-Id: Ia4f78de99d02f8ce28787346404d59ef13ca3d92 Signed-off-by: Yosry Ahmed --- arch/x86/kernel/process_64.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 26a853328f2d4..c62098332f05c 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -831,17 +831,13 @@ static int prctl_enable_tagged_addr(struct mm_struct = *mm, unsigned long nr_bits) return -EBUSY; } =20 - if (!nr_bits) { - mmap_write_unlock(mm); - return -EINVAL; - } else if (nr_bits <=3D LAM_U57_BITS) { - mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; - mm->context.untag_mask =3D ~GENMASK(62, 57); - } else { + if (!nr_bits || nr_bits > LAM_U57_BITS) { mmap_write_unlock(mm); return -EINVAL; } =20 + mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; + mm->context.untag_mask =3D ~GENMASK(62, 57); on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); set_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags); =20 --=20 2.45.2.803.g4e1b14247a-goog