From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7706719D8AF for ; Tue, 2 Jul 2024 13:11:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925886; cv=none; b=mSW+I89R8I8Fic3OCkMLhxhLTFoicY9TVgEYLuYtRgDRHHL0Ycs8LsZnpHT+Jr8V1y0pRFB9z/MN0Ufwk4jET+Ft6l0FNyaXuethTgw2g+fZwvE5TsMZG6OAngWKncrpbsCo7ypGXw8P0QCI3IpHPkkMbjnTEG9oJsrUrHDquVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925886; c=relaxed/simple; bh=+g/siJnzmZoFiX3UTf80ep+rreHDj09IRPBQNzXe1gw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RKG1nUOy/xnLwcrSWFPf2URu37hhBnPHAL/Hl3ZcGyNZ4GMsXPjLfXBKJPI1BfO25QFdQAHmLldePFo+EBowtaYbZqlBk2WqMChJ+tgUg+rnq+g+Ow9garPntO3oCkI9jUM6jtvEirafTNljaGkt2I9VVr3Q/78gh/OznkHFKhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l4D3PyWy; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l4D3PyWy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719925886; x=1751461886; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+g/siJnzmZoFiX3UTf80ep+rreHDj09IRPBQNzXe1gw=; b=l4D3PyWyVrxuPpvhbZYp+TU9LzjT1JbCbFxWwrz1TXnyrE0VMlf9Jaxo 1JKD3T/XyR+qbraPIa5kp/q0XJL4SJzvLJ9w3cyzR8MvWN7hdXVMkxZU2 V+jbZtlYv5K2qXzwBEy5n/L9HJk8oKEwiVnxexjf0ty4+P+tn9qIdfQOf KFQE4xZUio4xZCcl7zX6RntDGqQKPJaV+be9vq7f1b0+NbqsY2uug6E4D p2g+iSlXu6P+j0K0FsD7OFMfPlETY9YCuYGKrx7UCKcFNjc5Kfq/pRDvX YhImGnC+mVeuSnXU/5jCfIrw3YRorAxZvc6UYob+8pggFqc6O0rjM8jb2 A==; X-CSE-ConnectionGUID: 5n72zuEHQiy3yXCHATSRnw== X-CSE-MsgGUID: SXt2XBmUTQuwxFK1enXXeA== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="27699994" X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="27699994" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 06:11:25 -0700 X-CSE-ConnectionGUID: wLdcj0pCSjqrsCSOpmUzDQ== X-CSE-MsgGUID: /RTKjcrDS4C5AmdTfY00PA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="50250830" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:23 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] iommu/vt-d: Handle volatile descriptor status read Date: Tue, 2 Jul 2024 21:08:33 +0800 Message-Id: <20240702130839.108139-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jacob Pan Queued invalidation wait descriptor status is volatile in that IOMMU hardware writes the data upon completion. Use READ_ONCE() to prevent compiler optimizations which ensures memory reads every time. As a side effect, READ_ONCE() also enforces strict types and may add an extra instruction. But it should not have negative performance impact since we use cpu_relax anyway and the extra time(by adding an instruction) may allow IOMMU HW request cacheline ownership easier. e.g. gcc 12.3 BEFORE: 81 38 ad de 00 00 cmpl $0x2,(%rax) AFTER (with READ_ONCE()) 772f: 8b 00 mov (%rax),%eax 7731: 3d ad de 00 00 cmp $0x2,%eax //status data is 32 bit Signed-off-by: Jacob Pan Reviewed-by: Kevin Tian Reviewed-by: Yi Liu Link: https://lore.kernel.org/r/20240607173817.3914600-1-jacob.jun.pan@linu= x.intel.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/dmar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index 304e84949ca7..1c8d3141cb55 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1446,7 +1446,7 @@ int qi_submit_sync(struct intel_iommu *iommu, struct = qi_desc *desc, */ writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); =20 - while (qi->desc_status[wait_index] !=3D QI_DONE) { + while (READ_ONCE(qi->desc_status[wait_index]) !=3D QI_DONE) { /* * We will leave the interrupts disabled, to prevent interrupt * context to queue another cmd while a cmd is already submitted --=20 2.34.1 From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C96A19DF82 for ; Tue, 2 Jul 2024 13:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925888; cv=none; b=abY7Gsvnn00+/uv26QfFhqJF1LNFEPZ0c7uBdB8J8Nc2XDCs6RLD6gT/WRdky8IB9YXk76b65DrYOCRXHNVYW4A6E79Gk/Nl9wGZMwZ3VvF7IT5vCDNet4V5Z5mR7cBGYhSriJFMpPmogsJX5oiIGvgqm5gpDPbJpKwatHAVJDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925888; c=relaxed/simple; bh=As/Aykdbt4v6c2/zxur0icfFP/KzwqKu7AKzmNTPDcw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pHXHUT6vzrdo7eP9ktVWSMGxoBznTZQaybsbmESHuOryeL/YQzuoEe4cAQmy9w8uttcbdZJUhBtUW+t+lDGk+Ran0AF6n4gD1/dFckcoG9Gm8J967jMbFVYdeV+KF94skj5Ahd1IQPYC0rSk0bE2o/UFUnikE8MFmpAaiCuOqU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=alNJDMZ5; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="alNJDMZ5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719925887; x=1751461887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=As/Aykdbt4v6c2/zxur0icfFP/KzwqKu7AKzmNTPDcw=; b=alNJDMZ56com2/WlphFtcGaJlyYK32DlATLbG0kAP9Bp4xgIjdLrar3I 4mjEbSEG7PROImybLEVXe389tbz0mC3b10PgXru04xDlHNy7I/2Jy1Jau nrEUKpOm9xRWt+5qM8C5/cAeSYf4RzRpRMqLs/P6T1ajct1h/XwG9PYYX 9QYdbxNqY3cwd0ym65zaA3OUemHh2RDsMUX22Lf+0B360StgjoS+q5Lxr V7I7kjttuDyR9AJ35163iD+dBPNOCtWxu9TxkXPfxXntmGRqzJXB9AOEM eWHxZ8Sjo9VpQ3L8AF/P2D5gJiefuTsB+isL0vflCcoZs9LxjtEQttt4+ A==; X-CSE-ConnectionGUID: qP9qrBN8T7m75KUUA86g6A== X-CSE-MsgGUID: a8rrbJlGS8i9utMf9o/o7w== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="27700007" X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="27700007" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 06:11:26 -0700 X-CSE-ConnectionGUID: GjlT4eamQJypxR+LYADpHA== X-CSE-MsgGUID: MoMOyer4Q1uXsxLw/Dkazw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="50250835" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:25 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] iommu/vt-d: Remove comment for def_domain_type Date: Tue, 2 Jul 2024 21:08:34 +0800 Message-Id: <20240702130839.108139-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The comment for def_domain_type is outdated. Part of it is irrelevant. Furthermore, it could just be deleted since the iommu_ops::def_domain_type callback is properly documented in iommu.h, so individual implementations shouldn't need to repeat that. Remove it to avoid confusion. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240624024327.234979-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/iommu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 2e9811bf2a4e..abf0097f899d 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2177,17 +2177,6 @@ static bool device_rmrr_is_relaxable(struct device *= dev) return false; } =20 -/* - * Return the required default domain type for a specific device. - * - * @dev: the device in query - * @startup: true if this is during early boot - * - * Returns: - * - IOMMU_DOMAIN_DMA: device requires a dynamic mapping domain - * - IOMMU_DOMAIN_IDENTITY: device requires an identical mapping domain - * - 0: both identity and dynamic domains work for this device - */ static int device_def_domain_type(struct device *dev) { if (dev_is_pci(dev)) { --=20 2.34.1 From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 217DC19F469 for ; Tue, 2 Jul 2024 13:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925889; cv=none; b=YcUOX1CyuPwvmScKrc30sT63KUcWkl93lTC/ZWP73c7CuzPMjfq5D0xDWy22H2hZoBL5O0eTAgVFATpnLLejIUjNPc14BGX7LfK8J4FtW0tUxE7hoJvIf1B383z4wyNrtL2oo3Vrz7dntU0puzFnBTDUS4XfsgRF8ZmnvjIuHCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925889; c=relaxed/simple; bh=FYr95xHGLyR8gxK+4isyHcMbebbiTUqWfj8JkY18UaI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gNderpBWXAdX8RaQq06dD0r5ZAapQ0b92nn/UmkzVBgMCJJzSc4CmmL2+o8sH02z/C6go53r5WeW6wI1oMqogsBSv59byln6ob7xS9fxk+6fre2HmQmdeSkG9GaVyTq7EP05Iv4GBkozRnvBlfU8sepd9ZAy1wfx+/UW94YLaGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=c1lwwJJf; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c1lwwJJf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719925888; x=1751461888; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FYr95xHGLyR8gxK+4isyHcMbebbiTUqWfj8JkY18UaI=; b=c1lwwJJf/WYfPq1qvP7rV4ClBrrLKVig9UgLOYUfCab8Lxmz3MBNZD24 Xx9lFADRRbbJrosvhopnW8P93ChLMyjIoVf2HlkS4FlBcdQZp/sWbmQpY pN8abzneptfQ7mhyucTH5fDLMmEUje9yy8lK1a3zQawhPVmgo5IlorKbd ixtmugXhEU7itNgiAy86wKa151ZBlfn1S590+A252UTqwrQcgpBSv0GMJ YRud0PQPV9Csg8Uj5EITXaBlSJ3o55X9+DPlcyKD9VeXr6t7Ok8taaYin /+GD2jVqsVPheQftfMkVLbFrGGou7BQYJwwVDAkT1RWLXvbUf1kMSemyx w==; X-CSE-ConnectionGUID: k0qdbjUUSgm4FzSv89+WKQ== X-CSE-MsgGUID: CAfLLZGPRoiayM0rGhGv6A== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="27700016" X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="27700016" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 06:11:28 -0700 X-CSE-ConnectionGUID: JssnfPapTwymgI/vKRSGLw== X-CSE-MsgGUID: OtleRZBiT+6RnFPyeLh3iA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="50250844" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:26 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] iommu/vt-d: Remove control over Execute-Requested requests Date: Tue, 2 Jul 2024 21:08:35 +0800 Message-Id: <20240702130839.108139-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The VT-d specification has removed architectural support of the requests with pasid with a value of 1 for Execute-Requested (ER). And the NXE bit in the pasid table entry and XD bit in the first-stage paging Entries are deprecated accordingly. Remove the programming of these bits to make it consistent with the spec. Suggested-by: Jacob Pan Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240624032351.249858-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/iommu.h | 6 ++---- drivers/iommu/intel/pasid.h | 10 ---------- drivers/iommu/intel/iommu.c | 4 ++-- drivers/iommu/intel/pasid.c | 1 - 4 files changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index eaf015b4353b..9a3b064126de 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -49,7 +49,6 @@ #define DMA_FL_PTE_US BIT_ULL(2) #define DMA_FL_PTE_ACCESS BIT_ULL(5) #define DMA_FL_PTE_DIRTY BIT_ULL(6) -#define DMA_FL_PTE_XD BIT_ULL(63) =20 #define DMA_SL_PTE_DIRTY_BIT 9 #define DMA_SL_PTE_DIRTY BIT_ULL(DMA_SL_PTE_DIRTY_BIT) @@ -831,11 +830,10 @@ static inline void dma_clear_pte(struct dma_pte *pte) static inline u64 dma_pte_addr(struct dma_pte *pte) { #ifdef CONFIG_64BIT - return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); + return pte->val & VTD_PAGE_MASK; #else /* Must have a full atomic 64-bit read */ - return __cmpxchg64(&pte->val, 0ULL, 0ULL) & - VTD_PAGE_MASK & (~DMA_FL_PTE_XD); + return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; #endif } =20 diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h index da9978fef7ac..dde6d3ba5ae0 100644 --- a/drivers/iommu/intel/pasid.h +++ b/drivers/iommu/intel/pasid.h @@ -247,16 +247,6 @@ static inline void pasid_set_page_snoop(struct pasid_e= ntry *pe, bool value) pasid_set_bits(&pe->val[1], 1 << 23, value << 23); } =20 -/* - * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID - * entry. It is required when XD bit of the first level page table - * entry is about to be set. - */ -static inline void pasid_set_nxe(struct pasid_entry *pe) -{ - pasid_set_bits(&pe->val[2], 1 << 5, 1 << 5); -} - /* * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode * PASID entry. diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index abf0097f899d..1b5519dfa085 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -854,7 +854,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domai= n *domain, domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); pteval =3D ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DM= A_PTE_READ | DMA_PTE_WRITE; if (domain->use_first_level) - pteval |=3D DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; + pteval |=3D DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; =20 tmp =3D 0ULL; if (!try_cmpxchg64(&pte->val, &tmp, pteval)) @@ -1872,7 +1872,7 @@ __domain_mapping(struct dmar_domain *domain, unsigned= long iov_pfn, attr =3D prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP); attr |=3D DMA_FL_PTE_PRESENT; if (domain->use_first_level) { - attr |=3D DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; + attr |=3D DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; if (prot & DMA_PTE_WRITE) attr |=3D DMA_FL_PTE_DIRTY; } diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index abce19e2ad6f..aabcdf756581 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -333,7 +333,6 @@ int intel_pasid_setup_first_level(struct intel_iommu *i= ommu, pasid_set_domain_id(pte, did); pasid_set_address_width(pte, iommu->agaw); pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); - pasid_set_nxe(pte); =20 /* Setup Present and PASID Granular Transfer Type: */ pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY); --=20 2.34.1 From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E5631A00F6 for ; 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X-CSE-ConnectionGUID: XeB7VmZqSeepwtUdNEZRHg== X-CSE-MsgGUID: lwM0SE4zQduZ/TCJIjAytw== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="27700021" X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="27700021" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 06:11:30 -0700 X-CSE-ConnectionGUID: 3IQ/xsymR+uNK7moAq5DeA== X-CSE-MsgGUID: t1Iz1HeAQNCstEh9CuTRjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="50250848" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:28 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] iommu/vt-d: Downgrade warning for pre-enabled IR Date: Tue, 2 Jul 2024 21:08:36 +0800 Message-Id: <20240702130839.108139-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Emitting a warning is overkill in intel_setup_irq_remapping() since the interrupt remapping is pre-enabled. For example, there's no guarantee that kexec will explicitly disable interrupt remapping before booting a new kernel. As a result, users are seeing warning messages like below when they kexec boot a kernel, though there is nothing wrong: DMAR-IR: IRQ remapping was enabled on dmar18 but we are not in kdump mode DMAR-IR: IRQ remapping was enabled on dmar17 but we are not in kdump mode DMAR-IR: IRQ remapping was enabled on dmar16 but we are not in kdump mode ... ... Downgrade the severity of this message to avoid user confusion. CC: Paul Menzel Link: https://lore.kernel.org/linux-iommu/5517f76a-94ad-452c-bae6-34ecc0ec4= 831@molgen.mpg.de/ Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240625043912.258036-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/irq_remapping.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index e4a70886678c..e090ca07364b 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -597,8 +597,8 @@ static int intel_setup_irq_remapping(struct intel_iommu= *iommu) =20 if (ir_pre_enabled(iommu)) { if (!is_kdump_kernel()) { - pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n= ", - iommu->name); + pr_info_once("IRQ remapping was enabled on %s but we are not in kdump m= ode\n", + iommu->name); clear_ir_pre_enabled(iommu); iommu_disable_irq_remapping(iommu); } else if (iommu_load_old_irte(iommu)) --=20 2.34.1 From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D9071A2FBA for ; Tue, 2 Jul 2024 13:11:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925894; cv=none; b=onfT48ngY2tphXXOZLuf4n0sUj92NHfP4F8c+0oBDnUCCEUbyYR+Szl3Y/LlDwGzlf9eaYkFyyO+CipHS1mFDTHwE5O0e+VYw9+rvFGV5ZW/MWFD72wURRY2L18J5OkQjrrEM5GcKD+2Qh6D0Mo8wcwTyqpEjVJh6Wa4UeH2WoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925894; c=relaxed/simple; bh=CPNrATy825FEHzfvGjy5SHzIN9+YwYaoDVHNJTLIPw4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Sr+q8RgtBLj17zWKlnluxK0GmmEctdbl5lVMDmE0Jww82c1id0HCKgjDnhio6PRFqcoEBgQb1Lq8EZ9bFhe9j3E0mu0DX2hE5Dm9G4MqC9952pbk8eU5MExJSdH61OWchzorKTf2S6WUYLXo9eToIK4OOUeO3rbHjhOSASpW3QQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YUFK4xF+; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YUFK4xF+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719925893; x=1751461893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CPNrATy825FEHzfvGjy5SHzIN9+YwYaoDVHNJTLIPw4=; b=YUFK4xF+g+YtoYgyHAfOIzbBBIn3iZTx3d8Z63pCIWqu/9IIwvxbvxbl +9BreJCMsUpZlROiNRXJ3BibV5vKcxXm0uURocIbAy7EPBYHd3Ihcs2QG RDm3IHHIt4vTa1Y+13B7/jNPUT6Dtc2xgBZ5f4FJZRSPa7to5othurLu6 mxydVAkt5Qd8FghB/UOvghzs0v6dlrkYkV45iBZrzdA1N2izRgeDsOauh qUsGccP5RrJxG4InimvDLAjXHtBbxTw4PzpS1MDoBjNmiw0dKnB6vRyQh XQyNrzdQlPdf/KfekRjSddnzm042cLC+/dWaonMU0yUtiPmsEYsyYBfIF w==; X-CSE-ConnectionGUID: uOrCGD3sROSNSrLFQT99xA== X-CSE-MsgGUID: lqJWf3gQRJKgx3Q+feTQqg== X-IronPort-AV: E=McAfee;i="6700,10204,11121"; a="27700027" X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="27700027" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2024 06:11:31 -0700 X-CSE-ConnectionGUID: a18cdenGTiS7mLRWcz78Tg== X-CSE-MsgGUID: 6YIkVVFwRiC5+Hz3MvS1mA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,178,1716274800"; d="scan'208";a="50250850" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:29 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] iommu/vt-d: Add helper to allocate paging domain Date: Tue, 2 Jul 2024 21:08:37 +0800 Message-Id: <20240702130839.108139-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The domain_alloc_user operation is currently implemented by allocating a paging domain using iommu_domain_alloc(). This is because it needs to fully initialize the domain before return. Add a helper to do this to avoid using iommu_domain_alloc(). Signed-off-by: Lu Baolu Reviewed-by: Jason Gunthorpe Link: https://lore.kernel.org/r/20240610085555.88197-16-baolu.lu@linux.inte= l.com Reviewed-by: Yi Liu --- drivers/iommu/intel/iommu.c | 90 +++++++++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 1b5519dfa085..1f0d6892a0b6 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3622,6 +3622,79 @@ static struct iommu_domain blocking_domain =3D { } }; =20 +static int iommu_superpage_capability(struct intel_iommu *iommu, bool firs= t_stage) +{ + if (!intel_iommu_superpage) + return 0; + + if (first_stage) + return cap_fl1gp_support(iommu->cap) ? 2 : 1; + + return fls(cap_super_page_val(iommu->cap)); +} + +static struct dmar_domain *paging_domain_alloc(struct device *dev, bool fi= rst_stage) +{ + struct device_domain_info *info =3D dev_iommu_priv_get(dev); + struct intel_iommu *iommu =3D info->iommu; + struct dmar_domain *domain; + int addr_width; + + domain =3D kzalloc(sizeof(*domain), GFP_KERNEL); + if (!domain) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&domain->devices); + INIT_LIST_HEAD(&domain->dev_pasids); + INIT_LIST_HEAD(&domain->cache_tags); + spin_lock_init(&domain->lock); + spin_lock_init(&domain->cache_lock); + xa_init(&domain->iommu_array); + + domain->nid =3D dev_to_node(dev); + domain->has_iotlb_device =3D info->ats_enabled; + domain->use_first_level =3D first_stage; + + /* calculate the address width */ + addr_width =3D agaw_to_width(iommu->agaw); + if (addr_width > cap_mgaw(iommu->cap)) + addr_width =3D cap_mgaw(iommu->cap); + domain->gaw =3D addr_width; + domain->agaw =3D iommu->agaw; + domain->max_addr =3D __DOMAIN_MAX_ADDR(addr_width); + + /* iommu memory access coherency */ + domain->iommu_coherency =3D iommu_paging_structure_coherency(iommu); + + /* pagesize bitmap */ + domain->domain.pgsize_bitmap =3D SZ_4K; + domain->iommu_superpage =3D iommu_superpage_capability(iommu, first_stage= ); + domain->domain.pgsize_bitmap |=3D domain_super_pgsize_bitmap(domain); + + /* + * IOVA aperture: First-level translation restricts the input-address + * to a canonical address (i.e., address bits 63:N have the same value + * as address bit [N-1], where N is 48-bits with 4-level paging and + * 57-bits with 5-level paging). Hence, skip bit [N-1]. + */ + domain->domain.geometry.force_aperture =3D true; + domain->domain.geometry.aperture_start =3D 0; + if (first_stage) + domain->domain.geometry.aperture_end =3D __DOMAIN_MAX_ADDR(domain->gaw -= 1); + else + domain->domain.geometry.aperture_end =3D __DOMAIN_MAX_ADDR(domain->gaw); + + /* always allocate the top pgd */ + domain->pgd =3D iommu_alloc_page_node(domain->nid, GFP_KERNEL); + if (!domain->pgd) { + kfree(domain); + return ERR_PTR(-ENOMEM); + } + domain_flush_cache(domain, domain->pgd, PAGE_SIZE); + + return domain; +} + static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) { struct dmar_domain *dmar_domain; @@ -3684,15 +3757,14 @@ intel_iommu_domain_alloc_user(struct device *dev, u= 32 flags, if (user_data || (dirty_tracking && !ssads_supported(iommu))) return ERR_PTR(-EOPNOTSUPP); =20 - /* - * domain_alloc_user op needs to fully initialize a domain before - * return, so uses iommu_domain_alloc() here for simple. - */ - domain =3D iommu_domain_alloc(dev->bus); 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d="scan'208";a="50250854" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:31 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] iommu/vt-d: Add helper to flush caches for context change Date: Tue, 2 Jul 2024 21:08:38 +0800 Message-Id: <20240702130839.108139-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This helper is used to flush the related caches following a change in a context table entry that was previously present. The VT-d specification provides guidance for such invalidations in section 6.5.3.3. This helper replaces the existing open code in the code paths where a present context entry is being torn down. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240701112317.94022-2-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.h | 4 ++ drivers/iommu/intel/iommu.c | 32 +---------- drivers/iommu/intel/pasid.c | 106 +++++++++++++++++++++++++++++------- 3 files changed, 92 insertions(+), 50 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 9a3b064126de..63eb3306c025 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -1143,6 +1143,10 @@ void cache_tag_flush_all(struct dmar_domain *domain); void cache_tag_flush_range_np(struct dmar_domain *domain, unsigned long st= art, unsigned long end); =20 +void intel_context_flush_present(struct device_domain_info *info, + struct context_entry *context, + bool affect_domains); + #ifdef CONFIG_INTEL_IOMMU_SVM void intel_svm_check(struct intel_iommu *iommu); int intel_svm_enable_prq(struct intel_iommu *iommu); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 1f0d6892a0b6..e84b0fdca107 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1359,21 +1359,6 @@ static void iommu_disable_pci_caps(struct device_dom= ain_info *info) } } =20 -static void __iommu_flush_dev_iotlb(struct device_domain_info *info, - u64 addr, unsigned int mask) -{ - u16 sid, qdep; - - if (!info || !info->ats_enabled) - return; - - sid =3D info->bus << 8 | info->devfn; - qdep =3D info->ats_qdep; - qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, - qdep, addr, mask); - quirk_extra_dev_tlb_flush(info, addr, mask, IOMMU_NO_PASID, qdep); -} - static void intel_flush_iotlb_all(struct iommu_domain *domain) { cache_tag_flush_all(to_dmar_domain(domain)); @@ -1959,7 +1944,6 @@ static void domain_context_clear_one(struct device_do= main_info *info, u8 bus, u8 { struct intel_iommu *iommu =3D info->iommu; struct context_entry *context; - u16 did_old; =20 spin_lock(&iommu->lock); context =3D iommu_context_addr(iommu, bus, devfn, 0); @@ -1968,24 +1952,10 @@ static void domain_context_clear_one(struct device_= domain_info *info, u8 bus, u8 return; } =20 - did_old =3D context_domain_id(context); - context_clear_entry(context); __iommu_flush_cache(iommu, context, sizeof(*context)); spin_unlock(&iommu->lock); - iommu->flush.flush_context(iommu, - did_old, - (((u16)bus) << 8) | devfn, - DMA_CCMD_MASK_NOBIT, - DMA_CCMD_DEVICE_INVL); - - iommu->flush.flush_iotlb(iommu, - did_old, - 0, - 0, - DMA_TLB_DSI_FLUSH); - - __iommu_flush_dev_iotlb(info, 0, MAX_AGAW_PFN_WIDTH); + intel_context_flush_present(info, context, true); } =20 static int domain_setup_first_level(struct intel_iommu *iommu, diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index aabcdf756581..d6623d2c2050 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -691,25 +691,7 @@ static void device_pasid_table_teardown(struct device = *dev, u8 bus, u8 devfn) context_clear_entry(context); __iommu_flush_cache(iommu, context, sizeof(*context)); spin_unlock(&iommu->lock); - - /* - * Cache invalidation for changes to a scalable-mode context table - * entry. - * - * Section 6.5.3.3 of the VT-d spec: - * - Device-selective context-cache invalidation; - * - Domain-selective PASID-cache invalidation to affected domains - * (can be skipped if all PASID entries were not-present); - * - Domain-selective IOTLB invalidation to affected domains; - * - Global Device-TLB invalidation to affected functions. - * - * The iommu has been parked in the blocking state. All domains have - * been detached from the device or PASID. The PASID and IOTLB caches - * have been invalidated during the domain detach path. - */ - iommu->flush.flush_context(iommu, 0, PCI_DEVID(bus, devfn), - DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL); - devtlb_invalidation_with_pasid(iommu, dev, IOMMU_NO_PASID); + intel_context_flush_present(info, context, false); } =20 static int pci_pasid_table_teardown(struct pci_dev *pdev, u16 alias, void = *data) @@ -871,3 +853,89 @@ int intel_pasid_setup_sm_context(struct device *dev) =20 return pci_for_each_dma_alias(to_pci_dev(dev), pci_pasid_table_setup, dev= ); } + +/* + * Global Device-TLB invalidation following changes in a context entry whi= ch + * was present. + */ +static void __context_flush_dev_iotlb(struct device_domain_info *info) +{ + if (!info->ats_enabled) + return; + + qi_flush_dev_iotlb(info->iommu, PCI_DEVID(info->bus, info->devfn), + info->pfsid, info->ats_qdep, 0, MAX_AGAW_PFN_WIDTH); + + /* + * There is no guarantee that the device DMA is stopped when it reaches + * here. Therefore, always attempt the extra device TLB invalidation + * quirk. The impact on performance is acceptable since this is not a + * performance-critical path. + */ + quirk_extra_dev_tlb_flush(info, 0, MAX_AGAW_PFN_WIDTH, IOMMU_NO_PASID, + info->ats_qdep); +} + +/* + * Cache invalidations after change in a context table entry that was pres= ent + * according to the Spec 6.5.3.3 (Guidance to Software for Invalidations).= If + * IOMMU is in scalable mode and all PASID table entries of the device were + * non-present, set flush_domains to false. Otherwise, true. + */ +void intel_context_flush_present(struct device_domain_info *info, + struct context_entry *context, + bool flush_domains) +{ + struct intel_iommu *iommu =3D info->iommu; + u16 did =3D context_domain_id(context); + struct pasid_entry *pte; + int i; + + /* + * Device-selective context-cache invalidation. The Domain-ID field + * of the Context-cache Invalidate Descriptor is ignored by hardware + * when operating in scalable mode. Therefore the @did value doesn't + * matter in scalable mode. + */ + iommu->flush.flush_context(iommu, did, PCI_DEVID(info->bus, info->devfn), + DMA_CCMD_MASK_NOBIT, DMA_CCMD_DEVICE_INVL); + + /* + * For legacy mode: + * - Domain-selective IOTLB invalidation + * - Global Device-TLB invalidation to all affected functions + */ + if (!sm_supported(iommu)) { + iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); + __context_flush_dev_iotlb(info); + + return; + } + + /* + * For scalable mode: + * - Domain-selective PASID-cache invalidation to affected domains + * - Domain-selective IOTLB invalidation to affected domains + * - Global Device-TLB invalidation to affected functions + */ + if (flush_domains) { + /* + * If the IOMMU is running in scalable mode and there might + * be potential PASID translations, the caller should hold + * the lock to ensure that context changes and cache flushes + * are atomic. + */ + assert_spin_locked(&iommu->lock); + for (i =3D 0; i < info->pasid_table->max_pasid; i++) { + pte =3D intel_pasid_get_entry(info->dev, i); + if (!pte || !pasid_pte_is_present(pte)) + continue; + + did =3D pasid_get_domain_id(pte); + qi_flush_pasid_cache(iommu, did, QI_PC_ALL_PASIDS, 0); + iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); + } + } + + __context_flush_dev_iotlb(info); +} --=20 2.34.1 From nobody Fri Dec 19 09:08:24 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAD2B1A38C1 for ; Tue, 2 Jul 2024 13:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719925896; cv=none; b=nun09Qi00R70lZl9Xtf6QLJhqqyyG6ep+s1OtMYM6Kr8vGvq2o/QbcLgVM6v3yPKFX96pNEPdk18ZyV4IMLkqyNF9QIdWe0B8aFOLYVdFnW8vI/WkRWiIT/980sN3t9uEVHYAxj50+S5iuD/Y3mNMyDgLh3+946ZrQh421YJssg= ARC-Message-Signature: i=1; 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d="scan'208";a="50250856" Received: from unknown (HELO allen-box.sh.intel.com) ([10.239.159.127]) by fmviesa003.fm.intel.com with ESMTP; 02 Jul 2024 06:11:33 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon Cc: Jacob Pan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] iommu/vt-d: Refactor PCI PRI enabling/disabling callbacks Date: Tue, 2 Jul 2024 21:08:39 +0800 Message-Id: <20240702130839.108139-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702130839.108139-1-baolu.lu@linux.intel.com> References: <20240702130839.108139-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 0095bf83554f8 ("iommu: Improve iopf_queue_remove_device()") specified the flow for disabling the PRI on a device. Refactor the PRI callbacks in the intel iommu driver to better manage PRI enabling and disabling and align it with the device queue interfaces in the iommu core. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20240701112317.94022-3-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.h | 9 ++++++ drivers/iommu/intel/iommu.c | 57 +++++++++++++++++++++++++++++++++---- drivers/iommu/intel/pasid.c | 2 -- 3 files changed, 61 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 63eb3306c025..b67c14da1240 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -1045,6 +1045,15 @@ static inline void context_set_sm_pre(struct context= _entry *context) context->lo |=3D BIT_ULL(4); } =20 +/* + * Clear the PRE(Page Request Enable) field of a scalable mode context + * entry. + */ +static inline void context_clear_sm_pre(struct context_entry *context) +{ + context->lo &=3D ~BIT_ULL(4); +} + /* Returns a number of VTD pages, but aligned to MM page size */ static inline unsigned long aligned_nrpages(unsigned long host_addr, size_= t size) { diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index e84b0fdca107..523407f6f6b2 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4244,6 +4244,37 @@ static int intel_iommu_enable_sva(struct device *dev) return 0; } =20 +static int context_flip_pri(struct device_domain_info *info, bool enable) +{ + struct intel_iommu *iommu =3D info->iommu; + u8 bus =3D info->bus, devfn =3D info->devfn; + struct context_entry *context; + + spin_lock(&iommu->lock); + if (context_copied(iommu, bus, devfn)) { + spin_unlock(&iommu->lock); + return -EINVAL; + } + + context =3D iommu_context_addr(iommu, bus, devfn, false); + if (!context || !context_present(context)) { + spin_unlock(&iommu->lock); + return -ENODEV; + } + + if (enable) + context_set_sm_pre(context); + else + context_clear_sm_pre(context); + + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(context, sizeof(*context)); + intel_context_flush_present(info, context, true); + spin_unlock(&iommu->lock); + + return 0; +} + static int intel_iommu_enable_iopf(struct device *dev) { struct pci_dev *pdev =3D dev_is_pci(dev) ? to_pci_dev(dev) : NULL; @@ -4273,15 +4304,23 @@ static int intel_iommu_enable_iopf(struct device *d= ev) if (ret) return ret; =20 + ret =3D context_flip_pri(info, true); + if (ret) + goto err_remove_device; + ret =3D pci_enable_pri(pdev, PRQ_DEPTH); - if (ret) { - iopf_queue_remove_device(iommu->iopf_queue, dev); - return ret; - } + if (ret) + goto err_clear_pri; =20 info->pri_enabled =3D 1; =20 return 0; +err_clear_pri: + context_flip_pri(info, false); +err_remove_device: + iopf_queue_remove_device(iommu->iopf_queue, dev); + + return ret; } =20 static int intel_iommu_disable_iopf(struct device *dev) @@ -4292,6 +4331,15 @@ static int intel_iommu_disable_iopf(struct device *d= ev) if (!info->pri_enabled) return -EINVAL; =20 + /* Disable new PRI reception: */ + context_flip_pri(info, false); + + /* + * Remove device from fault queue and acknowledge all outstanding + * PRQs to the device: + */ + iopf_queue_remove_device(iommu->iopf_queue, dev); + /* * PCIe spec states that by clearing PRI enable bit, the Page * Request Interface will not issue new page requests, but has @@ -4302,7 +4350,6 @@ static int intel_iommu_disable_iopf(struct device *de= v) */ pci_disable_pri(to_pci_dev(dev)); info->pri_enabled =3D 0; - iopf_queue_remove_device(iommu->iopf_queue, dev); =20 return 0; } diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index d6623d2c2050..9a7b5668c723 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -749,8 +749,6 @@ static int context_entry_set_pasid_table(struct context= _entry *context, =20 if (info->ats_supported) context_set_sm_dte(context); - if (info->pri_supported) - context_set_sm_pre(context); if (info->pasid_supported) context_set_pasid(context); =20 --=20 2.34.1