From nobody Fri Dec 19 12:14:56 2025 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE32813BADF for ; Wed, 3 Jul 2024 05:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719986237; cv=none; b=jE/7HUgcZTEt+lJwDOm3lpafsRQaCPffAOCHIme0y8rtDY7CpQNU8GDPDOULhbzaqsBlwRtqL6gf/oAdmsljfJCYwhzq1eG4M7z6KOipQ7jrfYVgc3ANBCltRgRaM2/oeGvGXvucLWVg7E4JBr97vDO4WyyWw4VMpRBd3ZfaLpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719986237; c=relaxed/simple; bh=uWAEAl3/1U0yZtNYeouADyVxBW97grMaJDDcsjEX0/s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VEULEP6Rkh4OcTl8qY5IYAYaypquXIGCmm0Fy2ltPxnDj04DGx6+L55B9hSi7vRk/RQmCshgj0GvtDDYwsXGQlIL7VLeloYv3YtxQTEoSEvO+vDhJCzGvwVkObfnzYddzY8QD6RVdkk/9yzR78XQQgNABXbeB6ZLXXE/gFN+aa8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=J3uTA8m5; arc=none smtp.client-ip=209.85.167.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="J3uTA8m5" Received: by mail-oi1-f174.google.com with SMTP id 5614622812f47-3d853e31de8so157562b6e.2 for ; Tue, 02 Jul 2024 22:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1719986234; x=1720591034; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=L2IjXx4NcaEixIgSix5AFPnT9uYJdWPHkZjt+gDuKDw=; b=J3uTA8m592i7V9QLHEpJxAw6knybb4wbMqnS/0bxtwSssMfJPY4SnvIUnoBPqZxYAy MkzaWR6VqcNfZiWEkefno/O8ql+Rea3seUJkubyWfJarZNPGNU0No+peBkHuINoo0utE VCY4Jb463B7UavK2On2yhJGRk5QZoAVAnPeVeDJBHL4wlhFvKqvZHDq62qgqvuy7T1mI Rdijrqur0pUOWmwDdsDo3AfKYil4AmuuaeQu+cnuY9pTt1ivpIzaK3g4vWyzOIoc7AbP MhWwkoJCdx/Lt4P52wn7Gny9DvxoLZVysIkrlIj9I+SGRIqUkhgF4/P10cAg8yLEgoNp swvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719986234; x=1720591034; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L2IjXx4NcaEixIgSix5AFPnT9uYJdWPHkZjt+gDuKDw=; b=p1Lk7JZQ3Tf5EZz00EH0PM4BTvYeyC6+lfyGqzOcebOJy3kbNuYBEuEsfWjmE/S9jz gGcCbmAUVAJaXDaniFOkudLD5FR1BuIH+JTjs1VTUxtEWng14BFie94X6TsQDUpBnmh9 CgCxMytiDJXSkjxydBqh8Vqq++6F2i4hhtozm2Zt0bexbg9q5SNK2gNy+y5XJPlTSbgv THKHmCyMzjy7+ULIfAHztaHLyMZ9PVp1KNvmIoXFZFd/S/jUxwyngixjfXF16ro+19rO bdLIRh+BSCjvXgvkFdJMg0Ao+R8Cu5qpCgJ0Rt2nHGqhS8acg7YDgcOMMl43AlF6yBmp hJ6w== X-Forwarded-Encrypted: i=1; AJvYcCUYOwMIXmhYrFppg8Avd9S44J+NXjBfvqOG700R6AhEU7FrUwYyoZiXC7KhJubbaIo0WLfJ6aLSO6fCVWQon/X3V/d9S0ETcih/s2kM X-Gm-Message-State: AOJu0YyHh4T0ePVz3WtomJX+rSn04M3zt+I9JBcXqsEpT8FCGjjQ6MBL ljv0ckPEnkWhIi0c7MRwtPAkd8rnLa+KNUqfKsYbpAT68RbdKMzZvSV3dQE0agA= X-Google-Smtp-Source: AGHT+IHIWQJO7LL7TOZj1S1Gbp8rPdlQ2gPt5G5BK9YQzlgmUdFqBLARYC/c6Um6lU7tJQLKnNG8ww== X-Received: by 2002:a05:6808:2204:b0:3d6:2cde:e930 with SMTP id 5614622812f47-3d6b36bf6f0mr13487899b6e.23.1719986233852; Tue, 02 Jul 2024 22:57:13 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70804a89fc9sm9514103b3a.212.2024.07.02.22.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 22:57:13 -0700 (PDT) From: Charlie Jenkins Date: Tue, 02 Jul 2024 22:56:29 -0700 Subject: [PATCH v4 09/13] riscv: vector: Support xtheadvector save/restore Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240702-xtheadvector-v4-9-2bad6820db11@rivosinc.com> References: <20240702-xtheadvector-v4-0-2bad6820db11@rivosinc.com> In-Reply-To: <20240702-xtheadvector-v4-0-2bad6820db11@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins , Conor Dooley X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719986213; l=18179; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=uWAEAl3/1U0yZtNYeouADyVxBW97grMaJDDcsjEX0/s=; b=fTf3FGfMPokaJWkdPxpNiHQE1djtg1XsNQIhUix1prTIynSXdJVVrGKKZWfQnxWRGL73ULLuK RukKVgc/QiqCVI5M48OmyhPkpP8KYDCjcUWbFwaRLSrX2SGwq/2PpuP X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Use alternatives to add support for xtheadvector vector save/restore routines. Signed-off-by: Charlie Jenkins Reviewed-by: Conor Dooley --- arch/riscv/include/asm/csr.h | 6 + arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 224 +++++++++++++++++++++++++----= ---- arch/riscv/kernel/cpufeature.c | 2 +- arch/riscv/kernel/kernel_mode_vector.c | 8 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +- arch/riscv/kernel/vector.c | 13 +- 8 files changed, 197 insertions(+), 68 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index c0a60c4ed911..b4b3fcb1d142 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -30,6 +30,12 @@ #define SR_VS_CLEAN _AC(0x00000400, UL) #define SR_VS_DIRTY _AC(0x00000600, UL) =20 +#define SR_VS_THEAD _AC(0x01800000, UL) /* xtheadvector Status */ +#define SR_VS_OFF_THEAD _AC(0x00000000, UL) +#define SR_VS_INITIAL_THEAD _AC(0x00800000, UL) +#define SR_VS_CLEAN_THEAD _AC(0x01000000, UL) +#define SR_VS_DIRTY_THEAD _AC(0x01800000, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 7594df37cc9f..f9cbebe372b8 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -99,7 +99,7 @@ do { \ __set_prev_cpu(__prev->thread); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index 731dcd0ed4de..0425a0d609f9 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,27 @@ #include #include #include +#include +#include +#include + +#define __riscv_v_vstate_or(_val, TYPE) ({ \ + typeof(_val) _res =3D _val; \ + if (has_xtheadvector()) \ + _res =3D (_res & ~SR_VS_THEAD) | SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D (_res & ~SR_VS) | SR_VS_##TYPE; \ + _res; \ +}) + +#define __riscv_v_vstate_check(_val, TYPE) ({ \ + bool _res; \ + if (has_xtheadvector()) \ + _res =3D ((_val) & SR_VS_THEAD) =3D=3D SR_VS_##TYPE##_THEAD; \ + else \ + _res =3D ((_val) & SR_VS) =3D=3D SR_VS_##TYPE; \ + _res; \ +}) =20 extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -40,39 +61,62 @@ static __always_inline bool has_vector(void) return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); } =20 +static __always_inline bool has_xtheadvector_no_alternatives(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_isa_vendor_extension_available(THEAD_VENDOR_ID, XTHEADVECTO= R); + else + return false; +} + +static __always_inline bool has_xtheadvector(void) +{ + if (IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR)) + return riscv_has_vendor_extension_unlikely(THEAD_VENDOR_ID, + RISCV_ISA_VENDOR_EXT_XTHEADVECTOR); + else + return false; +} + static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_CLEAN; + regs->status =3D __riscv_v_vstate_or(regs->status, CLEAN); } =20 static inline void __riscv_v_vstate_dirty(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_DIRTY; + regs->status =3D __riscv_v_vstate_or(regs->status, DIRTY); } =20 static inline void riscv_v_vstate_off(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_OFF; + regs->status =3D __riscv_v_vstate_or(regs->status, OFF); } =20 static inline void riscv_v_vstate_on(struct pt_regs *regs) { - regs->status =3D (regs->status & ~SR_VS) | SR_VS_INITIAL; + regs->status =3D __riscv_v_vstate_or(regs->status, INITIAL); } =20 static inline bool riscv_v_vstate_query(struct pt_regs *regs) { - return (regs->status & SR_VS) !=3D 0; + return !__riscv_v_vstate_check(regs->status, OFF); } =20 static __always_inline void riscv_v_enable(void) { - csr_set(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_set(CSR_SSTATUS, SR_VS_THEAD); + else + csr_set(CSR_SSTATUS, SR_VS); } =20 static __always_inline void riscv_v_disable(void) { - csr_clear(CSR_SSTATUS, SR_VS); + if (has_xtheadvector()) + csr_clear(CSR_SSTATUS, SR_VS_THEAD); + else + csr_clear(CSR_SSTATUS, SR_VS); } =20 static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *= dest) @@ -81,10 +125,36 @@ static __always_inline void __vstate_csr_save(struct _= _riscv_v_ext_state *dest) "csrr %0, " __stringify(CSR_VSTART) "\n\t" "csrr %1, " __stringify(CSR_VTYPE) "\n\t" "csrr %2, " __stringify(CSR_VL) "\n\t" - "csrr %3, " __stringify(CSR_VCSR) "\n\t" - "csrr %4, " __stringify(CSR_VLENB) "\n\t" : "=3Dr" (dest->vstart), "=3Dr" (dest->vtype), "=3Dr" (dest->vl), - "=3Dr" (dest->vcsr), "=3Dr" (dest->vlenb) : :); + "=3Dr" (dest->vcsr) : :); + + if (has_xtheadvector()) { + unsigned long status; + + /* + * CSR_VCSR is defined as + * [2:1] - vxrm[1:0] + * [0] - vxsat + * The earlier vector spec implemented by T-Head uses separate + * registers for the same bit-elements, so just combine those + * into the existing output field. + * + * Additionally T-Head cores need FS to be enabled when accessing + * the VXRM and VXSAT CSRs, otherwise ending in illegal instructions. + * Though the cores do not implement the VXRM and VXSAT fields in the + * FCSR CSR that vector-0.7.1 specifies. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + dest->vcsr =3D csr_read(CSR_VXSAT) | csr_read(CSR_VXRM) << CSR_VXRM_SHIF= T; + + dest->vlenb =3D riscv_v_vsize / 32; + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + dest->vcsr =3D csr_read(CSR_VCSR); + dest->vlenb =3D csr_read(CSR_VLENB); + } } =20 static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_stat= e *src) @@ -95,9 +165,25 @@ static __always_inline void __vstate_csr_restore(struct= __riscv_v_ext_state *src "vsetvl x0, %2, %1\n\t" ".option pop\n\t" "csrw " __stringify(CSR_VSTART) ", %0\n\t" - "csrw " __stringify(CSR_VCSR) ", %3\n\t" - : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), - "r" (src->vcsr) :); + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl)); + + if (has_xtheadvector()) { + unsigned long status =3D csr_read(CSR_SSTATUS); + + /* + * Similar to __vstate_csr_save above, restore values for the + * separate VXRM and VXSAT CSRs from the vcsr variable. + */ + status =3D csr_read_set(CSR_STATUS, SR_FS_DIRTY); + + csr_write(CSR_VXRM, (src->vcsr >> CSR_VXRM_SHIFT) & CSR_VXRM_MASK); + csr_write(CSR_VXSAT, src->vcsr & CSR_VXSAT_MASK); + + if ((status & SR_FS) !=3D SR_FS_DIRTY) + csr_write(CSR_STATUS, status); + } else { + csr_write(CSR_VCSR, src->vcsr); + } } =20 static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_= to, @@ -107,19 +193,33 @@ static inline void __riscv_v_vstate_save(struct __ris= cv_v_ext_state *save_to, =20 riscv_v_enable(); __vstate_csr_save(save_to); - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vse8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vse8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VSB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } riscv_v_disable(); } =20 @@ -129,55 +229,77 @@ static inline void __riscv_v_vstate_restore(struct __= riscv_v_ext_state *restore_ unsigned long vl; =20 riscv_v_enable(); - asm volatile ( - ".option push\n\t" - ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" - "vle8.v v0, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v8, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v16, (%1)\n\t" - "add %1, %1, %0\n\t" - "vle8.v v24, (%1)\n\t" - ".option pop\n\t" - : "=3D&r" (vl) : "r" (datap) : "memory"); + if (has_xtheadvector()) { + asm volatile ( + "mv t0, %0\n\t" + THEAD_VSETVLI_T4X0E8M8D1 + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + "add t0, t0, t4\n\t" + THEAD_VLB_V_V0T0 + : : "r" (datap) : "memory", "t0", "t4"); + } else { + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=3D&r" (vl) : "r" (datap) : "memory"); + } __vstate_csr_restore(restore_from); riscv_v_disable(); } =20 static inline void __riscv_v_vstate_discard(void) { - unsigned long vl, vtype_inval =3D 1UL << (BITS_PER_LONG - 1); + unsigned long vtype_inval =3D 1UL << (BITS_PER_LONG - 1); =20 riscv_v_enable(); + if (has_xtheadvector()) + asm volatile (THEAD_VSETVLI_X0X0E8M8D1); + else + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e8, m8, ta, ma\n\t" + ".option pop\n\t"); + asm volatile ( ".option push\n\t" ".option arch, +v\n\t" - "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" "vmv.v.i v16, -1\n\t" "vmv.v.i v24, -1\n\t" - "vsetvl %0, x0, %1\n\t" + "vsetvl x0, x0, %0\n\t" ".option pop\n\t" - : "=3D&r" (vl) : "r" (vtype_inval) : "memory"); + : : "r" (vtype_inval)); + riscv_v_disable(); } =20 static inline void riscv_v_vstate_discard(struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_OFF) - return; - - __riscv_v_vstate_discard(); - __riscv_v_vstate_dirty(regs); + if (riscv_v_vstate_query(regs)) { + __riscv_v_vstate_discard(); + __riscv_v_vstate_dirty(regs); + } } =20 static inline void riscv_v_vstate_save(struct __riscv_v_ext_state *vstate, struct pt_regs *regs) { - if ((regs->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(regs->status, DIRTY)) { __riscv_v_vstate_save(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -186,7 +308,7 @@ static inline void riscv_v_vstate_save(struct __riscv_v= _ext_state *vstate, static inline void riscv_v_vstate_restore(struct __riscv_v_ext_state *vsta= te, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { __riscv_v_vstate_restore(vstate, vstate->datap); __riscv_v_vstate_clean(regs); } @@ -195,7 +317,7 @@ static inline void riscv_v_vstate_restore(struct __risc= v_v_ext_state *vstate, static inline void riscv_v_vstate_set_restore(struct task_struct *task, struct pt_regs *regs) { - if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + if (riscv_v_vstate_query(regs)) { set_tsk_thread_flag(task, TIF_RISCV_V_DEFER_RESTORE); riscv_v_vstate_on(regs); } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 077be4ab1f9a..180f7eae9086 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -789,7 +789,7 @@ void __init riscv_fill_hwcap(void) elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (elf_hwcap & COMPAT_HWCAP_ISA_V || has_xtheadvector_no_alternatives())= { riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c index 6afe80c7f03a..99972a48e86b 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -143,7 +143,7 @@ static int riscv_v_start_kernel_context(bool *is_nested) =20 /* Transfer the ownership of V from user to kernel, then save */ riscv_v_start(RISCV_PREEMPT_V | RISCV_PREEMPT_V_DIRTY); - if ((task_pt_regs(current)->status & SR_VS) =3D=3D SR_VS_DIRTY) { + if (__riscv_v_vstate_check(task_pt_regs(current)->status, DIRTY)) { uvstate =3D ¤t->thread.vstate; __riscv_v_vstate_save(uvstate, uvstate->datap); } @@ -160,7 +160,7 @@ asmlinkage void riscv_v_context_nesting_start(struct pt= _regs *regs) return; =20 depth =3D riscv_v_ctx_get_depth(); - if (depth =3D=3D 0 && (regs->status & SR_VS) =3D=3D SR_VS_DIRTY) + if (depth =3D=3D 0 && __riscv_v_vstate_check(regs->status, DIRTY)) riscv_preempt_v_set_dirty(); =20 riscv_v_ctx_depth_inc(); @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested =3D false; =20 - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!(has_vector() || has_xtheadvector()))) return; =20 riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..191023decd16 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -176,7 +176,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_free(tsk); } =20 @@ -222,7 +222,7 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.s[0] =3D 0; } p->thread.riscv_v_flags =3D 0; - if (has_vector()) + if (has_vector() || has_xtheadvector()) riscv_v_thread_alloc(p); p->thread.ra =3D (unsigned long)ret_from_fork; p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 5a2edd7f027e..1d5e4b3ca9e1 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -189,7 +189,7 @@ static long restore_sigcontext(struct pt_regs *regs, =20 return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!(has_vector() || has_xtheadvector()) || !riscv_v_vstate_query(regs= ) || size !=3D riscv_v_sc_size) return -EINVAL; =20 @@ -211,7 +211,7 @@ static size_t get_rt_frame_size(bool cal_all) =20 frame_size =3D sizeof(*frame); =20 - if (has_vector()) { + if (has_vector() || has_xtheadvector()) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size +=3D riscv_v_sc_size; } @@ -284,7 +284,7 @@ static long setup_sigcontext(struct rt_sigframe __user = *frame, if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs)) err |=3D save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |=3D __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 3ba2f2432483..83126995f61a 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -63,7 +63,7 @@ int riscv_v_setup_vsize(void) =20 void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 riscv_v_user_cachep =3D kmem_cache_create_usercopy("riscv_vector_ctx", @@ -184,7 +184,8 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 insn =3D (u32)regs->badaddr; =20 /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V) && + !(has_xtheadvector() && riscv_v_vstate_ctrl_user_allowed())) return false; =20 /* If V has been enabled then it is not the first-use trap */ @@ -223,7 +224,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return; =20 next =3D riscv_v_ctrl_get_next(tsk); @@ -245,7 +246,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) =20 long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -256,7 +257,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; =20 - if (!has_vector()) + if (!(has_vector() || has_xtheadvector())) return -EINVAL; =20 if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -306,7 +307,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = =3D { =20 static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector() || has_xtheadvector()) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; --=20 2.44.0