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Mon, 1 Jul 2024 04:35:13 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7733220040; Mon, 1 Jul 2024 04:35:11 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 854452004D; Mon, 1 Jul 2024 04:35:08 +0000 (GMT) Received: from localhost.localdomain (unknown [9.43.21.126]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 1 Jul 2024 04:35:08 +0000 (GMT) From: Athira Rajeev To: acme@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, irogers@google.com, namhyung@kernel.org, segher@kernel.crashing.org, christophe.leroy@csgroup.eu Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, akanksha@linux.ibm.com, maddy@linux.ibm.com, atrajeev@linux.vnet.ibm.com, kjain@linux.ibm.com, disgoel@linux.vnet.ibm.com Subject: [PATCH V5 11/17] tools/perf: Update instruction tracking for powerpc Date: Mon, 1 Jul 2024 10:04:24 +0530 Message-Id: <20240701043430.66666-12-atrajeev@linux.vnet.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20240701043430.66666-1-atrajeev@linux.vnet.ibm.com> References: <20240701043430.66666-1-atrajeev@linux.vnet.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: MnFtEHmxQPmRV29oanSqzQpStbEYHdlO X-Proofpoint-GUID: 1ait4Af32JTzkq7w6L2Wrh-Xz4phVuKL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-01_03,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 spamscore=0 mlxlogscore=999 malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407010030 Content-Type: text/plain; charset="utf-8" Add instruction tracking function "update_insn_state_powerpc" for powerpc. Example sequence in powerpc: ld r10,264(r3) mr r31,r3 < ld r9,312(r31) Consider ithe sample is pointing to: "ld r9,312(r31)". Here the memory reference is hit at "312(r31)" where 312 is the offset and r31 is the source register. Previous instruction sequence shows that register state of r3 is moved to r31. So to identify the data type for r31 access, the previous instruction ("mr") needs to be tracked and the state type entry has to be updated. Current instruction tracking support in perf tools infrastructure is specific to x86. Patch adds this support for powerpc as well. Signed-off-by: Athira Rajeev --- .../perf/arch/powerpc/annotate/instructions.c | 59 +++++++++++++++++++ tools/perf/util/annotate-data.c | 9 ++- tools/perf/util/disasm.c | 3 + 3 files changed, 70 insertions(+), 1 deletion(-) diff --git a/tools/perf/arch/powerpc/annotate/instructions.c b/tools/perf/a= rch/powerpc/annotate/instructions.c index aa25a336d8d0..7f2b09000860 100644 --- a/tools/perf/arch/powerpc/annotate/instructions.c +++ b/tools/perf/arch/powerpc/annotate/instructions.c @@ -231,6 +231,65 @@ static struct ins_ops *check_ppc_insn(u32 raw_insn) return NULL; } =20 +/* + * Instruction tracking function to track register state moves. + * Example sequence: + * ld r10,264(r3) + * mr r31,r3 + * < + * ld r9,312(r31) + * + * Previous instruction sequence shows that register state of r3 + * is moved to r31. update_insn_state_powerpc tracks these state + * changes + */ +#ifdef HAVE_DWARF_SUPPORT +static void update_insn_state_powerpc(struct type_state *state, + struct data_loc_info *dloc, Dwarf_Die * cu_die __maybe_unused, + struct disasm_line *dl) +{ + struct annotated_insn_loc loc; + struct annotated_op_loc *src =3D &loc.ops[INSN_OP_SOURCE]; + struct annotated_op_loc *dst =3D &loc.ops[INSN_OP_TARGET]; + struct type_state_reg *tsr; + u32 insn_offset =3D dl->al.offset; + + if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0) + return; + + /* + * Value 444 for bits 21:30 is for "mr" + * instruction. "mr" is extended OR. So set the + * source and destination reg correctly + */ + if (PPC_21_30(dl->raw.raw_insn) =3D=3D 444) { + int src_reg =3D src->reg1; + + src->reg1 =3D dst->reg1; + dst->reg1 =3D src_reg; + } + + if (!has_reg_type(state, dst->reg1, dloc->arch)) + return; + + tsr =3D &state->regs[dst->reg1]; + + if (!has_reg_type(state, src->reg1, dloc->arch) || + !state->regs[src->reg1].ok) { + tsr->ok =3D false; + return; + } + + tsr->type =3D state->regs[src->reg1].type; + tsr->kind =3D state->regs[src->reg1].kind; + tsr->ok =3D true; + + pr_debug_dtp("mov [%x] reg%d -> reg%d", + insn_offset, src->reg1, dst->reg1); + pr_debug_type_name(&tsr->type, tsr->kind); +} +#endif /* HAVE_DWARF_SUPPORT */ + static int powerpc__annotate_init(struct arch *arch, char *cpuid __maybe_u= nused) { if (!arch->initialized) { diff --git a/tools/perf/util/annotate-data.c b/tools/perf/util/annotate-dat= a.c index fac9d3cdd318..721235e1e6cf 100644 --- a/tools/perf/util/annotate-data.c +++ b/tools/perf/util/annotate-data.c @@ -1085,6 +1085,13 @@ static int find_data_type_insn(struct data_loc_info = *dloc, return ret; } =20 +static int arch_supports_insn_tracking(struct data_loc_info *dloc) +{ + if ((arch__is(dloc->arch, "x86")) || (arch__is(dloc->arch, "powerpc"))) + return 1; + return 0; +} + /* * Construct a list of basic blocks for each scope with variables and try = to find * the data type by updating a type state table through instructions. @@ -1099,7 +1106,7 @@ static int find_data_type_block(struct data_loc_info = *dloc, int ret =3D -1; =20 /* TODO: other architecture support */ - if (!arch__is(dloc->arch, "x86")) + if (!arch_supports_insn_tracking(dloc)) return -1; =20 prev_dst_ip =3D dst_ip =3D dloc->ip; diff --git a/tools/perf/util/disasm.c b/tools/perf/util/disasm.c index 03227112ccfb..9da5bc893c66 100644 --- a/tools/perf/util/disasm.c +++ b/tools/perf/util/disasm.c @@ -157,6 +157,9 @@ static struct arch architectures[] =3D { { .name =3D "powerpc", .init =3D powerpc__annotate_init, +#ifdef HAVE_DWARF_SUPPORT + .update_insn_state =3D update_insn_state_powerpc, +#endif }, { .name =3D "riscv64", --=20 2.43.0