From nobody Wed Dec 17 15:31:43 2025 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19DC67A715 for ; Fri, 28 Jun 2024 20:56:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608165; cv=none; b=Qfxx7xV230UktEjSp8B84hpdJ5j584VGIHM0XUniARblAEVbbB8STMotoLR4XmGJV7QLD4eJ4ortz2nTzm939ZviN30JTKPSnv0dlitkW8bCbo5Lniw4u9ebWIJvZCnAhqLzSSYGl0t0amv7bAiJ3XbOtktxXp3eBP3wnJL3GB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608165; c=relaxed/simple; bh=7vSs2AxTZFZFcue+3cJMHw0ES5vsxSJk9Wv60ZDzZKM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hxhlmX6mIeW2tmd8xv+r1+LW3WVmUAXi4heJ/xxwtEXR0YAHA5TatU0SwK6NqbfHAdjXbWDLNeM2XGUn2QXAcV/jKIFng2j1garwBflhGDP+RJIINCgRhJ6sW1lMADmpCFwilpqF+wBBApfv3sPYyXIEnAHCR/28ajMkXxyrxQ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=J8Dot2eR; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="J8Dot2eR" X-Envelope-To: radhey.shyam.pandey@amd.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1719608162; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VhvHqCXuudFTNwDuA4VjIUrafDHyK4yeQF5CqDZlZYo=; b=J8Dot2eRL2Hf3kwUWOGKMagrRlX7BmnSpUlyWTekGmsAkFY3Nj8fnj/ynx7S15N9iDegVI EPTHfmDTlq2yAKQmwTePrfa0Hex4kzioby+753sqUZmd9IJ+XIdXQvb6fOAZUVJZQMZaSK mueQ6zkItnOi+haWU7fldEg5aqsDvto= X-Envelope-To: laurent.pinchart@ideasonboard.com X-Envelope-To: linux-phy@lists.infradead.org X-Envelope-To: vkoul@kernel.org X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: kishon@kernel.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Radhey Shyam Pandey , Laurent Pinchart , linux-phy@lists.infradead.org Cc: Vinod Koul , linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Michal Simek , Sean Anderson Subject: [PATCH v3 1/5] phy: zynqmp: Enable reference clock correctly Date: Fri, 28 Jun 2024 16:55:36 -0400 Message-Id: <20240628205540.3098010-2-sean.anderson@linux.dev> In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev> References: <20240628205540.3098010-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for po= wer-save") Signed-off-by: Sean Anderson --- Changes in v3: - Remove inapplicable comments Changes in v2: - New drivers/phy/xilinx/phy-zynqmp.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqm= p.c index dc8319bda43d..f2bff7f25f05 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -80,7 +80,8 @@ =20 /* Reference clock selection parameters */ #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) -#define L0_REF_CLK_SEL_MASK 0x8f +#define L0_REF_CLK_LCL_SEL BIT(7) +#define L0_REF_CLK_SEL_MASK 0x9f =20 /* Calibration digital logic parameters */ #define L3_TM_CALIB_DIG19 0xec4c @@ -349,11 +350,12 @@ static void xpsgtr_configure_pll(struct xpsgtr_phy *g= tr_phy) PLL_FREQ_MASK, ssc->pll_ref_clk); =20 /* Enable lane clock sharing, if required */ - if (gtr_phy->refclk !=3D gtr_phy->lane) { - /* Lane3 Ref Clock Selection Register */ + if (gtr_phy->refclk =3D=3D gtr_phy->lane) + xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), + L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL); + else xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); - } =20 /* SSC step size [7:0] */ xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, @@ -573,7 +575,7 @@ static int xpsgtr_phy_init(struct phy *phy) mutex_lock(>r_dev->gtr_mutex); =20 /* Configure and enable the clock when peripheral phy_init call */ - if (clk_prepare_enable(gtr_dev->clk[gtr_phy->lane])) + if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk])) goto out; =20 /* Skip initialization if not required. */ @@ -625,7 +627,7 @@ static int xpsgtr_phy_exit(struct phy *phy) gtr_phy->skip_phy_init =3D false; =20 /* Ensure that disable clock only, which configure for lane */ - clk_disable_unprepare(gtr_dev->clk[gtr_phy->lane]); + clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]); =20 return 0; } --=20 2.35.1.1320.gc452695387.dirty From nobody Wed Dec 17 15:31:43 2025 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA2557E57F for ; Fri, 28 Jun 2024 20:56:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608167; cv=none; b=Nh5upYQLehzB1FCBL+lofo7oVGqsNVbs0ruwaYUna/9uaREKHAi36631H+Kqns0krYqciimZpKPghM50rti32+6GhkG0Gsj8TTT8YiJQHzmYzj9idNfAsuC8if+WgNFrlzcXlosv0JYVJlANXm8JjyJHN8r+Pxy67HQqRmFwPVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608167; c=relaxed/simple; bh=LEy8D65DVWTPCerMbid4+wSUvGQMf7XkjZr3fbp8YLQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JyHaN34LlxIuhRwhGHCt0GmmQCJAdECm06+WUHqh26kbE4O4pWttjrVqFyGsjJaNE2KxzleLC83aat6TfwwwQqU8UO6RtAnhAsr+MLS/IZ+gpoq7FnNcwMv+3UQ6uDn2Y351kLczXJghABuWeEOXi75fc7V72ftpiZUPS1ts49A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=ujZBDOPl; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="ujZBDOPl" X-Envelope-To: radhey.shyam.pandey@amd.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1719608164; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZnUj+c1q39DBVPLXCwh57WqrokI529fLR0JHteKNTjs=; b=ujZBDOPlEYYWjfjBVUZTqLsKPKsW2M3UL31ET/f89ghCN9urm569SXA1G6tSaKAPQRx0vE 9nlyCxTJk6PCYKdQ61DdV2Jit1r8Qqjt+L8DM5PYIw53/ecgmHSxUHqhEE3K5N5RGWm2MB aGdeYVxlzvkzLlGG70SvWHS8NxDAkHo= X-Envelope-To: laurent.pinchart@ideasonboard.com X-Envelope-To: linux-phy@lists.infradead.org X-Envelope-To: vkoul@kernel.org X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: kishon@kernel.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Radhey Shyam Pandey , Laurent Pinchart , linux-phy@lists.infradead.org Cc: Vinod Koul , linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Michal Simek , Sean Anderson Subject: [PATCH v3 2/5] phy: zynqmp: Store instance instead of type Date: Fri, 28 Jun 2024 16:55:37 -0400 Message-Id: <20240628205540.3098010-3-sean.anderson@linux.dev> In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev> References: <20240628205540.3098010-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson --- (no changes since v2) Changes in v2: - Expand the icm_matrix comment drivers/phy/xilinx/phy-zynqmp.c | 115 +++++++++----------------------- 1 file changed, 31 insertions(+), 84 deletions(-) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqm= p.c index f2bff7f25f05..a1cf32024efb 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -147,22 +147,6 @@ /* Total number of controllers */ #define CONTROLLERS_PER_LANE 5 =20 -/* Protocol Type parameters */ -#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */ -#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */ -#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */ -#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */ -#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */ -#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */ -#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */ -#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */ -#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */ -#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */ -#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */ -#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */ -#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */ -#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */ - /* Timeout values */ #define TIMEOUT_US 1000 =20 @@ -185,7 +169,8 @@ struct xpsgtr_ssc { /** * struct xpsgtr_phy - representation of a lane * @phy: pointer to the kernel PHY device - * @type: controller which uses this lane + * @instance: instance of the protocol type (such as the lane within a + * protocol, or the USB/Ethernet controller) * @lane: lane number * @protocol: protocol in which the lane operates * @skip_phy_init: skip phy_init() if true @@ -194,7 +179,7 @@ struct xpsgtr_ssc { */ struct xpsgtr_phy { struct phy *phy; - u8 type; + u8 instance; u8 lane; u8 protocol; bool skip_phy_init; @@ -331,8 +316,8 @@ static int xpsgtr_wait_pll_lock(struct phy *phy) =20 if (ret =3D=3D -ETIMEDOUT) dev_err(gtr_dev->dev, - "lane %u (type %u, protocol %u): PLL lock timeout\n", - gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); + "lane %u (protocol %u, instance %u): PLL lock timeout\n", + gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance); =20 return ret; } @@ -645,8 +630,7 @@ static int xpsgtr_phy_power_on(struct phy *phy) * cumulating waits for both lanes. The user is expected to initialize * lane 0 last. */ - if (gtr_phy->protocol !=3D ICM_PROTOCOL_DP || - gtr_phy->type =3D=3D XPSGTR_TYPE_DP_0) + if (gtr_phy->protocol !=3D ICM_PROTOCOL_DP || !gtr_phy->instance) ret =3D xpsgtr_wait_pll_lock(phy); =20 return ret; @@ -676,73 +660,33 @@ static const struct phy_ops xpsgtr_phyops =3D { * OF Xlate Support */ =20 -/* Set the lane type and protocol based on the PHY type and instance numbe= r. */ +/* Set the lane protocol and instance based on the PHY type and instance n= umber. */ static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type, unsigned int phy_instance) { unsigned int num_phy_types; - const int *phy_types; =20 switch (phy_type) { - case PHY_TYPE_SATA: { - static const int types[] =3D { - XPSGTR_TYPE_SATA_0, - XPSGTR_TYPE_SATA_1, - }; - - phy_types =3D types; - num_phy_types =3D ARRAY_SIZE(types); + case PHY_TYPE_SATA: + num_phy_types =3D 2; gtr_phy->protocol =3D ICM_PROTOCOL_SATA; break; - } - case PHY_TYPE_USB3: { - static const int types[] =3D { - XPSGTR_TYPE_USB0, - XPSGTR_TYPE_USB1, - }; - - phy_types =3D types; - num_phy_types =3D ARRAY_SIZE(types); + case PHY_TYPE_USB3: + num_phy_types =3D 2; gtr_phy->protocol =3D ICM_PROTOCOL_USB; break; - } - case PHY_TYPE_DP: { - static const int types[] =3D { - XPSGTR_TYPE_DP_0, - XPSGTR_TYPE_DP_1, - }; - - phy_types =3D types; - num_phy_types =3D ARRAY_SIZE(types); + case PHY_TYPE_DP: + num_phy_types =3D 2; gtr_phy->protocol =3D ICM_PROTOCOL_DP; break; - } - case PHY_TYPE_PCIE: { - static const int types[] =3D { - XPSGTR_TYPE_PCIE_0, - XPSGTR_TYPE_PCIE_1, - XPSGTR_TYPE_PCIE_2, - XPSGTR_TYPE_PCIE_3, - }; - - phy_types =3D types; - num_phy_types =3D ARRAY_SIZE(types); + case PHY_TYPE_PCIE: + num_phy_types =3D 4; gtr_phy->protocol =3D ICM_PROTOCOL_PCIE; break; - } - case PHY_TYPE_SGMII: { - static const int types[] =3D { - XPSGTR_TYPE_SGMII0, - XPSGTR_TYPE_SGMII1, - XPSGTR_TYPE_SGMII2, - XPSGTR_TYPE_SGMII3, - }; - - phy_types =3D types; - num_phy_types =3D ARRAY_SIZE(types); + case PHY_TYPE_SGMII: + num_phy_types =3D 4; gtr_phy->protocol =3D ICM_PROTOCOL_SGMII; break; - } default: return -EINVAL; } @@ -750,22 +694,25 @@ static int xpsgtr_set_lane_type(struct xpsgtr_phy *gt= r_phy, u8 phy_type, if (phy_instance >=3D num_phy_types) return -EINVAL; =20 - gtr_phy->type =3D phy_types[phy_instance]; + gtr_phy->instance =3D phy_instance; return 0; } =20 /* - * Valid combinations of controllers and lanes (Interconnect Matrix). + * Valid combinations of controllers and lanes (Interconnect Matrix). Each + * "instance" represents one controller for a lane. For PCIe and DP, the + * "instance" is the logical lane in the link. For SATA, USB, and SGMII, + * the instance is the index of the controller. + * + * This information is only used to validate the devicetree reference, and= is + * not used when programming the hardware. */ static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] =3D { - { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, - XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 }, - { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0, - XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 }, - { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0, - XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 }, - { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1, - XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 } + /* PCIe, SATA, USB, DP, SGMII */ + { 0, 0, 0, 1, 0 }, /* Lane 0 */ + { 1, 1, 0, 0, 1 }, /* Lane 1 */ + { 2, 0, 0, 1, 2 }, /* Lane 2 */ + { 3, 1, 1, 0, 3 }, /* Lane 3 */ }; =20 /* Translate OF phandle and args to PHY instance. */ @@ -820,7 +767,7 @@ static struct phy *xpsgtr_xlate(struct device *dev, * is allowed to operate on the lane. */ for (i =3D 0; i < CONTROLLERS_PER_LANE; i++) { - if (icm_matrix[phy_lane][i] =3D=3D gtr_phy->type) + if (icm_matrix[phy_lane][i] =3D=3D gtr_phy->instance) return gtr_phy->phy; } =20 --=20 2.35.1.1320.gc452695387.dirty From nobody Wed Dec 17 15:31:43 2025 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C152280BF2 for ; Fri, 28 Jun 2024 20:56:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608169; cv=none; b=qWEXRXxxVmacsawLpYgzI4WwihPyCdr/ImTBZ3cX6Rqc4IS2mFTNVgp18QdP/ruoZ+IlzwPKN+nRC7XaaoMMHoM3zL+Lx15M7l3JEzCmk8SbqPE04TAGDk34regiYAs/Ro2Amgx2zcHMq+HcRxf6YqWVipjAhLBdhdiYPjCvB9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608169; c=relaxed/simple; bh=nopR7kksnQPVM1Lih9chyh7N87REt7rwU0ihF7ZbveY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BGpF0TAV+PFmJ9ixhYh93zqe+sqVZ9xrFehUrcggOt/s6fUjFHdf0KIzBgRFgUiW2Mrn9lupQKu4Xggvnt4hOiwhA4wyPKPpvMpoavxzGfitB/ovGCjnLX/GBzBoRZ/7JmGiXZNGOXdvMclGxC60q+VanisUkiI8RcPiHlAwePA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=AFDgDhKY; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="AFDgDhKY" X-Envelope-To: radhey.shyam.pandey@amd.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1719608166; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HEWbV4dqpa1TJriBZCpsvwB0QOnRaJIArW3SQXCHi9c=; b=AFDgDhKY0NsP3dTnmHaWQtnn6jcTiThwnjPr+V/uYInCqwflw4ml4bg9bGbEcCcOZtZt4R P+Q4wcZKBXTNZEe37nHg3mod/xb+ly7GqY1vgyhRKwTmzN2OHS/UJ+R+GYomNjWWF4Xc+X 1Z8IXM89R0k7+VXCe/pdR/IbyMMtE+E= X-Envelope-To: laurent.pinchart@ideasonboard.com X-Envelope-To: linux-phy@lists.infradead.org X-Envelope-To: vkoul@kernel.org X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: kishon@kernel.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Radhey Shyam Pandey , Laurent Pinchart , linux-phy@lists.infradead.org Cc: Vinod Koul , linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Michal Simek , Sean Anderson Subject: [PATCH v3 3/5] phy: zynqmp: Only wait for PLL lock "primary" instances Date: Fri, 28 Jun 2024 16:55:38 -0400 Message-Id: <20240628205540.3098010-4-sean.anderson@linux.dev> In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev> References: <20240628205540.3098010-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson --- (no changes since v2) Changes in v2: - Move the logic for waiting on PLL lock to xpsgtr_wait_pll_lock drivers/phy/xilinx/phy-zynqmp.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqm= p.c index a1cf32024efb..4d697e11d8eb 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -294,10 +294,30 @@ static int xpsgtr_wait_pll_lock(struct phy *phy) struct xpsgtr_phy *gtr_phy =3D phy_get_drvdata(phy); struct xpsgtr_dev *gtr_dev =3D gtr_phy->dev; unsigned int timeout =3D TIMEOUT_US; + u8 protocol =3D gtr_phy->protocol; int ret; =20 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); =20 + /* + * For DP and PCIe, only the instance 0 PLL is used. Switch to that phy + * so we wait on the right PLL. + */ + if ((protocol =3D=3D ICM_PROTOCOL_DP || protocol =3D=3D ICM_PROTOCOL_PCIE= ) && + gtr_phy->instance) { + int i; + + for (i =3D 0; i < NUM_LANES; i++) { + gtr_phy =3D >r_dev->phys[i]; + + if (gtr_phy->protocol =3D=3D protocol && !gtr_phy->instance) + goto got_phy; + } + + return -EBUSY; + } + +got_phy: while (1) { u32 reg =3D xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); =20 @@ -625,15 +645,7 @@ static int xpsgtr_phy_power_on(struct phy *phy) /* Skip initialization if not required. */ if (!xpsgtr_phy_init_required(gtr_phy)) return ret; - /* - * Wait for the PLL to lock. For DP, only wait on DP0 to avoid - * cumulating waits for both lanes. The user is expected to initialize - * lane 0 last. - */ - if (gtr_phy->protocol !=3D ICM_PROTOCOL_DP || !gtr_phy->instance) - ret =3D xpsgtr_wait_pll_lock(phy); - - return ret; + return xpsgtr_wait_pll_lock(phy); } =20 static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts = *opts) --=20 2.35.1.1320.gc452695387.dirty From nobody Wed Dec 17 15:31:43 2025 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FDCD7A715 for ; Fri, 28 Jun 2024 20:56:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608171; cv=none; b=f5fMkVGNJ/TQWKbAeQLnDyvwK2mOSh8diFZXtvPDeCS47o5lgObD5tpy6fjwYoyNpkwdo4kjw7vByF4H0AV6rXKfMd12K5C+tXu/Kmcf/w604iqiuEpOLhmN4F6XDgtlBgTWzeNoHRJMX4jd/mB+bQqF99NRiweBgEalQU4bnZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608171; c=relaxed/simple; bh=fGwvdcJajYq+BAliIScip+LfollDtBbRdL8TeQU386Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XNWXIUX9SEF2hzT0T1hf86lVmfQxiD784XCZ1PQkz2BOaBr3tWTF89XlzYKzdVV7i0ELJiT8e7J2NmwaH3BKdl3tYMP7pIAICFEwTvQiLbJ6Hn3kRWwysUcwiQhUNxYle/PLwkKV56BlazkAmZvA1dcv0SJZe/JnEVVLYRZwgxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=LoRjkfuf; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="LoRjkfuf" X-Envelope-To: radhey.shyam.pandey@amd.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1719608167; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ePtnv+mOy1V2a9C9AGkoMpYJ4bWTIeHu876bvQ6PA7w=; b=LoRjkfufmI+It1uHsu+j94T3quZNHVJZk802KYnAcvZadmEkuQvNWwdhnFHJ4kw+oR2Ajg p6tUKCEhXJioBIeC4VbIwlNoiQnr6fhdJV6h52a03Xhh2CiwUHtWPLPzjFNlBEEx0KrMkM SF3sSn/s3gj1eQhQb7b1oiKD9rrpHro= X-Envelope-To: laurent.pinchart@ideasonboard.com X-Envelope-To: linux-phy@lists.infradead.org X-Envelope-To: vkoul@kernel.org X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: kishon@kernel.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Radhey Shyam Pandey , Laurent Pinchart , linux-phy@lists.infradead.org Cc: Vinod Koul , linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Michal Simek , Sean Anderson Subject: [PATCH v3 4/5] phy: zynqmp: Take the phy mutex in xlate Date: Fri, 28 Jun 2024 16:55:39 -0400 Message-Id: <20240628205540.3098010-5-sean.anderson@linux.dev> In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev> References: <20240628205540.3098010-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Take the phy mutex in xlate to protect against concurrent modification/access to gtr_phy. This does not typically cause any issues, since in most systems the phys are only xlated once and thereafter accessed with the phy API (which takes the locks). However, we are about to allow userspace to access phys for debugging, so it's important to avoid any data races. Signed-off-by: Sean Anderson --- Changes in v3: - New drivers/phy/xilinx/phy-zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqm= p.c index 4d697e11d8eb..991be42eef3d 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -759,6 +759,7 @@ static struct phy *xpsgtr_xlate(struct device *dev, phy_type =3D args->args[1]; phy_instance =3D args->args[2]; =20 + guard(mutex)(>r_phy->phy->mutex); ret =3D xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance); if (ret < 0) { dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); --=20 2.35.1.1320.gc452695387.dirty From nobody Wed Dec 17 15:31:43 2025 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B861812FF63 for ; Fri, 28 Jun 2024 20:56:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608173; cv=none; b=DRPzHmFGg3+8TVypA2ESlDfjKdPRarPqmkaSMIUTs8LH3NX6nJXqb1GF37Tsy/z519Yz75z0+GyF0CdwwR64s/Et0GmQKhOdF7hkuaAfnez++KBjja1u9NljYLpyHoDveYQiAVf+QDct0qMUfu6hgILgDQDh3IGArC8AEYQ/fZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719608173; c=relaxed/simple; bh=Vr4GWAtkI0RK8RKzAPo9ZX18QXiqWSiamhRUG0ug9As=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NIUMm4t3fwiD5RUzNyKfe2AZ24xGnvodTUJ1KvgN2nB4j7v7fgE3QWj4bIIZodSjXFM/DN2p02TyWiA1GZTn6ybU/QkZi4MyLSlUGOQPsDcEhrGwPzkiQNqSWOEjNAK6OKO4Ttss2dgMdAqb7qj7vK4lPK56dhTppp+6QTmiL3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jlVQwsY4; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jlVQwsY4" X-Envelope-To: radhey.shyam.pandey@amd.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1719608170; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cc0/PQs/I7BBZwE0Aen+Vq0PIaX9cTiisku8tz9D9Po=; b=jlVQwsY43r14MNC0D6Flo6YEepgaDVnzgdU91I+spzzM5yeGX12vDVymiuiuwed3w1+dwF zkX4UQWOAOtby4t7+krBw4qHLQ3oQohWjYNn6s7/oU6gf5nqaUb6A7upuxwMeslkcfziLy 9Eb2ApDhlfu9CO+BrOWHjSLDWf5CDzk= X-Envelope-To: laurent.pinchart@ideasonboard.com X-Envelope-To: linux-phy@lists.infradead.org X-Envelope-To: vkoul@kernel.org X-Envelope-To: linux-arm-kernel@lists.infradead.org X-Envelope-To: kishon@kernel.org X-Envelope-To: linux-kernel@vger.kernel.org X-Envelope-To: michal.simek@amd.com X-Envelope-To: sean.anderson@linux.dev X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Sean Anderson To: Radhey Shyam Pandey , Laurent Pinchart , linux-phy@lists.infradead.org Cc: Vinod Koul , linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Michal Simek , Sean Anderson Subject: [PATCH v3 5/5] phy: zynqmp: Add debugfs support Date: Fri, 28 Jun 2024 16:55:40 -0400 Message-Id: <20240628205540.3098010-6-sean.anderson@linux.dev> In-Reply-To: <20240628205540.3098010-1-sean.anderson@linux.dev> References: <20240628205540.3098010-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Add support for printing some basic status information to debugfs. This is helpful when debugging phy consumers to make sure they are configuring the phy appropriately. Signed-off-by: Sean Anderson --- Changes in v3: - Use "none" to represent ICM_PROTOCOL_PD, since the lane may not actually be powered-down. Changes in v2: - Use debugfs_create_devm_seqfile drivers/phy/xilinx/phy-zynqmp.c | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqm= p.c index 991be42eef3d..cb15041371c9 100644 --- a/drivers/phy/xilinx/phy-zynqmp.c +++ b/drivers/phy/xilinx/phy-zynqmp.c @@ -13,6 +13,7 @@ */ =20 #include +#include #include #include #include @@ -123,6 +124,15 @@ #define ICM_PROTOCOL_DP 0x4 #define ICM_PROTOCOL_SGMII 0x5 =20 +static const char *const xpsgtr_icm_str[] =3D { + [ICM_PROTOCOL_PD] =3D "none", + [ICM_PROTOCOL_PCIE] =3D "PCIe", + [ICM_PROTOCOL_SATA] =3D "SATA", + [ICM_PROTOCOL_USB] =3D "USB", + [ICM_PROTOCOL_DP] =3D "DisplayPort", + [ICM_PROTOCOL_SGMII] =3D "SGMII", +}; + /* Test Mode common reset control parameters */ #define TM_CMN_RST 0x10018 #define TM_CMN_RST_EN 0x1 @@ -787,6 +797,34 @@ static struct phy *xpsgtr_xlate(struct device *dev, return ERR_PTR(-EINVAL); } =20 +/* + * DebugFS + */ + +static int xpsgtr_status_read(struct seq_file *seq, void *data) +{ + struct device *dev =3D seq->private; + struct xpsgtr_phy *gtr_phy =3D dev_get_drvdata(dev); + struct clk *clk; + u32 pll_status; + + mutex_lock(>r_phy->phy->mutex); + pll_status =3D xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1); + clk =3D gtr_phy->dev->clk[gtr_phy->refclk]; + + seq_printf(seq, "Lane: %u\n", gtr_phy->lane); + seq_printf(seq, "Protocol: %s\n", + xpsgtr_icm_str[gtr_phy->protocol]); + seq_printf(seq, "Instance: %u\n", gtr_phy->instance); + seq_printf(seq, "Reference clock: %u (%pC)\n", gtr_phy->refclk, clk); + seq_printf(seq, "Reference rate: %lu\n", clk_get_rate(clk)); + seq_printf(seq, "PLL locked: %s\n", + pll_status & PLL_STATUS_LOCKED ? "yes" : "no"); + + mutex_unlock(>r_phy->phy->mutex); + return 0; +} + /* * Power Management */ @@ -936,6 +974,8 @@ static int xpsgtr_probe(struct platform_device *pdev) =20 gtr_phy->phy =3D phy; phy_set_drvdata(phy, gtr_phy); + debugfs_create_devm_seqfile(&phy->dev, "status", phy->debugfs, + xpsgtr_status_read); } =20 /* Register the PHY provider. */ --=20 2.35.1.1320.gc452695387.dirty