From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BD1474BF8; Fri, 28 Jun 2024 20:13:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605613; cv=none; b=TZOuLlqcrcOw8MNmqcP6RWDG8Vzenfx2SmPzCswXKmyUtCvDZXJrMTxIOSgGFIae71ppxDZ0H2r3npSkru0kWV6rzlyPydwqBkySgCbNu98fMfOVCH6QLoklzlCQ1brmy/WnQGSN7HFyutuukeRfJE7/99gSCthfFL3NXvziDRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605613; c=relaxed/simple; bh=d8UHbC86D5le7EhTyKfMWZTXd5alVS+oeTMGdeu7JY0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iOzyfToKDM0uA3FtR073FEffK0p4dkg8ADoRC8xAV4yGDw3y9V4Dgqn4DAIqdtTuHpxcMrVM7YH2GfM8L/3ZkHArOoFi0mQJhldSoRc0RfOyW4VQTMGmzi2OoGpQ5QZizhjKUggOsyd9PzbrrTM6jmm7Q5ns2ej0kmFy2xGHc6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Rr/2tX3N; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Rr/2tX3N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605611; x=1751141611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d8UHbC86D5le7EhTyKfMWZTXd5alVS+oeTMGdeu7JY0=; b=Rr/2tX3NlbhDZCyebOEwlk+l9ujlEGHCc/0yXntTM4SgHlIsrWr60YJl TbclUNPp0zWOgZCk/4ZCxWsf9EYPlknL8dPIIkcW/GYl2tclf+jgT857Z gD+Yyk2iohOEA3jE5TgsrXVAM6Wm958iznWw11IIcl6mg4jwkTm9E4o0v u+GcGlXSF2Wwm8KYMcxlvGe6dNs9ud/62Sh/cvtTqI6WX7FAGjnhhAl20 tdP9wpEeHGFvoH6s1VHisphRPODaXJVv/hGqzmb0Qj5p8/3krUtExjotq sIUlBiMIxVLQptS4n/QHbTUrsRysFhDlOji29oEEWIXBpd0dr4orEQaAA Q==; X-CSE-ConnectionGUID: B2PVsf0gQN27Vwe567ueiA== X-CSE-MsgGUID: L/UDM/ThSJ2mDKJ/80pMqA== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12306969" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12306969" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:29 -0700 X-CSE-ConnectionGUID: kTnBrpQOTRqDTqOjnll9lw== X-CSE-MsgGUID: LFxPA/8DRFKfTLZt+bfW+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312552" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:29 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 01/11] x86/irq: Add enumeration of NMI source reporting CPU feature Date: Fri, 28 Jun 2024 13:18:29 -0700 Message-Id: <20240628201839.673086-2-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The lack of a mechanism to pinpoint the origins of Non-Maskable Interrupts (NMIs) necessitates that the NMI vector 2 handler consults each NMI source handler individually. This approach leads to inefficiencies, delays, and the occurrence of unnecessary NMIs, thereby also constraining the potential applications of NMIs. A new CPU feature, known as NMI source reporting, has been introduced as part of the Flexible Return and Event Delivery (FRED) spec. This feature enables the NMI vector 2 handler to directly obtain information about the NMI source from the FRED event data. The functionality of NMI source reporting is tied to the FRED. Although it is enumerated by a unique CPUID feature bit, it cannot be turned off independently once FRED is activated. Signed-off-by: Jacob Pan --- v3: Removed CONFIG_X86_NMI_SOURCE (Li Xin, HPA, Sohil) v2: Removed NMI source from static CPU ID dependency table (HPA) --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/traps.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 3c7434329661..ec78d361e685 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -327,6 +327,7 @@ #define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery= */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_WRMSRNS (12*32+19) /* "" Non-serializing WRMSR */ +#define X86_FEATURE_NMI_SOURCE (12*32+20) /* NMI source reporting */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMAD= D52[H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 4fa0b17e5043..465f04e4a79f 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1427,8 +1427,10 @@ early_param("fred", fred_setup); =20 void __init trap_init(void) { - if (cpu_feature_enabled(X86_FEATURE_FRED) && !enable_fred) + if (cpu_feature_enabled(X86_FEATURE_FRED) && !enable_fred) { setup_clear_cpu_cap(X86_FEATURE_FRED); + setup_clear_cpu_cap(X86_FEATURE_NMI_SOURCE); + } =20 /* Init cpu_entry_area before IST entries are set up */ setup_cpu_entry_areas(); --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A32077106; Fri, 28 Jun 2024 20:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605613; cv=none; b=tEHznX8DVlj95uS30+n2xUN29xB99YT42KRhzZKxARsEYl52OioOBH5XYA5q0Fx1jDX0vwu8z3uAriSmSgWqjubj/V8myzf1gMtJ+vsGW+Am19g2fibWfb3XRQT8YRBEtQ/4rmZZZFNk+1gLgvwBuLxlZik8NIxNbKNWvFfiHeU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605613; c=relaxed/simple; bh=YaLGreArR0RfUK3ts8KhEHnwYeH8rZjXGYjiewXAyI0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XcITi3oxi4L+fe6QwbQR2ZERWfKl1o4Y3mKcP5YEmiTLldxVyoINLVTOFtTNJ4jDOHUPSbBzA4JBSTNNjheF97PhywrukUmCJ89sNSWBuekTu6878mHsDYktCZ89sebHj6LG5NVwrvAGJxqPgEkvcB6zcGjmdWZlbQ21z8npLUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KGZNAk50; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KGZNAk50" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605612; x=1751141612; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YaLGreArR0RfUK3ts8KhEHnwYeH8rZjXGYjiewXAyI0=; b=KGZNAk50MNc0WEUHYUdqNVFHWQBaA4y2UITAMulpODXB5atL7m81dCWr RoRR2sCrl7L8z/v+yMXAlAQ3lyhRNiB1mi1BreSfxEATnnqPNWHl75QWq kDN/OieGuQMkVBLmksIHAzzXhKNRtAF30g/TY8kONnmEgjU3KMZWQ0+Cj vfUkn/HvDmop8gAbi0Qz8pLFDKJnwS3lcPkAMEs3TnakBWVUpQrkJmd1n BJz4G5pThsQhLWj9fBNUuT35sCJSWEYSYqToAn0jyst29j1cRrVP8dGTJ 4YIlnqJQYGIbvPgQFgSufKL+G+CWySblqCJtmSetJ69ijsflfsbnDxEbk w==; X-CSE-ConnectionGUID: WDFWqHaBSq+aE0SBwiEjNw== X-CSE-MsgGUID: /itxHHwQTzms2+QfgMgY8g== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12306980" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12306980" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:30 -0700 X-CSE-ConnectionGUID: LZg2+07AQCiVFmAwWpxnvg== X-CSE-MsgGUID: 4Bg6rPtFRECb+JtZ7Ls3Fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312566" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:30 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 02/11] x86/irq: Define NMI source vectors Date: Fri, 28 Jun 2024 13:18:30 -0700 Message-Id: <20240628201839.673086-3-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When NMI-source reporting is supported, each logical processor maintains a 16-bit NMI-source bitmap. It is up to the system software to assign NMI sources for their matching vector (bit position) in the bitmap. Notice that NMI source vector is in a different namespace than the IDT vectors. Though they share the same programming interface/field in the NMI originator. This initial allocation of the NMI sources are limited to local NMIs in that there is no external device NMI usage yet. Signed-off-by: Jacob Pan --- arch/x86/include/asm/irq_vectors.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_= vectors.h index 13aea8fc3d45..e4cd33bc4fef 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -105,6 +105,34 @@ =20 #define NR_VECTORS 256 =20 +/* + * The NMI senders specify the NMI source vector as an 8bit integer in the= ir + * vector field with NMI delivery mode. A local APIC receiving an NMI will + * set the corresponding bit in a 16bit bitmask, which is accumulated until + * the NMI is delivered. + * When a sender didn't specify an NMI source vector the source vector will + * be 0, which will result in bit 0 of the bitmask being set. For out of + * bounds vectors >=3D 16 bit 0 will also be set. + * When bit 0 is set, system software must invoke all registered NMI handl= ers + * as if NMI source feature is not enabled. + * + * Vector 2 is reserved for matching IDT NMI vector where it may be hardco= ded + * by some external devices. + * + * The NMI source vectors are sorted by descending priority with the excep= tions + * of 0 and 2. + */ +#define NMI_SOURCE_VEC_UNKNOWN 0 +#define NMI_SOURCE_VEC_IPI_REBOOT 1 /* Crash reboot */ +#define NMI_SOURCE_VEC_IDT_NMI 2 /* Match IDT NMI vector 2 */ +#define NMI_SOURCE_VEC_IPI_SMP_STOP 3 /* Panic stop CPU */ +#define NMI_SOURCE_VEC_IPI_BT 4 /* CPU backtrace */ +#define NMI_SOURCE_VEC_PMI 5 /* PerfMon counters */ +#define NMI_SOURCE_VEC_IPI_KGDB 6 /* KGDB */ +#define NMI_SOURCE_VEC_IPI_MCE 7 /* MCE injection */ +#define NMI_SOURCE_VEC_IPI_TEST 8 /* For remote and local IPIs */ +#define NR_NMI_SOURCE_VECTORS 9 + #ifdef CONFIG_X86_LOCAL_APIC #define FIRST_SYSTEM_VECTOR POSTED_MSI_NOTIFICATION_VECTOR #else --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCB7F7711F; Fri, 28 Jun 2024 20:13:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605614; cv=none; b=rPm0QRLDEbIS/RERbEr4tyCcVoQGMwkWG1TQ0RpR4oqHJWip3owIf0S2nvT//La+m+8pUZ3yPVl8V1Y+ybGIkM2zGvB/GPSuzvJ/h9nKnNO8Dgwi3+lqYinGpZOZehpmciae22P7FD4VhrBXvnO1hnzh9q1p2fEN6bJoo+VmqjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605614; c=relaxed/simple; bh=FIJfwu2+ZCDBeyvGH6hVptLLCTdcLErBwWfG7s8uYJI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pQ5PggGpHeKYobIjNizn73iwgHHutjiLE8eR/4XbW28prb7qlDnXWGoI7GOV7wGMyG3tqQ2Asm3L1QLxqGSDbuTu0mgwmA3Ex/aRElujDxdSW6aEpA0twu5stjmS0jh6uepz8YXIweoryCRIIr8Oxeh+3jvMQS4vM4flNcDCZX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MYfGlt52; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MYfGlt52" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605612; x=1751141612; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FIJfwu2+ZCDBeyvGH6hVptLLCTdcLErBwWfG7s8uYJI=; b=MYfGlt52VISDysraNyDnDhwnX26SwUKhvUSFA93/umEI1PzqBlPws/CF UQeCSZw+jypBqL7Up9bxCnqwjnc5VTKMJUdpFHqF8dMVh1s5vo+wdkQhv bXOvvDElq5bA0V1dmPpkbi9W6r2JDA3UDIjxHbn7nrxCSUeJEZD/lWgfW HrOtTrgUJrPbiPypLLHgiOP9yP/Zg9NvuU+J2oJKS1nJb4Kf+dbI5E7eV GbvrdwODgj7VTTqY82TbOMo+Q+L7B+ZFHqHA+mfRjbNRKJ2Qo0HGww1hX EuuVEn/fqaIJT91un9vjhFcyW8nVQ/d11FQkPRlCkK6iVE+KAUPHInWgw Q==; X-CSE-ConnectionGUID: i4lIClxiQVyC8k+6ZXDfJQ== X-CSE-MsgGUID: TZcW15dtTk+lG2y70UDFXQ== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12306988" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12306988" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:31 -0700 X-CSE-ConnectionGUID: vcm61bN2RSK2t7xQGWpO3Q== X-CSE-MsgGUID: jkQJ3vjrT/ijtwSpBr53EQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312575" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:30 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 03/11] x86/irq: Extend NMI handler registration interface to include source Date: Fri, 28 Jun 2024 13:18:31 -0700 Message-Id: <20240628201839.673086-4-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a source vector argument to register_nmi_handler() such that designated NMI originators can leverage NMI source reporting feature. For those who do not use NMI source reporting, 0 (unknown) is used as the source vector. = NMI source vectors (up to 16) are pre-defined. Signed-off-by: Jacob Pan --- v3: - Move NMI source vector definitions to a separate patch (Sohil) v2:(address review comments from HPA, not including optimizations" - Reserve IDT NMI vector 2 in case of devices use hardcoded vector 2 - Sort NMI source vector by priority in descending order Signed-off-by: Jacob Pan --- arch/x86/events/amd/ibs.c | 2 +- arch/x86/events/core.c | 3 ++- arch/x86/include/asm/nmi.h | 4 +++- arch/x86/kernel/apic/hw_nmi.c | 2 +- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 2 +- arch/x86/kernel/kgdb.c | 4 ++-- arch/x86/kernel/nmi.c | 22 ++++++++++++++++++++++ arch/x86/kernel/nmi_selftest.c | 5 +++-- arch/x86/kernel/reboot.c | 2 +- arch/x86/kernel/smp.c | 2 +- arch/x86/platform/uv/uv_nmi.c | 4 ++-- drivers/acpi/apei/ghes.c | 2 +- drivers/char/ipmi/ipmi_watchdog.c | 2 +- drivers/edac/igen6_edac.c | 2 +- drivers/watchdog/hpwdt.c | 6 +++--- 16 files changed, 46 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e91970b01d62..20989071f59a 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1246,7 +1246,7 @@ static __init int perf_event_ibs_init(void) if (ret) goto err_op; =20 - ret =3D register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ib= s"); + ret =3D register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ib= s", 0); if (ret) goto err_nmi; =20 diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 5b0dd07b1ef1..1ef2201e48ac 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2100,7 +2100,8 @@ static int __init init_hw_perf_events(void) x86_pmu.intel_ctrl =3D (1 << x86_pmu.num_counters) - 1; =20 perf_events_lapic_init(); - register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); + + register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI", NMI_SOU= RCE_VEC_PMI); =20 unconstrained =3D (struct event_constraint) __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 41a0ebb699ec..6fe26fea30eb 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -39,15 +39,17 @@ struct nmiaction { u64 max_duration; unsigned long flags; const char *name; + unsigned int source_vec; }; =20 -#define register_nmi_handler(t, fn, fg, n, init...) \ +#define register_nmi_handler(t, fn, fg, n, src, init...) \ ({ \ static struct nmiaction init fn##_na =3D { \ .list =3D LIST_HEAD_INIT(fn##_na.list), \ .handler =3D (fn), \ .name =3D (n), \ .flags =3D (fg), \ + .source_vec =3D (src), \ }; \ __register_nmi_handler((t), &fn##_na); \ }) diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 45af535c44a0..9f0125d3b8b0 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -54,7 +54,7 @@ NOKPROBE_SYMBOL(nmi_cpu_backtrace_handler); static int __init register_nmi_cpu_backtrace_handler(void) { register_nmi_handler(NMI_LOCAL, nmi_cpu_backtrace_handler, - 0, "arch_bt"); + 0, "arch_bt", NMI_SOURCE_VEC_IPI_BT); return 0; } early_initcall(register_nmi_cpu_backtrace_handler); diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 94953d749475..365a03f11d06 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -769,7 +769,7 @@ static int __init inject_init(void) =20 debugfs_init(); =20 - register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); + register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify", NMI_SO= URCE_VEC_IPI_MCE); mce_register_injector_chain(&inject_nb); =20 setup_inj_struct(&i_mce); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index e0fd57a8ba84..2fb9408a8ba9 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -486,7 +486,7 @@ static void __init ms_hyperv_init_platform(void) } =20 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, - "hv_nmi_unknown"); + "hv_nmi_unknown", 0); #endif =20 #ifdef CONFIG_X86_IO_APIC diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 9c9faa1634fb..d167eb23cf13 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -603,12 +603,12 @@ int kgdb_arch_init(void) goto out; =20 retval =3D register_nmi_handler(NMI_LOCAL, kgdb_nmi_handler, - 0, "kgdb"); + 0, "kgdb", NMI_SOURCE_VEC_IPI_KGDB); if (retval) goto out1; =20 retval =3D register_nmi_handler(NMI_UNKNOWN, kgdb_nmi_handler, - 0, "kgdb"); + 0, "kgdb", 0); =20 if (retval) goto out2; diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index ed163c8c8604..1ebe93edba7a 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -86,6 +86,12 @@ static DEFINE_PER_CPU(struct nmi_stats, nmi_stats); =20 static int ignore_nmis __read_mostly; =20 +/* + * Contains all actions registered by originators with source vector, + * excluding UNKNOWN NMI source vector 0. + */ +static struct nmiaction *nmiaction_src_table[NR_NMI_SOURCE_VECTORS - 1]; + int unknown_nmi_panic; /* * Prevent NMI reason port (0x61) being accessed simultaneously, can @@ -163,6 +169,12 @@ static int nmi_handle(unsigned int type, struct pt_reg= s *regs) } NOKPROBE_SYMBOL(nmi_handle); =20 +static inline bool use_nmi_source(unsigned int type, struct nmiaction *a) +{ + return (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE) && + type =3D=3D NMI_LOCAL && a->source_vec); +} + int __register_nmi_handler(unsigned int type, struct nmiaction *action) { struct nmi_desc *desc =3D nmi_to_desc(type); @@ -173,6 +185,11 @@ int __register_nmi_handler(unsigned int type, struct n= miaction *action) =20 raw_spin_lock_irqsave(&desc->lock, flags); =20 + if (use_nmi_source(type, action)) { + rcu_assign_pointer(nmiaction_src_table[action->source_vec], action); + pr_info("NMI source %d registered for %s\n", action->source_vec, action-= >name); + } + /* * Indicate if there are multiple registrations on the * internal NMI handler call chains (SERR and IO_CHECK). @@ -210,6 +227,11 @@ void unregister_nmi_handler(unsigned int type, const c= har *name) if (!strcmp(n->name, name)) { WARN(in_nmi(), "Trying to free NMI (%s) from NMI context!\n", n->name); + if (use_nmi_source(type, n)) { + rcu_assign_pointer(nmiaction_src_table[n->source_vec], NULL); + pr_info("NMI source %d unregistered for %s\n", n->source_vec, n->name); + } + list_del_rcu(&n->list); found =3D n; break; diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index e93a8545c74d..f014c8a66b0c 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -44,7 +44,7 @@ static void __init init_nmi_testsuite(void) { /* trap all the unknown NMIs we may generate */ register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk", - __initdata); + 0, __initdata); } =20 static void __init cleanup_nmi_testsuite(void) @@ -67,7 +67,8 @@ static void __init test_nmi_ipi(struct cpumask *mask) unsigned long timeout; =20 if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, - NMI_FLAG_FIRST, "nmi_selftest", __initdata)) { + NMI_FLAG_FIRST, "nmi_selftest", NMI_SOURCE_VEC_IPI_TEST, + __initdata)) { nmi_fail =3D FAILURE; return; } diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index f3130f762784..acc19c1d3b4f 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -910,7 +910,7 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); /* Would it be better to replace the trap vector here? */ if (register_nmi_handler(NMI_LOCAL, crash_nmi_callback, - NMI_FLAG_FIRST, "crash")) + NMI_FLAG_FIRST, "crash", NMI_SOURCE_VEC_IPI_REBOOT)) return; /* Return what? */ /* * Ensure the new callback function is set before sending diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index 18266cc3d98c..f27469e40141 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -143,7 +143,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) static int register_stop_handler(void) { return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, - NMI_FLAG_FIRST, "smp_stop"); + NMI_FLAG_FIRST, "smp_stop", NMI_SOURCE_VEC_IPI_SMP_STOP); } =20 static void native_stop_other_cpus(int wait) diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c index 5c50e550ab63..473c34eb264c 100644 --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -1029,10 +1029,10 @@ static int uv_handle_nmi_ping(unsigned int reason, = struct pt_regs *regs) =20 static void uv_register_nmi_notifier(void) { - if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) + if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv", 0)) pr_warn("UV: NMI handler failed to register\n"); =20 - if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping")) + if (register_nmi_handler(NMI_LOCAL, uv_handle_nmi_ping, 0, "uvping", 0)) pr_warn("UV: PING NMI handler failed to register\n"); } =20 diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 623cc0cb4a65..393dca95d2b3 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -1318,7 +1318,7 @@ static void ghes_nmi_add(struct ghes *ghes) { mutex_lock(&ghes_list_mutex); if (list_empty(&ghes_nmi)) - register_nmi_handler(NMI_LOCAL, ghes_notify_nmi, 0, "ghes"); + register_nmi_handler(NMI_LOCAL, ghes_notify_nmi, 0, "ghes", 0); list_add_rcu(&ghes->list, &ghes_nmi); mutex_unlock(&ghes_list_mutex); } diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_wat= chdog.c index 9a459257489f..61bb5dcade5a 100644 --- a/drivers/char/ipmi/ipmi_watchdog.c +++ b/drivers/char/ipmi/ipmi_watchdog.c @@ -1272,7 +1272,7 @@ static void check_parms(void) } if (do_nmi && !nmi_handler_registered) { rv =3D register_nmi_handler(NMI_UNKNOWN, ipmi_nmi, 0, - "ipmi"); + "ipmi", 0); if (rv) { pr_warn("Can't register nmi handler\n"); return; diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index dbe9fe5f2ca6..891278245d8b 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -1321,7 +1321,7 @@ static int register_err_handler(void) } =20 rc =3D register_nmi_handler(NMI_SERR, ecclog_nmi_handler, - 0, IGEN6_NMI_NAME); + 0, IGEN6_NMI_NAME, 0); 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X-CSE-ConnectionGUID: ZJrhWwTAQjGcnkYxQm02/w== X-CSE-MsgGUID: uD8Zu7OhRjWB1WGnDUuG8w== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12306996" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12306996" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:31 -0700 X-CSE-ConnectionGUID: PTJFqZLRTyW7yWy2U7TViA== X-CSE-MsgGUID: SR60AZVeSpa+clu/LzHgfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312580" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:31 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 04/11] x86/irq: Factor out common NMI handling code Date: Fri, 28 Jun 2024 13:18:32 -0700 Message-Id: <20240628201839.673086-5-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for handling NMIs with explicit source reporting, factor out common code for reuse. Signed-off-by: Jacob Pan --- arch/x86/kernel/nmi.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 1ebe93edba7a..639a34e78bc9 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -135,6 +135,20 @@ static void nmi_check_duration(struct nmiaction *actio= n, u64 duration) action->handler, duration, decimal_msecs); } =20 +static inline int do_handle_nmi(struct nmiaction *a, struct pt_regs *regs,= unsigned int type) +{ + int thishandled; + u64 delta; + + delta =3D sched_clock(); + thishandled =3D a->handler(type, regs); + delta =3D sched_clock() - delta; + trace_nmi_handler(a->handler, (int)delta, thishandled); + nmi_check_duration(a, delta); + + return thishandled; +} + static int nmi_handle(unsigned int type, struct pt_regs *regs) { struct nmi_desc *desc =3D nmi_to_desc(type); @@ -149,18 +163,8 @@ static int nmi_handle(unsigned int type, struct pt_reg= s *regs) * can be latched at any given time. Walk the whole list * to handle those situations. */ - list_for_each_entry_rcu(a, &desc->head, list) { - int thishandled; - u64 delta; - - delta =3D sched_clock(); - thishandled =3D a->handler(type, regs); - handled +=3D thishandled; - delta =3D sched_clock() - delta; - trace_nmi_handler(a->handler, (int)delta, thishandled); - - nmi_check_duration(a, delta); - } + list_for_each_entry_rcu(a, &desc->head, list) + handled +=3D do_handle_nmi(a, regs, type); =20 rcu_read_unlock(); =20 --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D4AD78C7A; Fri, 28 Jun 2024 20:13:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605615; cv=none; b=n2jLam3u4G7KoBRVh64641uU13s760KQxR+n98ZglO8+ZCjsVpuOIUw2x3zi8L+wvX26o96lidCmY07WCbeXLxWAaG7qe6+Q8tuw0LXH79ICbpkeYSDNFUtS6+5PNBN2JdKAElcS1YLG8oxnMDcYEuxTRPxoY+4YtpvBPCPmrsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605615; c=relaxed/simple; bh=omPgNj4vn9rg/7X/W1rrU+ad7KQp3WxkvLYbjpheWIs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mIPP5FaJzY2Utl8pBxL7mxwXMDvGHy9FCZXk3ZDRx0b+PhirAoyeM7C+orTJxrYDMK3ptzcYvOjjRMBLTsD8avZ7jgaKJKJOhOl8w8nvhUX9BGjsj71TxVUiX80pq16wFTmu0wRsDfeMVXzth447WbaZ4tfhbiTP2zFxzx70KD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=irsGS1E3; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="irsGS1E3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605614; x=1751141614; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=omPgNj4vn9rg/7X/W1rrU+ad7KQp3WxkvLYbjpheWIs=; b=irsGS1E3CLde5XKt0hk+puaezehDY2aqzIuySKFfqU82eA/o2mFrvy/M XrpkKAkDxoC1mOFN1bEhupcFNZlRxfuBGxu3zdiDBx+wjb81dBtPtrH6X bIiCVrIbe0miJLbMt0XPx0SCmldCtuG0TyFN6SO6GPZ1aqJAmvWCL1hjK K5B/LKOUf3+YDDMrHRiYZr+yq90Wbj8UaFaT2Qp6Ury+WhQQm5pqDfXqU cjvz8K3oubFXH/uyzH4TqFCCs1CQJS1PidcEFO+O3rKgzXpRhy9TaLtUl plmmR/NG3xPh/X1d0WefxTdNQEvagwq1LqcR5zf0KsNEWbh+5KsHlTl/S A==; X-CSE-ConnectionGUID: jlo54/F8RZa6RgKBE2ZprA== X-CSE-MsgGUID: aHSYvlKnR0GEvDwmPuRQ8g== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12307004" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12307004" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:32 -0700 X-CSE-ConnectionGUID: ouM+YWGZQ6yE25ZvcJpS7w== X-CSE-MsgGUID: /uQ/kxEpSLWzi4duddorBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312583" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:32 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 05/11] x86/irq: Process nmi sources in NMI handler Date: Fri, 28 Jun 2024 13:18:33 -0700 Message-Id: <20240628201839.673086-6-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With NMI source reporting enabled, NMI handler can prioritize the handling of sources reported explicitly. If the source is unknown, then resume the existing processing flow. i.e. invoke all NMI handlers. Signed-off-by: Jacob Pan --- v3: - Use a static flag to disable NMIs in case of HW failure - Optimize the case when unknown NMIs are mixed with known NMIs(HPA) v2: - Disable NMI source reporting once garbage data is given in FRED return stack. (HPA) --- arch/x86/kernel/nmi.c | 73 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 639a34e78bc9..c3a10af7f26b 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -149,23 +149,90 @@ static inline int do_handle_nmi(struct nmiaction *a, = struct pt_regs *regs, unsig return thishandled; } =20 +static int nmi_handle_src(unsigned int type, struct pt_regs *regs, unsigne= d long *handled_mask) +{ + static bool nmi_source_disabled; + bool has_unknown_src =3D false; + unsigned long source_bitmask; + struct nmiaction *a; + int handled =3D 0; + int vec =3D 1; + + if (!cpu_feature_enabled(X86_FEATURE_NMI_SOURCE) || + type !=3D NMI_LOCAL || nmi_source_disabled) + return 0; + + source_bitmask =3D fred_event_data(regs); + if (!source_bitmask) { + pr_warn("NMI received without source information! Disable source reporti= ng.\n"); + nmi_source_disabled =3D true; + return 0; + } + + /* + * Per NMI source specification, there is no guarantee that a valid + * NMI vector is always delivered, even when the source specified + * one. It is software's responsibility to check all available NMI + * sources when bit 0 is set in the NMI source bitmap. i.e. we have + * to call every handler as if we have no NMI source. + * On the other hand, if we do get non-zero vectors, we know exactly + * what the sources are. So we only call the handlers with the bit set. + */ + if (source_bitmask & BIT(NMI_SOURCE_VEC_UNKNOWN)) { + pr_warn_ratelimited("NMI received with unknown source\n"); + has_unknown_src =3D true; + } + + rcu_read_lock(); + /* Bit 0 is for unknown NMI sources, skip it. */ + for_each_set_bit_from(vec, &source_bitmask, NR_NMI_SOURCE_VECTORS) { + a =3D rcu_dereference(nmiaction_src_table[vec]); + if (!a) { + pr_warn_ratelimited("NMI received %d no handler", vec); + continue; + } + handled +=3D do_handle_nmi(a, regs, type); + /* + * Needs polling if unknown source bit is set, handled_mask is + * used to tell the polling code which NMIs can be skipped. + */ + if (has_unknown_src) + *handled_mask |=3D BIT(vec); + } + rcu_read_unlock(); + + return handled; +} + static int nmi_handle(unsigned int type, struct pt_regs *regs) { struct nmi_desc *desc =3D nmi_to_desc(type); + unsigned long handled_mask =3D 0; struct nmiaction *a; int handled=3D0; =20 - rcu_read_lock(); + /* + * Check if the NMI source handling is complete, otherwise polling is + * still required. handled_mask is non-zero if NMI source handling is + * partial due to unknown NMI sources. + */ + handled =3D nmi_handle_src(type, regs, &handled_mask); + if (handled && !handled_mask) + return handled; =20 + rcu_read_lock(); /* * NMIs are edge-triggered, which means if you have enough * of them concurrently, you can lose some because only one * can be latched at any given time. Walk the whole list * to handle those situations. */ - list_for_each_entry_rcu(a, &desc->head, list) + list_for_each_entry_rcu(a, &desc->head, list) { + /* Skip NMIs handled earlier with source info */ + if (BIT(a->source_vec) & handled_mask) + continue; handled +=3D do_handle_nmi(a, regs, type); - + } rcu_read_unlock(); =20 /* return total number of NMI events handled */ --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E04947A715; Fri, 28 Jun 2024 20:13:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605616; cv=none; b=lNva8O8BUy4vOj+ZdqgxJV/koMHE+FMhjlCq/iAYxQZF/zpLTJppaV8yqE/ToHIKUZbfjiBjUr5BotSEW6mOyNhzsFfySJGIAnFImKBgOgr9sXZORbadldMEo35jNiO4r0D+7/2qUyHvemEAYRn7/1yTDeA7pKIf7hCUozWR8Y8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605616; c=relaxed/simple; bh=e365/ZxkgEc9NqLkEwPGQtSfS583CvbekuFVDfTCoz4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FHBrL+1Pu8dSN5JCJTvA/TREq9pGL+2XcLXKyhA2UICXMbt4uw15ZrOIM8qoy0iJCKLcBL+DaSbEc3Ejr9uPOmo2/+iTcWGbZh49XEITObFzh+5+KAV39IST4Oo1S64NilGT5ZlcdvVO8zxcaGcZHs7YaStSIgaMoGu1MWHrzjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=n/JYYr6D; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="n/JYYr6D" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605615; x=1751141615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e365/ZxkgEc9NqLkEwPGQtSfS583CvbekuFVDfTCoz4=; b=n/JYYr6DmnEE+eCtV9GgdDvzZbCnIlD18X14ffLsSHKuJFMuQGMjg4Q5 QJbnIKjGlDcCorOQ40q2VafyU2ytLalg8nYg0Yr8jUT3rSuUh7DlaDZe4 TkQmHTfKlCNPfnL4PqIbyluXER89b+CUZvLZl4CuiLAcit8EnageGpynp VhLpt8xr99LsrP8t8NQaHny0U5xQqDHeR/ZpqZW3H5E4hiHjBAe8AztKz didr1feFDn4uD5ejASVg27Y8AQlFwDT9gHPzvwzjtQmP8hlSheVq267+/ w5focpiQ/kYrQdyniq5r30+czPy4h/X6ZeAi2tZLzmc38NYt5a1f8smeH A==; X-CSE-ConnectionGUID: xuew7Y29SGWr7RhIkK4UAQ== X-CSE-MsgGUID: Us8pPQfZSs2t/A3fSbeZYg== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12307012" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12307012" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:32 -0700 X-CSE-ConnectionGUID: u4+LddL8TdylEeYykAA3Lw== X-CSE-MsgGUID: ZuerWa87TTCJFwC9HU/QTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312586" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:32 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Zeng Guang , Jacob Pan Subject: [PATCH v3 06/11] KVM: VMX: Expand FRED kvm entry with event data Date: Fri, 28 Jun 2024 13:18:34 -0700 Message-Id: <20240628201839.673086-7-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zeng Guang For VM exits caused by events (NMI, #DB, and #PF) delivered by FRED, the event data is saved in the exit-qualification field. (FRED spec. 10.6.2) Expand FRED KVM entry interface to include the event data obtained from the exit qualification. Signed-off-by: Zeng Guang Signed-off-by: Jacob Pan --- arch/x86/include/asm/fred.h | 8 ++++---- arch/x86/kvm/vmx/vmx.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index e86c7ba32435..15f5d2eabd1d 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -63,14 +63,14 @@ static __always_inline unsigned long fred_event_data(st= ruct pt_regs *regs) =20 void asm_fred_entrypoint_user(void); void asm_fred_entrypoint_kernel(void); -void asm_fred_entry_from_kvm(struct fred_ss); +void asm_fred_entry_from_kvm(struct fred_ss, unsigned long edata); =20 __visible void fred_entry_from_user(struct pt_regs *regs); __visible void fred_entry_from_kernel(struct pt_regs *regs); __visible void __fred_entry_from_kvm(struct pt_regs *regs); =20 /* Can be called from noinstr code, thus __always_inline */ -static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector) +static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector, unsigned long edata) { struct fred_ss ss =3D { .ss =3D__KERNEL_DS, @@ -80,7 +80,7 @@ static __always_inline void fred_entry_from_kvm(unsigned = int type, unsigned int .lm =3D 1, }; =20 - asm_fred_entry_from_kvm(ss); + asm_fred_entry_from_kvm(ss, edata); } =20 void cpu_init_fred_exceptions(void); @@ -90,7 +90,7 @@ void fred_complete_exception_setup(void); static __always_inline unsigned long fred_event_data(struct pt_regs *regs)= { return 0; } static inline void cpu_init_fred_exceptions(void) { } static inline void fred_complete_exception_setup(void) { } -static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector) { } +static __always_inline void fred_entry_from_kvm(unsigned int type, unsigne= d int vector, unsigned long edata) { } #endif /* CONFIG_X86_FRED */ #endif /* !__ASSEMBLY__ */ =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b3c83c06f826..4e7b36081b76 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7024,7 +7024,7 @@ static void handle_external_interrupt_irqoff(struct k= vm_vcpu *vcpu, =20 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_EXTINT, vector); + fred_entry_from_kvm(EVENT_TYPE_EXTINT, vector, 0); else vmx_do_interrupt_irqoff(gate_offset((gate_desc *)host_idt_base + vector)= ); kvm_after_interrupt(vcpu); @@ -7332,7 +7332,7 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vc= pu *vcpu, is_nmi(vmx_get_intr_info(vcpu))) { kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR); + fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR, 0); else vmx_do_nmi_irqoff(); kvm_after_interrupt(vcpu); --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B1E07BB0A; Fri, 28 Jun 2024 20:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="12307020" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:33 -0700 X-CSE-ConnectionGUID: mYQouYAZTdOcQJ6tL0/j0Q== X-CSE-MsgGUID: Y8uVGEemTh+ExHNpAyl7VA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312592" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:33 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Zeng Guang , Jacob Pan Subject: [PATCH v3 07/11] KVM: VMX: Handle NMI Source report in VM exit Date: Fri, 28 Jun 2024 13:18:35 -0700 Message-Id: <20240628201839.673086-8-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zeng Guang If the "NMI exiting" VM-execution control is 1, the value of the 16-bit NMI source vector is saved in the exit-qualification field in the VMCS when VM exits occur on CPUs that support NMI source. KVM that is aware of NMI-source reporting will push the bitmask of NMI sour= ce vectors as the exceptoin event data field on the stack for then entry of FR= ED exception. Subsequently, the host NMI exception handler is invoked which will process NMI source information in the event data. This operation is independent of vCPU FRED enabling status. Signed-off-by: Zeng Guang Signed-off-by: Jacob Pan --- arch/x86/entry/entry_64_fred.S | 2 +- arch/x86/kvm/vmx/vmx.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/entry/entry_64_fred.S b/arch/x86/entry/entry_64_fred.S index a02bc6f3d2e6..0d934a3fcaf8 100644 --- a/arch/x86/entry/entry_64_fred.S +++ b/arch/x86/entry/entry_64_fred.S @@ -92,7 +92,7 @@ SYM_FUNC_START(asm_fred_entry_from_kvm) * +--------+-----------------+ */ push $0 /* Reserved, must be 0 */ - push $0 /* Event data, 0 for IRQ/NMI */ + push %rsi /* Event data for IRQ/NMI */ push %rdi /* fred_ss handed in by the caller */ push %rbp pushf diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 4e7b36081b76..6719c598fa5f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7331,10 +7331,15 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_= vcpu *vcpu, if ((u16)vmx->exit_reason.basic =3D=3D EXIT_REASON_EXCEPTION_NMI && is_nmi(vmx_get_intr_info(vcpu))) { kvm_before_interrupt(vcpu, KVM_HANDLING_NMI); - if (cpu_feature_enabled(X86_FEATURE_FRED)) - fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR, 0); - else + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + unsigned long edata =3D 0; + + if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) + edata =3D vmx_get_exit_qual(vcpu); + fred_entry_from_kvm(EVENT_TYPE_NMI, NMI_VECTOR, edata); + } else { vmx_do_nmi_irqoff(); + } kvm_after_interrupt(vcpu); } =20 --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B28187E103; Fri, 28 Jun 2024 20:13:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605617; cv=none; b=XzI73I7F9+k47XUQmwP8JyfXTY7S6bT90vVGAYXCyfdkqx3RwTF+8NK0gdRr4B4pa6K2gEijyQHQXpGjCLg7HZNNDFKXuj5DaYYKEFQKTYSCGzUw0nzU0QY/5w6GWYYqom7NyMDkSEVjizj3EIkfmztoZA5Cr4xfCVbhuHiH8rE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605617; c=relaxed/simple; bh=k6q6WxbyXw0+7mPgcDLUOmJB6APsUSfvyDqOQXl4s+Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Gy/do5+3mU+YG1OkJ22G2pg//H3o7n1PRBP2JjwdTDzxPc9tcYXH0Ii0EIjtKkl+ezZBif/LbqGhkRxCp/RkEMPFBSGR/6vyTn8ZJO0M+Xldx81SIxyp13HXpv8qY6PdNp6GapP4ACOWPqrhA81TY3QCTw6AnrcigV9HV955gqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z009rNsG; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z009rNsG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605615; x=1751141615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k6q6WxbyXw0+7mPgcDLUOmJB6APsUSfvyDqOQXl4s+Q=; b=Z009rNsGqt+1frZoSbqpWDiOhztRUuA7LFW6K4NtN8zHuMqtrSJFlVEA 7vGdpdcIB/uAbfJBjHJtZjpomsP0LhvYKAWGJnaGeQ3w6oicycO35Bgeg O1xVE3s/p3rTHqC5e/LjKeRRMp8Oz2oBqRsr3IQTInZxSRmZBSbDgHtZ+ QZ8gi+qmiQNcJt2PhMrqSONM4SpMHdyY53NEOdDIf7jYmYscsp7eVbMmP aisJ9bMpKJXwXn1oUZXYrvtH9083x/DTuOrywn4nH/sM1D9WZhEMR5/XS 79zOSri/HzhN/h75OL4270Yu7Q6RHaUZNLj920XXtobB1bXtfzZWE0LhC Q==; X-CSE-ConnectionGUID: DfgKSmFEQr21PmEXHQVxLA== X-CSE-MsgGUID: UmFxBJD1SJuC1QP+RjQeQw== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12307028" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12307028" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:33 -0700 X-CSE-ConnectionGUID: IpoE4qTESu6CEJKscEUvLw== X-CSE-MsgGUID: VUV5Dq8DS/GtHs234Yo4JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312597" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:33 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan , Zeng Guang Subject: [PATCH v3 08/11] perf/x86: Enable NMI source reporting for perfmon Date: Fri, 28 Jun 2024 13:18:36 -0700 Message-Id: <20240628201839.673086-9-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Program the designated NMI source vector into the performance monitoring interrupt (PMI) of the local vector table. PMI handler will be directly invoked when its NMI is generated. This avoids the latency of calling all NMI handlers blindly. Co-developed-by: Zeng Guang Signed-off-by: Zeng Guang Signed-off-by: Jacob Pan --- v3: Program NMI source vector in PVTPC unconditionally (HPA) v2: Fix a compile error apic_perfmon_ctr is undefined in i386 config --- arch/x86/events/core.c | 6 ++++-- arch/x86/events/intel/core.c | 6 +++--- arch/x86/include/asm/apic.h | 1 + 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 1ef2201e48ac..be75bdcdd400 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -46,6 +46,7 @@ =20 struct x86_pmu x86_pmu __read_mostly; static struct pmu pmu; +u32 apic_perfmon_ctr =3D APIC_DM_NMI; =20 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) =3D { .enabled =3D 1, @@ -1680,7 +1681,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs) * This generic handler doesn't seem to have any issues where the * unmasking occurs so it was left at the top. */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, apic_perfmon_ctr); =20 for (idx =3D 0; idx < x86_pmu.num_counters; idx++) { if (!test_bit(idx, cpuc->active_mask)) @@ -1723,7 +1724,8 @@ void perf_events_lapic_init(void) /* * Always use NMI for PMU */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_perfmon_ctr |=3D NMI_SOURCE_VEC_PMI; + apic_write(APIC_LVTPC, apic_perfmon_ctr); } =20 static int diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 38c1b1f1deaa..b4a70457c678 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3093,7 +3093,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * NMI handler. */ if (!late_ack && !mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, apic_perfmon_ctr); intel_bts_disable_local(); cpuc->enabled =3D 0; __intel_pmu_disable_all(true); @@ -3130,7 +3130,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) =20 done: if (mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, apic_perfmon_ctr); /* Only restore PMU state when it's active. See x86_pmu_disable(). */ cpuc->enabled =3D pmu_enabled; if (pmu_enabled) @@ -3143,7 +3143,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * Haswell CPUs. */ if (late_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, apic_perfmon_ctr); return handled; } =20 diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9327eb00e96d..bcf8d17240c8 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -49,6 +49,7 @@ static inline void x86_32_probe_apic(void) { } #endif =20 extern u32 cpuid_to_apicid[]; +extern u32 apic_perfmon_ctr; =20 #define CPU_ACPIID_INVALID U32_MAX =20 --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D189A7FBD1; Fri, 28 Jun 2024 20:13:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605618; cv=none; b=avXQcfR3Bv9nq5st+9DoLO9HaOmHgsAvWnSvPU+WkBaRuFd7YJS9K6Bhr93AJOZEzLfFNDIpCRcHODOsDu99UWF4PzrQ8zWOlQLtimAY8aIOHcYhQjcrvAG9fTn1E+4lOGH6pfY8+tpHH6RwhYQ5JMLnCoTlkwiM8Zp0jQad6Qo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719605618; c=relaxed/simple; bh=iBLQ6Tub7d00Y27yhd75nvfYjn+GuvWBLg/Pb8XSVR0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XCnWcXJfMFMsWfJljbwgzdGGWwPlevxcsQLvqxXsnBs3+MLdekxhaD3wUb08DDyYCMYGrqc6guLlUgMpSpQfVTy+HAMghvHMmxkEJL/UdF1eOHIU8yVhEdvhsH+LcHUG6kCltAsA2L7JW0YOq2CC509mzPLJTkRqm+sQaI82aLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MX77Cogd; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MX77Cogd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719605616; x=1751141616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iBLQ6Tub7d00Y27yhd75nvfYjn+GuvWBLg/Pb8XSVR0=; b=MX77CogdRbkms6QbUJpGTbxEb1xPCAqRUH+hNiM4xwP8bMHCZJbnsBxi 1ywiz+BispRG8LmtgQ4EFHo7gVyLdUVqxCKvMWd5/WqUiZ6vCfsq7K6mi W+x8wrCelmTr8hbi15jeCjD/x5/tpSNR/qY+nDU9ZHBgtj00gaDmy6u10 sqs7wUNsVs2/SMWD/P1qMj06a7gJjJ31jDmgc9eCWxp0WO0R+CgqwfjsK 4zyBqXr4wH82izsNCx2OdJ1JX3ff1VeZhnzu0XNkpeLaWFZAqPEveA4Vd RvEHnusa7BKBxwhCylhd2eUoTQc7RZ7laqT6OefTKf5wIePpHULZiBFzI g==; X-CSE-ConnectionGUID: 3ZDx6P17RqiEO2G9tNvL4g== X-CSE-MsgGUID: HrBjqJFGTNK40ZEXqKqHnw== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12307036" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12307036" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:34 -0700 X-CSE-ConnectionGUID: WtlFv8AERYupM5Vr+TkZfQ== X-CSE-MsgGUID: oTSGtKNJTviDZdUtwsrVvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312600" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:34 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 09/11] x86/irq: Enable NMI source on IPIs delivered as NMI Date: Fri, 28 Jun 2024 13:18:37 -0700 Message-Id: <20240628201839.673086-10-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Program designated NMI source vectors for all NMI delivered IPIs such that their handlers can be selectively invoked. Signed-off-by: Jacob Pan --- arch/x86/include/asm/irq_vectors.h | 10 ++++++++++ arch/x86/kernel/apic/hw_nmi.c | 3 ++- arch/x86/kernel/apic/ipi.c | 4 ++-- arch/x86/kernel/apic/local.h | 18 ++++++++++++------ arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/kgdb.c | 2 +- arch/x86/kernel/nmi_selftest.c | 2 +- arch/x86/kernel/reboot.c | 2 +- arch/x86/kernel/smp.c | 2 +- 9 files changed, 31 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_= vectors.h index e4cd33bc4fef..4cedebdc1afb 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -133,6 +133,16 @@ #define NMI_SOURCE_VEC_IPI_TEST 8 /* For remote and local IPIs */ #define NR_NMI_SOURCE_VECTORS 9 =20 +/* + * When programming the local APIC, IDT NMI vector and NMI source vector + * are encoded in a single 32 bit variable. The top 16 bits contain + * the NMI source vector and the bottom 16 bits contain NMI_VECTOR (2) + * The top 16 bits are always zero when NMI source feature is not enabled + * or the caller does not use NMI source. + */ +#define NMI_VECTOR_WITH_SOURCE(src) (NMI_VECTOR | (src << 16)) +#define NMI_SOURCE_VEC_MASK GENMASK(15, 0) + #ifdef CONFIG_X86_LOCAL_APIC #define FIRST_SYSTEM_VECTOR POSTED_MSI_NOTIFICATION_VECTOR #else diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index 9f0125d3b8b0..f73ca95d961e 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include "local.h" =20 @@ -33,7 +34,7 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh) #ifdef arch_trigger_cpumask_backtrace static void nmi_raise_cpu_backtrace(cpumask_t *mask) { - __apic_send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR_WITH_SOURCE(NMI_SOURCE_VEC_IPI_BT)); } =20 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c index 5da693d633b7..9d2b18e58758 100644 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -157,7 +157,7 @@ static void __default_send_IPI_shortcut(unsigned int sh= ortcut, int vector) * issues where otherwise the system hangs when the panic CPU tries * to stop the others before launching the kdump kernel. */ - if (unlikely(vector =3D=3D NMI_VECTOR)) + if (unlikely(is_nmi_vector(vector))) apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); @@ -174,7 +174,7 @@ void __default_send_IPI_dest_field(unsigned int dest_ma= sk, int vector, unsigned int dest_mode) { /* See comment in __default_send_IPI_shortcut() */ - if (unlikely(vector =3D=3D NMI_VECTOR)) + if (unlikely(is_nmi_vector(vector))) apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 842fe28496be..60e90b7bf058 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -12,6 +12,7 @@ =20 #include #include +#include =20 /* X2APIC */ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); @@ -26,19 +27,24 @@ extern u32 x2apic_max_apicid; =20 DECLARE_STATIC_KEY_FALSE(apic_use_ipi_shorthand); =20 +static inline bool is_nmi_vector(int vector) +{ + return (vector & NMI_SOURCE_VEC_MASK) =3D=3D NMI_VECTOR; +} + static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, unsigned int dest) { unsigned int icr =3D shortcut | dest; =20 - switch (vector) { - default: - icr |=3D APIC_DM_FIXED | vector; - break; - case NMI_VECTOR: + if (is_nmi_vector(vector)) { icr |=3D APIC_DM_NMI; - break; + if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) + icr |=3D vector >> 16; + } else { + icr |=3D APIC_DM_FIXED | vector; } + return icr; } =20 diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index 365a03f11d06..07bc6c29bd83 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -270,7 +270,7 @@ static void __maybe_unused raise_mce(struct mce *m) mce_irq_ipi, NULL, 0); preempt_enable(); } else if (m->inject_flags & MCJ_NMI_BROADCAST) - __apic_send_IPI_mask(mce_inject_cpumask, NMI_VECTOR); + __apic_send_IPI_mask(mce_inject_cpumask, NMI_VECTOR_WITH_SOURCE(NMI_SO= URCE_VEC_IPI_MCE)); } start =3D jiffies; while (!cpumask_empty(mce_inject_cpumask)) { diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index d167eb23cf13..02198cf9fe21 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -416,7 +416,7 @@ static void kgdb_disable_hw_debug(struct pt_regs *regs) */ void kgdb_roundup_cpus(void) { - apic_send_IPI_allbutself(NMI_VECTOR); + apic_send_IPI_allbutself(NMI_VECTOR_WITH_SOURCE(NMI_SOURCE_VEC_IPI_KGDB)); } #endif =20 diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index f014c8a66b0c..5aa122d3368c 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -76,7 +76,7 @@ static void __init test_nmi_ipi(struct cpumask *mask) /* sync above data before sending NMI */ wmb(); =20 - __apic_send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR_WITH_SOURCE(NMI_SOURCE_VEC_IPI_TEST= )); =20 /* Don't wait longer than a second */ timeout =3D USEC_PER_SEC; diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index acc19c1d3b4f..fb63bc0d6a0f 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -918,7 +918,7 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) */ wmb(); =20 - apic_send_IPI_allbutself(NMI_VECTOR); + apic_send_IPI_allbutself(NMI_VECTOR_WITH_SOURCE(NMI_SOURCE_VEC_IPI_REBOOT= )); =20 /* Kick CPUs looping in NMI context. */ WRITE_ONCE(crash_ipi_issued, 1); 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d="scan'208";a="49312605" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:34 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan Subject: [PATCH v3 10/11] x86/irq: Move __prepare_ICR to x86 common header Date: Fri, 28 Jun 2024 13:18:38 -0700 Message-Id: <20240628201839.673086-11-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reuse __prepare_ICR() outside APIC local code, move it to the x86 common header. e.g. It can be used by the KVM PV IPI code. Signed-off-by: Jacob Pan --- arch/x86/include/asm/apic.h | 21 +++++++++++++++++++++ arch/x86/kernel/apic/local.h | 22 ---------------------- 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index bcf8d17240c8..7fb4c3dae569 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -476,6 +476,27 @@ static __always_inline bool apic_id_valid(u32 apic_id) return apic_id <=3D apic->max_apic_id; } =20 +static inline bool is_nmi_vector(int vector) +{ + return (vector & NMI_SOURCE_VEC_MASK) =3D=3D NMI_VECTOR; +} + +static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, + unsigned int dest) +{ + unsigned int icr =3D shortcut | dest; + + if (is_nmi_vector(vector)) { + icr |=3D APIC_DM_NMI; + if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) + icr |=3D vector >> 16; + } else { + icr |=3D APIC_DM_FIXED | vector; + } + + return icr; +} + #else /* CONFIG_X86_LOCAL_APIC */ =20 static inline u32 apic_read(u32 reg) { return 0; } diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h index 60e90b7bf058..8b1fe152cd2d 100644 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -12,7 +12,6 @@ =20 #include #include -#include =20 /* X2APIC */ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); @@ -27,27 +26,6 @@ extern u32 x2apic_max_apicid; =20 DECLARE_STATIC_KEY_FALSE(apic_use_ipi_shorthand); =20 -static inline bool is_nmi_vector(int vector) -{ - return (vector & NMI_SOURCE_VEC_MASK) =3D=3D NMI_VECTOR; -} - -static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, - unsigned int dest) -{ - unsigned int icr =3D shortcut | dest; - - if (is_nmi_vector(vector)) { - icr |=3D APIC_DM_NMI; - if (cpu_feature_enabled(X86_FEATURE_NMI_SOURCE)) - icr |=3D vector >> 16; - } else { - icr |=3D APIC_DM_FIXED | vector; - } - - return icr; -} - void default_init_apic_ldr(void); =20 void apic_mem_wait_icr_idle(void); --=20 2.25.1 From nobody Tue Dec 16 14:35:47 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6644E80638; 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X-CSE-ConnectionGUID: FgSFohjgTP2f4pNbXuqkAw== X-CSE-MsgGUID: IytP9Ts7QCSz3LYWrOb75g== X-IronPort-AV: E=McAfee;i="6700,10204,11117"; a="12307052" X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="12307052" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2024 13:13:35 -0700 X-CSE-ConnectionGUID: c7dr9gDMTX2z11wPmeakXQ== X-CSE-MsgGUID: qt1jX1cSSeCKD9iqlQseGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,170,1716274800"; d="scan'208";a="49312608" Received: from jacob-builder.jf.intel.com ([10.54.39.125]) by fmviesa005.fm.intel.com with ESMTP; 28 Jun 2024 13:13:35 -0700 From: Jacob Pan To: X86 Kernel , Sean Christopherson , LKML , Thomas Gleixner , Dave Hansen , "H. Peter Anvin" , "Ingo Molnar" , "Borislav Petkov" , "Xin Li" , linux-perf-users@vger.kernel.org, Peter Zijlstra Cc: Paolo Bonzini , Tony Luck , Andy Lutomirski , acme@kernel.org, kan.liang@linux.intel.com, Andi Kleen , "Mehta, Sohil" , Jacob Pan , Zeng Guang Subject: [PATCH v3 11/11] KVM: X86: Use common code for PV IPIs in linux guest Date: Fri, 28 Jun 2024 13:18:39 -0700 Message-Id: <20240628201839.673086-12-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> References: <20240628201839.673086-1-jacob.jun.pan@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Paravirtual apic hooks to enable PV IPIs for KVM if the "send IPI" hypercall is available. Reuse common code for ICR preparation which covers NMI-source reporting if in effect. Originally-by: Zeng Guang Signed-off-by: Jacob Pan --- arch/x86/kernel/kvm.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 263f8aed4e2c..a45d60aa0302 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -516,15 +516,7 @@ static void __send_ipi_mask(const struct cpumask *mask= , int vector) =20 local_irq_save(flags); =20 - switch (vector) { - default: - icr =3D APIC_DM_FIXED | vector; - break; - case NMI_VECTOR: - icr =3D APIC_DM_NMI; - break; - } - + icr =3D __prepare_ICR(0, vector, 0); for_each_cpu(cpu, mask) { apic_id =3D per_cpu(x86_cpu_to_apicid, cpu); if (!ipi_bitmap) { --=20 2.25.1