From nobody Sun Dec 14 19:12:48 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F951CE0B2; Fri, 28 Jun 2024 15:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; cv=none; b=lrGWBStZ7wg8OtTppKVLf0keFocOgoRjq/xd3U99GHrIOB+4zuzlBxz3JUO1iphTqWfZ8IRkoD10ncLjFJdFeQwgP9CjEx+YbegJQrJaboIcYd+DKlXnxhPVf4HY6QhyjwQyVqTFuexTRzb13rmiR99UQZNYCJuf/1LGxv18t0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; c=relaxed/simple; bh=SS4l0vhuF8ANyvYivJMIGd8T3vZtD+Iy2iMKpSpG60Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VvUbJVbLs1rus4Etx/Uq7mSrcEd6LwkFZ5HvhCC5GjKZFV8h4STQ5c8wqj1hvbX7+ECLdAJzoGeERLATnv2mKAz0Id09V5LeMYmrVmDXZMG1vqCBw9qaPYEVWPlCbidiCM5ZwnMcX5vMRa9Kg6pIDBCpd8tLpYrFclTNMQRvUwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mtI8CfAZ; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mtI8CfAZ" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFKr5116465; Fri, 28 Jun 2024 10:15:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719587720; bh=QBMXpMS/iIZmIAzbQBnrntRuZS3CoOQYWfG3olNAVW8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mtI8CfAZmxW0vc0X6hir+pidupvtmy6xnuJnWM/Fdc7aiAnxvkTjtnlbqPvZAjFBk qBShujywcMhvvy6KmIIWyYSAVL/mVixPdjJgAjxEMLgxNTdxoYDPtC65Fa6zd5/Oxu CbR5L78FcLWs/1dfUSSIlbG/RLrlUOU67ZSza7Gc= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45SFFKbN021472 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Jun 2024 10:15:20 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 28 Jun 2024 10:15:20 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 28 Jun 2024 10:15:20 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJlV087911; Fri, 28 Jun 2024 10:15:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 2/7] arm64: dts: ti: k3-j7200: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:13 -0500 Message-ID: <20240628151518.40100-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fccaabfb13482..5097d192c2b20 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -164,12 +164,16 @@ mcu_timer9: timer@40490000 { ti,timer-pwm; }; =20 - mcu_conf: syscon@40f00000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x00 0x40f00000 0x00 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; - ranges =3D <0x00 0x00 0x40f00000 0x20000>; + ranges =3D <0x0 0x0 0x40f00000 0x20000>; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; =20 phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; @@ -420,7 +424,7 @@ cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2