From nobody Sun Dec 14 12:11:02 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A4281CE08A; Fri, 28 Jun 2024 15:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587740; cv=none; b=nEy+qfUg5/b6O9kIJ8FjckJWgSf8GVVl1yBoF5bnyfuOJrHcDD8IX+37f8e2imEd2ROtadKVqDso2PIeV/TrkNUqhqb9cy0RMV/3tqwdayoq3bTVZQkNfv9oDFVs5nm8TegLydNUKuOrUJsibRYX159pHepoP7/QzBauCU2AE4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587740; c=relaxed/simple; bh=oHVv0/SCCVI3F7WFGHyeGNhEBrtKYoQxxA0t6HyZu60=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KmkTlbg33GLBtxb+J6rDNEN+fPCdlQTAsujLj6f+bWOR5jTc5UO2vfcfbYEepsRwaQbV8rVjNnN07U7/qSYNJ5pzoGOTygjvZBabMpGluinLyo61m1pJI7RfipgQDMdGe+hJY9ZdOtl7ykzUhRbRU3nlFbdY4VexjBaQW2LSLtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=BNDyzQ3x; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BNDyzQ3x" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFK5M106479; Fri, 28 Jun 2024 10:15:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719587720; bh=bX/INQxCOvUYPBjtz6cmPeM5ZIJqmCkwp95Q9pPdEYo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BNDyzQ3xSp6HksXShakkm93iMEKI26qr8i+e1YSXz31X32tL4wvIhbgn7Qzc0xgig iCwf+Eh9ya3GklmKrtjyoK34v4B1v8a7XJgiy1n8Urev/VtNvQDhKxPIG+WDrEZ8gH z7cHEaTVragtgACxTo/2Jdu94H+qRu3P5laXFOTY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45SFFK8o071748 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 28 Jun 2024 10:15:20 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 28 Jun 2024 10:15:20 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 28 Jun 2024 10:15:20 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJlU087911; Fri, 28 Jun 2024 10:15:19 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 1/7] arm64: dts: ti: k3-am65: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:12 -0500 Message-ID: <20240628151518.40100-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 8feab93176447..43c6118d2bf0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -6,13 +6,17 @@ */ =20 &cbass_mcu { - mcu_conf: scm-conf@40f00000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x0 0x0 0x40f00000 0x20000>; =20 + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4040 0x4>; @@ -358,7 +362,7 @@ cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F951CE0B2; Fri, 28 Jun 2024 15:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; cv=none; b=lrGWBStZ7wg8OtTppKVLf0keFocOgoRjq/xd3U99GHrIOB+4zuzlBxz3JUO1iphTqWfZ8IRkoD10ncLjFJdFeQwgP9CjEx+YbegJQrJaboIcYd+DKlXnxhPVf4HY6QhyjwQyVqTFuexTRzb13rmiR99UQZNYCJuf/1LGxv18t0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; c=relaxed/simple; bh=SS4l0vhuF8ANyvYivJMIGd8T3vZtD+Iy2iMKpSpG60Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Fri, 28 Jun 2024 10:15:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 2/7] arm64: dts: ti: k3-j7200: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:13 -0500 Message-ID: <20240628151518.40100-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fccaabfb13482..5097d192c2b20 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -164,12 +164,16 @@ mcu_timer9: timer@40490000 { ti,timer-pwm; }; =20 - mcu_conf: syscon@40f00000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x00 0x40f00000 0x00 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; - ranges =3D <0x00 0x00 0x40f00000 0x20000>; + ranges =3D <0x0 0x0 0x40f00000 0x20000>; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; =20 phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; @@ -420,7 +424,7 @@ cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9F931CE080; Fri, 28 Jun 2024 15:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587739; cv=none; b=FmC3ltUaHS+Bfs/ipPqub+ga+E0seXg64dMQSj7Q0UmtoIRMr2yLKFkyzG9d+RfzVE4D5+FBxWgfgJFeY7q+k1k+RIwRo94JmHLwFs6Nz0GePGxOds7Xj3CWW2WfktYUsu2J0OBaG3EWwy+NFK/2oXrUR+Ni6VR+aiey6o/rteQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587739; c=relaxed/simple; bh=JjXBjmoqRLrivIjxwcsq2rz3H88BzVco+4kVndO5Qz8=; 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Fri, 28 Jun 2024 10:15:20 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJlW087911; Fri, 28 Jun 2024 10:15:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 3/7] arm64: dts: ti: k3-j721e: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:14 -0500 Message-ID: <20240628151518.40100-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 9349ae07c046e..6b6ef6a306142 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -34,13 +34,17 @@ k3_reset: reset-controller { }; }; =20 - mcu_conf: syscon@40f00000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x0 0x0 0x40f00000 0x20000>; =20 + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4040 0x4>; @@ -546,7 +550,7 @@ cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92F861CE0AE; Fri, 28 Jun 2024 15:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; cv=none; b=Tes4c1Aztser3qaUrvOORpDEL1j6xqU0z4fpciGc9qgm+rQld1rLeq5hUaEoBnWYaqBONfWqXdArS88qJ/FP6SVGlspsc8tmvRZCmsWiDUzDuR9xfEkok87llR5koCud+youePnJU2lqebn4pJxvdGPplJplHKAHTgc0sgRNmgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587742; c=relaxed/simple; bh=ezL8bk3Jk35BI/dergt8ULF2Jomyu78P8+/sCPXhFN8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Fri, 28 Jun 2024 10:15:20 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 4/7] arm64: dts: ti: k3-j721s2: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:15 -0500 Message-ID: <20240628151518.40100-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5ccb04c7c4624..8feb42c89e476 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -139,13 +139,17 @@ wkup_gpio_intr: interrupt-controller@42200000 { ti,interrupt-ranges =3D <16 960 16>; }; =20 - mcu_conf: syscon@40f00000 { - compatible =3D "syscon", "simple-mfd"; - reg =3D <0x0 0x40f00000 0x0 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x0 0x0 0x40f00000 0x20000>; =20 + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; + phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4040 0x4>; @@ -544,7 +548,7 @@ cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 826341CE087; Fri, 28 Jun 2024 15:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587740; cv=none; b=Zlxfb5nvVPLAdEhZxNSmKuZ2bV7VN52igK86ROC8cbmgUrOCcOAfL4w6Lsw7jMia7LniL60ZGpFxaQqUvvhLfF8JZtcrJhR2d6LnZ555nA8shkc5VbmLDCS4ZmXkqzFSAxC/TllT5V+VeoMRmLulD2XC9w2iWpxjc6axBt7IBd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587740; c=relaxed/simple; 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Fri, 28 Jun 2024 10:15:21 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJlY087911; Fri, 28 Jun 2024 10:15:21 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 5/7] arm64: dts: ti: k3-j784s4: Add cpsw-mac-efuse node to mcu_conf Date: Fri, 28 Jun 2024 10:15:16 -0500 Message-ID: <20240628151518.40100-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The MCU system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 2e18d91ae92f8..f3a6ed1c979d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -145,12 +145,16 @@ mcu_timerio_output: pinctrl@40f04280 { status =3D "reserved"; }; =20 - mcu_conf: syscon@40f00000 { - compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg =3D <0x00 0x40f00000 0x00 0x20000>; + mcu_conf: bus@40f00000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; - ranges =3D <0x00 0x00 0x40f00000 0x20000>; + ranges =3D <0x0 0x0 0x40f00000 0x20000>; + + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; =20 phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; @@ -553,7 +557,7 @@ mcu_cpsw_port1: port@1 { reg =3D <1>; ti,mac-only; label =3D "port1"; - ti,syscon-efuse =3D <&mcu_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; }; }; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 826971CE088; Fri, 28 Jun 2024 15:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587741; cv=none; b=ruQxvv7ND4nWsGcqfxPVsYDDXfsrh5OFstI8h/d3pHOw2aY3yK9b2LAPAipcyzSrgyvP9SPbiKPVX2DcfUYoiiZuXEdu2GBh4tVPGi7fMxZdTSkrgrswFRS6DiD7OKVeQ4kUgtoHYeqEI18Vr75xG1KXQ1o0MuP9u99tXir+LmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587741; c=relaxed/simple; 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Fri, 28 Jun 2024 10:15:22 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJlZ087911; Fri, 28 Jun 2024 10:15:21 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 6/7] arm64: dts: ti: k3-am62a: Add cpsw-mac-efuse node to wkup_conf Date: Fri, 28 Jun 2024 10:15:17 -0500 Message-ID: <20240628151518.40100-7-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The WKUP system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. This makes it so the system controller memory area does not need to be one big syscon area, describe this bus address area as the simple-bus it is. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index ce4a2f1056300..6b81abec8a145 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -713,7 +713,7 @@ cpsw_port1: port@1 { label =3D "port1"; phys =3D <&phy_gmii_sel 1>; mac-address =3D [00 00 00 00 00 00]; - ti,syscon-efuse =3D <&wkup_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; }; =20 cpsw_port2: port@2 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 5c5aca4bb9258..f5ac101a04dfa 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -6,9 +6,8 @@ */ =20 &cbass_wakeup { - wkup_conf: syscon@43000000 { - compatible =3D "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg =3D <0x00 0x43000000 0x00 0x20000>; + wkup_conf: bus@43000000 { + compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x00 0x00 0x43000000 0x20000>; @@ -18,6 +17,11 @@ chipid: chipid@14 { reg =3D <0x14 0x4>; }; =20 + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; + usb0_phy_ctrl: syscon@4008 { compatible =3D "ti,am62-usb-phy-ctrl", "syscon"; reg =3D <0x4008 0x4>; --=20 2.39.2 From nobody Sun Dec 14 12:11:02 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A33B21C9ED9; Fri, 28 Jun 2024 15:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719587735; cv=none; b=AssY1crwbftnlKHQjR6chC1LSJbCtAbvcOi/5fdePzrOwhaKVoEEBoMoQcL0ekP2zxqOe6RolPJ6aGhZnIBQ84kRMkQhIEzDZeaSY8BtlyAUs1vyWAPfAW5ygn05OtFOtZiN+WiSFTj3lnIwny9uqqRcYceplsAr4/n0cVP4BxY= ARC-Message-Signature: i=1; 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Fri, 28 Jun 2024 10:15:22 -0500 Received: from lelvsmtp5.itg.ti.com ([10.249.42.149]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45SFFJla087911; Fri, 28 Jun 2024 10:15:22 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jan Kiszka CC: , , , Andrew Davis Subject: [PATCH 7/7] arm64: dts: ti: k3-am62: Add cpsw-mac-efuse node to wkup_conf Date: Fri, 28 Jun 2024 10:15:18 -0500 Message-ID: <20240628151518.40100-8-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628151518.40100-1-afd@ti.com> References: <20240628151518.40100-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The WKUP system controller address region contains an eFuse block with MAC addresses to be used by the Ethernet controller. The property =E2=80=9Cti,syscon-efuse=E2=80=9D contains a phandle to a syscon region and= an offset into this region where the MAC addresses can be found. Currently "ti,syscon-efuse" points to the entire system controller address space node with an offset to the eFuse IP address. Instead add a cpsw-mac-efuse node to describe the exact eFuse area. Then point the Ethernet controller directly to this region, no offset needed. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 0f2722c4bcc32..9662b20d59dae 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -739,7 +739,7 @@ cpsw_port1: port@1 { label =3D "port1"; phys =3D <&phy_gmii_sel 1>; mac-address =3D [00 00 00 00 00 00]; - ti,syscon-efuse =3D <&wkup_conf 0x200>; + ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; }; =20 cpsw_port2: port@2 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 66ddf2dc51afa..e0afafd532a5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -22,6 +22,11 @@ chipid: chipid@14 { reg =3D <0x14 0x4>; }; =20 + cpsw_mac_syscon: ethernet-mac-syscon@200 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x200 0x8>; + }; + usb0_phy_ctrl: syscon@4008 { compatible =3D "ti,am62-usb-phy-ctrl", "syscon"; reg =3D <0x4008 0x4>; --=20 2.39.2