From nobody Sun Dec 14 12:14:21 2025 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B76A2155CAE; Fri, 28 Jun 2024 14:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583465; cv=none; b=hpGVdHrXGa+8jfV6rBfaW6vzwMTLcXBnMMRzCS4kQlBYUjE8Rqk/Ia+jRAUDiLjmoRRxJWBDWbp7EsAKKkkaFEV0ZY5xMnO6cEb4m1UGqktAtXFwKh1V2G1mSA1oMcg1QFPdPb9OS3Wiw4M24ertyhDGjEr/YtLNhldrzvLdZnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583465; c=relaxed/simple; bh=aOFbB1UYssZ8v5LPVxLTA42lqnXbomgRjmrdBQDwgdA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iEIYCWPEUK/pHtCnOaRdVMluVe5Iy6eRTgLN3kw7ON8snalm4OAovQ/s70U0tDvU31IX9dA33yFaPNdJalE1PYt2JcUEMCsO3TcYrgFtbyM6CRcYnpbpI+mDe95iKpp7TT8naFKYMA/S2oQgUhJ9DX/3X4KsyeoKaD7+2V2kOoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4W9ccN55gSzMQL9; Fri, 28 Jun 2024 14:04:04 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Erez Geva Subject: [PATCH 1/4] Add generic functions for accessing the SPI-NOR chip. Date: Fri, 28 Jun 2024 16:03:25 +0200 Message-Id: <20240628140328.279792-2-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628140328.279792-1-erezgeva@nwtime.org> References: <20240628140328.279792-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Functions: - Send a opcode - Read a register - Write a register Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/core.c | 130 +++++++++++++++++++++++++++---------- drivers/mtd/spi-nor/core.h | 27 +------- 2 files changed, 99 insertions(+), 58 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 028514c6996f..0f267da339a4 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -354,53 +354,134 @@ int spi_nor_write_any_volatile_reg(struct spi_nor *n= or, struct spi_mem_op *op, } =20 /** - * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. + * _nor_send_cmd() - Send instruction without address or data to the chip. * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send * * Return: 0 on success, -errno otherwise. */ -int spi_nor_write_enable(struct spi_nor *nor) +static inline int _nor_send_cmd(struct spi_nor *nor, u8 opcode) { int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WREN_OP; + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, - NULL, 0); + ret =3D spi_nor_controller_ops_write_reg(nor, opcode, NULL, 0); } =20 - if (ret) - dev_dbg(nor->dev, "error %d on Write Enable\n", ret); + return ret; +} + +/** + * spi_nor_send_cmd() - Send instruction without address or data to the ch= ip. + * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_send_cmd(struct spi_nor *nor, u8 opcode) +{ + int ret; + + ret =3D _nor_send_cmd(nor, opcode); =20 return ret; } =20 /** - * spi_nor_write_disable() - Send Write Disable instruction to the chip. + * spi_nor_read_reg() - Send instruction without address or data to the ch= ip. * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * @len: register value length * * Return: 0 on success, -errno otherwise. */ -int spi_nor_write_disable(struct spi_nor *nor) +int spi_nor_read_reg(struct spi_nor *nor, u8 opcode, size_t len) { int ret; =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_WRDI_OP; + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(len, nor->bouncebuf, 0)); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, - NULL, 0); + ret =3D spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len= ); } =20 + return ret; +} + +/* + * spi_nor_write_reg() - Send instruction without address or data to the c= hip. + * @nor: pointer to 'struct spi_nor'. + * @opcode: Command to send + * @len: register value length + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, size_t len) +{ + int ret; + + if (nor->spimem) { + struct spi_mem_op op =3D SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(len, nor->bouncebuf, 0)); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + ret =3D spi_mem_exec_op(nor->spimem, &op); + } else { + ret =3D spi_nor_controller_ops_write_reg(nor, opcode, nor->bouncebuf, le= n); + } + + return ret; +} + +/** + * spi_nor_write_enable() - Set write enable latch with Write Enable comma= nd. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_enable(struct spi_nor *nor) +{ + int ret; + + ret =3D _nor_send_cmd(nor, SPINOR_OP_WREN); + + if (ret) + dev_dbg(nor->dev, "error %d on Write Enable\n", ret); + + return ret; +} + +/** + * spi_nor_write_disable() - Send Write Disable instruction to the chip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_write_disable(struct spi_nor *nor) +{ + int ret; + + ret =3D _nor_send_cmd(nor, SPINOR_OP_WRDI); + if (ret) dev_dbg(nor->dev, "error %d on Write Disable\n", ret); =20 @@ -521,18 +602,8 @@ int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_n= or *nor, bool enable) { int ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_EN4B_EX4B_OP(enable); - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, - enable ? SPINOR_OP_EN4B : - SPINOR_OP_EX4B, - NULL, 0); - } + ret =3D _nor_send_cmd(nor, enable ? SPINOR_OP_EN4B : + SPINOR_OP_EX4B); =20 if (ret) dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); @@ -765,16 +836,7 @@ int spi_nor_global_block_unlock(struct spi_nor *nor) if (ret) return ret; =20 - if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_GBULK_OP; - - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); - - ret =3D spi_mem_exec_op(nor->spimem, &op); - } else { - ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, - NULL, 0); - } + ret =3D _nor_send_cmd(nor, SPINOR_OP_GBULK); =20 if (ret) { dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 442786685515..df456a713d92 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -25,18 +25,6 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(len, buf, 0)) =20 -#define SPI_NOR_WREN_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - -#define SPI_NOR_WRDI_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_RDSR_OP(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \ SPI_MEM_OP_NO_ADDR, \ @@ -67,24 +55,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_IN(1, buf, 0)) =20 -#define SPI_NOR_EN4B_EX4B_OP(enable) \ - SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_BRWR_OP(buf) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(1, buf, 0)) =20 -#define SPI_NOR_GBULK_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), \ - SPI_MEM_OP_NO_ADDR, \ - SPI_MEM_OP_NO_DUMMY, \ - SPI_MEM_OP_NO_DATA) - #define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \ @@ -611,6 +587,9 @@ extern const struct attribute_group *spi_nor_sysfs_grou= ps[]; void spi_nor_spimem_setup_op(const struct spi_nor *nor, struct spi_mem_op *op, const enum spi_nor_protocol proto); +int spi_nor_send_cmd(struct spi_nor *nor, u8 opcode); +int spi_nor_read_reg(struct spi_nor *nor, u8 opcode, size_t len); +int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, size_t len); int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); --=20 2.39.2 From nobody Sun Dec 14 12:14:21 2025 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 04ABA1BE25E; Fri, 28 Jun 2024 14:04:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583468; cv=none; b=fHEJXD7BGImLpe6GccBIMx+LXVLz3SRareLMcFIlDVYabfvwvAsfcPTgComvnvzKs4o+EepZu7uaWoc0iu0VKdvI5reSd03zxphaneRW54u8u36MOa5VwJQXG3XOWBRZUTO8DFl3BynukrifEhUJx6xuC+oDdjTNNWPFDP2qSY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583468; c=relaxed/simple; bh=BKnp5qBwbxDEcoRm80oPnb70IF4TvTnv8dTWdnMJYCw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RTlAODw3iydG7ervtovtS3eJHa4o8WAVWV2bOO+rQ2ne7qMlN5++T7BE1rmUb65J9HCghVcUuC5E16gSKCs/3GsKT7gpMFB2X5jTY0B28FSyVnByHP19KObyQ6oaMkG8EYfLmWkvzmNcf9qrLE633FPWkt+QzYqPZUwqi0NvSAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4W9ccR4gSBzMQLJ; Fri, 28 Jun 2024 14:04:07 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Erez Geva Subject: [PATCH 2/4] Add support for SPI-NOR Macronix OTP. Date: Fri, 28 Jun 2024 16:03:26 +0200 Message-Id: <20240628140328.279792-3-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628140328.279792-1-erezgeva@nwtime.org> References: <20240628140328.279792-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Macronix SPI-NOR support OTP. Add callbacks to read, write and lock the OTP. Notice Macronix OTP do not support erase. Every bit written with '0', can not be changed further. Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/macronix.c | 185 +++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 10 ++ 2 files changed, 195 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index ea6be95e75a5..f210231468a6 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,180 @@ =20 #include "core.h" =20 +/** + * macronix_nor_otp_enter() - Send Enter Secured OTP instruction to the ch= ip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_enter(struct spi_nor *nor) +{ + int error; + + error =3D spi_nor_send_cmd(nor, SPINOR_OP_ENSO); + + if (error) + dev_dbg(nor->dev, "error %d on Macronix Enter Secured OTP\n", error); + + return error; +} + +/** + * macronix_nor_otp_exit() - Send Exit Secured OTP instruction to the chip. + * @nor: pointer to 'struct spi_nor'. + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_exit(struct spi_nor *nor) +{ + int error; + + error =3D spi_nor_send_cmd(nor, SPINOR_OP_EXSO); + + if (error) + dev_dbg(nor->dev, "error %d on Macronix Enter Secured OTP\n", error); + + return error; +} + +/** + * macronix_nor_otp_read() - read security register + * @nor: pointer to 'struct spi_nor' + * @addr: offset to read from + * @len: number of bytes to read + * @buf: pointer to dst buffer + * + * Return: number of bytes read successfully, -errno otherwise + */ +static int macronix_nor_otp_read(struct spi_nor *nor, loff_t addr, size_t = len, u8 *buf) +{ + int ret, error; + + error =3D macronix_nor_otp_enter(nor); + if (error) + return error; + + ret =3D spi_nor_read_data(nor, addr, len, buf); + + error =3D macronix_nor_otp_exit(nor); + + if (ret < 0) + dev_dbg(nor->dev, "error %d on Macronix read OTP data\n", ret); + else if (error) + return error; + + return ret; +} + +/** + * macronix_nor_otp_write() - write security register + * @nor: pointer to 'struct spi_nor' + * @addr: offset to write to + * @len: number of bytes to write + * @buf: pointer to src buffer + * + * Return: number of bytes written successfully, -errno otherwise + */ +static int macronix_nor_otp_write(struct spi_nor *nor, loff_t addr, size_t= len, const u8 *buf) +{ + int error, ret =3D 0; + + error =3D macronix_nor_otp_enter(nor); + if (error) + return error; + + error =3D spi_nor_write_enable(nor); + if (error) + goto otp_write_err; + + ret =3D spi_nor_write_data(nor, addr, len, buf); + if (ret < 0) { + dev_dbg(nor->dev, "error %d on Macronix write OTP data\n", ret); + goto otp_write_err; + } + + error =3D spi_nor_wait_till_ready(nor); + if (error) + dev_dbg(nor->dev, "error %d on Macronix waiting write OTP finish\n", err= or); + +otp_write_err: + + error =3D macronix_nor_otp_exit(nor); + + return ret; +} + +/** + * macronix_nor_otp_lock() - lock the OTP region + * @nor: pointer to 'struct spi_nor' + * @region: OTP region + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_lock(struct spi_nor *nor, unsigned int region) +{ + int error; + u8 *rdscur =3D nor->bouncebuf; + + error =3D spi_nor_read_reg(nor, SPINOR_OP_RDSCUR, 1); + if (error) { + dev_dbg(nor->dev, "error %d on read security register\n", error); + return error; + } + + switch (region) { + case 0: /* Lock 1st 4K-bit region */ + if (rdscur[0] & SEC_REG_LDSO) + return 0; /* Already locked */ + rdscur[0] |=3D SEC_REG_LDSO; + break; + case 1: /* Lock 2nd 4K-bit region */ + if (rdscur[0] & SEC_REG_LDS1) + return 0; /* Already locked */ + rdscur[0] |=3D SEC_REG_LDS1; + break; + default: + return 0; /* Unknown region */ + } + + error =3D spi_nor_write_reg(nor, SPINOR_OP_WRSCUR, 1); + if (error) + dev_dbg(nor->dev, "error %d on update security register\n", error); + + return error; +} + +/** + * macronix_nor_otp_is_locked() - get the OTP region lock status + * @nor: pointer to 'struct spi_nor' + * @region: OTP region + * + * Return: 0 on success, -errno otherwise. + */ +static int macronix_nor_otp_is_locked(struct spi_nor *nor, unsigned int re= gion) +{ + int ret; + u8 *rdscur =3D nor->bouncebuf; + + ret =3D spi_nor_read_reg(nor, SPINOR_OP_RDSCUR, 1); + if (ret) { + dev_dbg(nor->dev, "error %d on read security register\n", ret); + return ret; + } + + switch (region) { + case 0: /* 1st 4K-bit region */ + ret =3D (rdscur[0] & SEC_REG_LDSO) > 0; + break; + case 1: /* 2nd 4K-bit region */ + ret =3D (rdscur[0] & SEC_REG_LDS1) > 0; + break; + default: /* Unknown region */ + break; + } + return ret; +} + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -190,8 +364,19 @@ static void macronix_nor_default_init(struct spi_nor *= nor) nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; } =20 +static const struct spi_nor_otp_ops macronix_nor_otp_ops =3D { + .read =3D macronix_nor_otp_read, + .write =3D macronix_nor_otp_write, + /* .erase =3D Macronix OTP do not support erase, */ + .lock =3D macronix_nor_otp_lock, + .is_locked =3D macronix_nor_otp_is_locked, +}; + static int macronix_nor_late_init(struct spi_nor *nor) { + if (nor->params->otp.org->n_regions) + nor->params->otp.ops =3D ¯onix_nor_otp_ops; + if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; =20 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index cdcfe0fd2e7d..f5965f90f51e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -81,6 +81,16 @@ #define SPINOR_OP_BP 0x02 /* Byte program */ #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ =20 +/* Used by Macronix OTP. */ +#define SPINOR_OP_RDSCUR 0x2b /* read security register */ +#define SPINOR_OP_WRSCUR 0x2f /* write security register */ +#define SPINOR_OP_ENSO 0xb1 /* enter secured OTP */ +#define SPINOR_OP_EXSO 0xc1 /* exit secured OTP */ + +/* Security register */ +#define SEC_REG_LDSO BIT(1) /* lock-down bit 1st 4K-bit */ +#define SEC_REG_LDS1 BIT(0) /* lock-down bit 2nd 4K-bit */ + /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ --=20 2.39.2 From nobody Sun Dec 14 12:14:21 2025 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 46FF21BF320; Fri, 28 Jun 2024 14:04:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583471; cv=none; b=A8MB1IOx7U//xBdjPXnT8LE/z4srYwpoMb5iW1bBlmb5rfZC0iF+GCi7LwHHiACOMjfdbokj/a+nGZqvnE5doZMxsdMXQQEPAsZ7iKU5caW3q8TRn9t2tAlpGtX61vt0t4vZXnwNxQJjpC6LvweJ+wMRRGzDJqnnVQzUEgNtK4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583471; c=relaxed/simple; bh=MdgNgRn8q3VbxMI6SqzSPsegSxcWvQzL7F9fijcslNs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gn5kINfvhm56OK0T6WgqdB39pQxKLDL63g62ZuWeENXHgNBUJkG1/nvlCU1dXwWIS75YMiI0vhzF0sOpW8FIT7WCbhWXOwhfci6nzzwgMyjPvjRFiyfawGo1OgoWeEcFJ04WLiiAVgD9eRjbdqN5vuIZ9E6bukzHad7nilXafds= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4W9ccV3YWKzMQLS; Fri, 28 Jun 2024 14:04:10 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Erez Geva Subject: [PATCH 3/4] dt-bindings: mtd: macronix,mx25l12833f: add SPI-NOR chip Date: Fri, 28 Jun 2024 16:03:27 +0200 Message-Id: <20240628140328.279792-4-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628140328.279792-1-erezgeva@nwtime.org> References: <20240628140328.279792-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva Add Macronix SPI-NOR mx25l12833f. Signed-off-by: Erez Geva Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 6e3afb42926e..625a618a7992 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -22,7 +22,7 @@ properties: n25q(32b|064|128a11|128a13|256a|512a|164k)))|\ atmel,at25df(321a|641|081a)|\ everspin,mr25h(10|40|128|256)|\ - (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)= |\ + (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|12833f|= 25635e)|\ (mxicy|macronix),mx25u(4033|4035)|\ (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\ (sst|microchip),sst25vf(016b|032b|040b)|\ --=20 2.39.2 From nobody Sun Dec 14 12:14:21 2025 Received: from chessie.everett.org (chessie.fmt1.pfcs.com [66.220.13.234]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC2F71BE843; Fri, 28 Jun 2024 14:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=66.220.13.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583473; cv=none; b=gmYandhQokEfpz/iDTXWITmybLH/wpkkPLArFxc6U7UOPii79D6Tl+O7nF5eb1ex/1KFfNz4MtrdRmOk78iW22BeeR50bslJoPppGy7otJ1R+iA+a3IEHj3yC6Lhm6jYvo2R35usav0v6nztKVHgvMTDEzT1l7rxHCFUhV9X8jo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719583473; c=relaxed/simple; bh=majJpbIEZ5L9h6UbAm35Av5QMsq9MbUrx/XGexo7JsQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TpNR/7Y8xHJmxKZ+WbVGBt+Lzxa3L4Hzimq/5goYxXls8EZtceVLHJjMS9HDjB6ZFeikTzYkmH8GLmA/EsgEHO/2al5PhL/m61kFEZNvmsx7rLri4IYZ2F/znpNZ2UFH3Gn0bc0VS4hmbId+U4zp3AZRnxvviBxCyGU28Ii9ORI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org; spf=pass smtp.mailfrom=nwtime.org; arc=none smtp.client-ip=66.220.13.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=nwtime.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nwtime.org Received: from localhost.localdomain (unknown [31.16.248.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by chessie.everett.org (Postfix) with ESMTPSA id 4W9ccY3L1GzMQLT; Fri, 28 Jun 2024 14:04:13 +0000 (UTC) From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Erez Geva Subject: [PATCH 4/4] Add Macronix SPI-NOR mx25l12833f with OTP. Date: Fri, 28 Jun 2024 16:03:28 +0200 Message-Id: <20240628140328.279792-5-erezgeva@nwtime.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240628140328.279792-1-erezgeva@nwtime.org> References: <20240628140328.279792-1-erezgeva@nwtime.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Erez Geva mx25l12833f uses the same JEDEC-id as mx25l12805d. The 2 chips have the same flash size. mx25l12833f support SFDP and have a bigger symmetric OTP. Signed-off-by: Erez Geva --- drivers/mtd/spi-nor/core.c | 1 + drivers/mtd/spi-nor/macronix.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0f267da339a4..f2a46add2695 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3799,6 +3799,7 @@ static const struct spi_device_id spi_nor_dev_ids[] = =3D { */ {"at25df321a"}, {"at25df641"}, {"at26df081a"}, {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, + {"mx25l12833f"}, /* uses the same jedec ID of mx25l12805d */ {"mx25l25635e"},{"mx66l51235l"}, {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index f210231468a6..fba3fc8e0d49 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -247,6 +247,11 @@ static const struct flash_info macronix_nor_parts[] = =3D { .size =3D SZ_16M, .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, .no_sfdp_flags =3D SECT_4K, + }, { /* Yes, Same JEDEC-id as mx25l12805d */ + .id =3D SNOR_ID(0xc2, 0x20, 0x18), + .name =3D "mx25l12833f", + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP, + .otp =3D SNOR_OTP(512, 2, 0x000, 0x200), }, { .id =3D SNOR_ID(0xc2, 0x20, 0x19), .name =3D "mx25l25635e", --=20 2.39.2