From nobody Sun Dec 14 19:28:52 2025 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1BD41BE87E; Fri, 28 Jun 2024 13:35:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719581748; cv=none; b=t5hkga+LVtbvyXxcRFnfLP4AjwfxKY9wQlOg6xDLjq2SS4O/jBNEbUs97VHFKaPAViDLTcXuPbyKJbGnZSWwLqWODZtTXCIhScMMvU8uWowFm8N75TJlffS1/csspJUdkt18U1jSWhA1jshSrEyHJYDJWy0cP+QjA9s4RlBK+oQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719581748; c=relaxed/simple; bh=XUJRq5NoJhFWDbGeLYQUboD1oN3kDGU4Lf5qx+YkPVo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eM9+qlFyV6C29g+yGUeF8R8IKaOs7wBDVzl4EZURV/UZaEJFE4EdKBY9L7pbvAl3fX9wcySdGQbsLfDETqQ7gZRKOx/ffJJ6qG7IJCIAfmValzqN/F+xskGY6BAVU63Ty1+uYByYIbidodLPo5uWyeCxniR01Zmz1OV99dH2Sfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=iOrX6BU1; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="iOrX6BU1" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45SA18BX027520; Fri, 28 Jun 2024 06:35:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=pfpt0220; bh=UZ3aGUP0Np8ZeitrBs/MDNkUA NRDUJBqYnVnZhqdWsk=; b=iOrX6BU1NrOoxTHIuoqJ/vF/t5E1z2xhazBtal5hQ CTg+H9HN3RrR5Ma4xo9WgGxTtLoxwdaJnfMk5xx5F5iV+jY7lMeKtMWOexitamP1 XpHh4PHlZNJB5KR2jt+enAlHdZp0LQtY1/7CezfAiY9dSmOoAcqTXjEQEi75GUHl s1E3TIW5ZHQd/tvbRa9izpVDXNFn4raTn8tJpIZuOIsvtF7OdW6Ah6pmxbUpTgOj N7dgNvb2oyegXUfBMCUL+jwq9KTLvsYujsq0ZCNPRZTlrXVaV9XnoiYB7gdO9ZaG mOrixXOao0J4+MjdBHeTl2cOgFpKRL+s4K1G7VNF/ywJQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 401c8hubm9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 06:35:26 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 28 Jun 2024 06:35:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 28 Jun 2024 06:35:25 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id F2A273F704E; Fri, 28 Jun 2024 06:35:21 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , Subject: [net-next PATCH v7 01/10] octeontx2-pf: Refactoring RVU driver Date: Fri, 28 Jun 2024 19:05:08 +0530 Message-ID: <20240628133517.8591-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628133517.8591-1-gakula@marvell.com> References: <20240628133517.8591-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: gEEb86X60kvrZ3ItSqtaCAYTfAHAvow- X-Proofpoint-ORIG-GUID: gEEb86X60kvrZ3ItSqtaCAYTfAHAvow- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_09,2024-06-28_01,2024-05-17_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactoring and export list of shared functions such that they can be used by both RVU NIC and representor driver. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../ethernet/marvell/octeontx2/af/common.h | 2 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 2 + .../net/ethernet/marvell/octeontx2/af/npc.h | 1 + .../net/ethernet/marvell/octeontx2/af/rvu.c | 11 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 1 + .../marvell/octeontx2/af/rvu_debugfs.c | 27 -- .../ethernet/marvell/octeontx2/af/rvu_nix.c | 47 ++-- .../marvell/octeontx2/af/rvu_npc_fs.c | 5 + .../ethernet/marvell/octeontx2/af/rvu_reg.h | 4 + .../marvell/octeontx2/af/rvu_struct.h | 26 ++ .../marvell/octeontx2/af/rvu_switch.c | 2 +- .../marvell/octeontx2/nic/otx2_common.c | 6 +- .../marvell/octeontx2/nic/otx2_common.h | 43 ++-- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 240 +++++++++++------- .../marvell/octeontx2/nic/otx2_txrx.c | 17 +- .../marvell/octeontx2/nic/otx2_txrx.h | 3 +- .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 7 +- 17 files changed, 266 insertions(+), 178 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/n= et/ethernet/marvell/octeontx2/af/common.h index 2436c1ff9ba4..46fbc8f2dce8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -155,9 +155,11 @@ enum nix_scheduler { /* Min/Max packet sizes, excluding FCS */ #define NIC_HW_MIN_FRS 40 #define NIC_HW_MAX_FRS 9212 +#define SDP_HW_MIN_FRS 16 #define SDP_HW_MAX_FRS 65535 #define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */ #define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */ +#define SDP_LINK_CREDIT 0x320202 =20 /* NIX RX action operation*/ #define NIX_RX_ACTIONOP_DROP (0x0ull) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 4a77f6fe2622..e6d7d6e862c0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -78,6 +78,7 @@ struct otx2_mbox { struct mbox_hdr { u64 msg_size; /* Total msgs size embedded */ u16 num_msgs; /* No of msgs embedded */ + u16 sig; }; =20 /* Header which precedes every msg and is also part of it */ @@ -1562,6 +1563,7 @@ struct flow_msg { u8 icmp_type; u8 icmp_code; __be16 tcp_flags; + u16 sq_id; }; =20 struct npc_install_flow_req { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/= ethernet/marvell/octeontx2/af/npc.h index d883157393ea..a6533a9b8aa1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h @@ -245,6 +245,7 @@ enum key_fields { NPC_VLAN_TAG2, /* inner vlan tci for double tagged frame */ NPC_VLAN_TAG3, + NPC_SQ_ID, /* other header fields programmed to extract but not of our interest */ NPC_UNKNOWN, NPC_KEY_FIELDS_MAX, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index ff78251f92d4..fc0d085cfad1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2151,6 +2151,16 @@ static void __rvu_mbox_handler(struct rvu_work *mwor= k, int type, bool poll) =20 offset =3D mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); =20 + if (req_hdr->sig) { + rvu_write64(rvu, BLKADDR_NIX0, RVU_AF_BAR2_SEL, + RVU_AF_BAR2_PFID); + rvu_write64(rvu, BLKADDR_NIX0, + AF_BAR2_ALIASX(0, NIX_LF_CINTX_INT_W1S(devid)), + 0x1); + usleep_range(1000, 2000); + goto done; + } + for (id =3D 0; id < mw->mbox_wrk[devid].num_msgs; id++) { msg =3D mdev->mbase + offset; =20 @@ -2184,6 +2194,7 @@ static void __rvu_mbox_handler(struct rvu_work *mwork= , int type, bool poll) err, otx2_mbox_id2name(msg->id), msg->id, devid); } +done: mw->mbox_wrk[devid].num_msgs =3D 0; =20 if (poll) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 3063a84a45ef..30efa5607c58 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -1016,6 +1016,7 @@ int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int= blkaddr); void rvu_switch_enable(struct rvu *rvu); void rvu_switch_disable(struct rvu *rvu); void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); +void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); =20 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, u64 pkind, u8 var_len_off, u8 var_len_off_mask, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 4a4ef5bd9e0b..e661f83b188b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -45,33 +45,6 @@ enum { CGX_STAT18, }; =20 -/* NIX TX stats */ -enum nix_stat_lf_tx { - TX_UCAST =3D 0x0, - TX_BCAST =3D 0x1, - TX_MCAST =3D 0x2, - TX_DROP =3D 0x3, - TX_OCTS =3D 0x4, - TX_STATS_ENUM_LAST, -}; - -/* NIX RX stats */ -enum nix_stat_lf_rx { - RX_OCTS =3D 0x0, - RX_UCAST =3D 0x1, - RX_BCAST =3D 0x2, - RX_MCAST =3D 0x3, - RX_DROP =3D 0x4, - RX_DROP_OCTS =3D 0x5, - RX_FCS =3D 0x6, - RX_ERR =3D 0x7, - RX_DRP_BCAST =3D 0x8, - RX_DRP_MCAST =3D 0x9, - RX_DRP_L3BCAST =3D 0xa, - RX_DRP_L3MCAST =3D 0xb, - RX_STATS_ENUM_LAST, -}; - static char *cgx_rx_stats_fields[] =3D { [CGX_STAT0] =3D "Received packets", [CGX_STAT1] =3D "Octets of received packets", diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 00af8888e329..785ef71a5ead 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -289,6 +289,23 @@ static void nix_rx_sync(struct rvu *rvu, int blkaddr) dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); } =20 +static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) +{ + struct rvu_hwinfo *hw =3D rvu->hw; + int pf =3D rvu_get_pf(pcifunc); + u8 cgx_id =3D 0, lmac_id =3D 0; + + if (is_lbk_vf(rvu, pcifunc)) {/* LBK links */ + return hw->cgx_links; + } else if (is_pf_cgxmapped(rvu, pf)) { + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + return (cgx_id * hw->lmac_per_cgx) + lmac_id; + } + + /* SDP link */ + return hw->cgx_links + hw->lbk_links; +} + static bool is_valid_txschq(struct rvu *rvu, int blkaddr, int lvl, u16 pcifunc, u16 schq) { @@ -584,6 +601,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, if (!is_pf_cgxmapped(rvu, pf) && type !=3D NIX_INTF_TYPE_LBK) return 0; =20 + if (is_sdp_pfvf(pcifunc)) + type =3D NIX_INTF_TYPE_SDP; + pfvf =3D rvu_get_pfvf(rvu, pcifunc); err =3D nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); if (err) @@ -1984,23 +2004,6 @@ static void nix_clear_tx_xoff(struct rvu *rvu, int b= lkaddr, rvu_write64(rvu, blkaddr, reg, 0x0); } =20 -static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) -{ - struct rvu_hwinfo *hw =3D rvu->hw; - int pf =3D rvu_get_pf(pcifunc); - u8 cgx_id =3D 0, lmac_id =3D 0; - - if (is_lbk_vf(rvu, pcifunc)) {/* LBK links */ - return hw->cgx_links; - } else if (is_pf_cgxmapped(rvu, pf)) { - rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); - return (cgx_id * hw->lmac_per_cgx) + lmac_id; - } - - /* SDP link */ - return hw->cgx_links + hw->lbk_links; -} - static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc, int link, int *start, int *end) { @@ -2930,7 +2933,7 @@ static int nix_tx_vtag_alloc(struct rvu *rvu, int blk= addr, { struct nix_hw *nix_hw =3D get_nix_hw(rvu->hw, blkaddr); struct nix_txvlan *vlan; - u64 regval; + u64 regval, etype; int index; =20 if (!nix_hw) @@ -2949,6 +2952,8 @@ static int nix_tx_vtag_alloc(struct rvu *rvu, int blk= addr, mutex_unlock(&vlan->rsrc_lock); =20 regval =3D size ? vtag : vtag << 32; + etype =3D FIELD_GET(NIX_VLAN_ETYPE_MASK, vtag); + regval |=3D FIELD_PREP(NIX_VLAN_ETYPE_MASK, etype); =20 rvu_write64(rvu, blkaddr, NIX_AF_TX_VTAG_DEFX_DATA(index), regval); @@ -4619,6 +4624,7 @@ static void nix_link_config(struct rvu *rvu, int blka= ddr, rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); =20 + rvu_write64(rvu, blkaddr, NIX_AF_SDP_LINK_CREDIT, SDP_LINK_CREDIT); /* Set default min/max packet lengths allowed on NIX Rx links. * * With HW reset minlen value of 60byte, HW will treat ARP pkts @@ -4630,14 +4636,15 @@ static void nix_link_config(struct rvu *rvu, int bl= kaddr, ((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS); } =20 - for (link =3D hw->cgx_links; link < hw->lbk_links; link++) { + for (link =3D hw->cgx_links; link < hw->cgx_links + hw->lbk_links; + link++) { rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS); } if (hw->sdp_links) { link =3D hw->cgx_links + hw->lbk_links; rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), - SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); + SDP_HW_MAX_FRS << 16 | SDP_HW_MIN_FRS); } =20 /* Get MCS external bypass status for CN10K-B */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 150635de2bd5..9fa06ec21ad1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -555,6 +555,7 @@ do { \ NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6); /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */ NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2); + NPC_SCAN_HDR(NPC_SQ_ID, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 2, 3); } =20 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf) @@ -1225,6 +1226,10 @@ static int npc_update_tx_entry(struct rvu *rvu, stru= ct rvu_pfvf *pfvf, npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target), 0, mask, 0, NIX_INTF_TX); =20 + npc_update_entry(rvu, NPC_SQ_ID, entry, + (__force u16)htons(req->packet.sq_id), + 0, req->mask.sq_id, 0, NIX_INTF_TX); + *(u64 *)&action =3D 0x00; action.op =3D req->op; action.index =3D req->index; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_reg.h index 5ec92654e7ad..789f11ae0f36 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -51,6 +51,8 @@ #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) #define RVU_AF_SMMU_ADDR_TLN (0x6018) #define RVU_AF_SMMU_TLN_FLIT0 (0x6020) +#define RVU_AF_BAR2_SEL (0x9000000) +#define RVU_AF_BAR2_PFID (0x16400) =20 /* Admin function's privileged PF/VF registers */ #define RVU_PRIV_CONST (0x8000000) @@ -431,6 +433,7 @@ #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16) #define NIX_AF_SMQX_STATUS(a) (0x730 | (a) << 16) #define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0 | (a) << 16) +#define NIX_LF_CINTX_INT_W1S(a) (0xd30 | (a) << 12) =20 #define NIX_PRIV_AF_INT_CFG (0x8000000) #define NIX_PRIV_LFX_CFG (0x8000010) @@ -443,6 +446,7 @@ =20 #define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12) #define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0) +#define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48) =20 #define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16) #define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_struct.h index 5ef406c7e8a4..ee54f1694ea6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h @@ -825,4 +825,30 @@ enum nix_tx_vtag_op { #define VTAG_STRIP BIT_ULL(4) #define VTAG_CAPTURE BIT_ULL(5) =20 +/* NIX TX stats */ +enum nix_stat_lf_tx { + TX_UCAST =3D 0x0, + TX_BCAST =3D 0x1, + TX_MCAST =3D 0x2, + TX_DROP =3D 0x3, + TX_OCTS =3D 0x4, + TX_STATS_ENUM_LAST, +}; + +/* NIX RX stats */ +enum nix_stat_lf_rx { + RX_OCTS =3D 0x0, + RX_UCAST =3D 0x1, + RX_BCAST =3D 0x2, + RX_MCAST =3D 0x3, + RX_DROP =3D 0x4, + RX_DROP_OCTS =3D 0x5, + RX_FCS =3D 0x6, + RX_ERR =3D 0x7, + RX_DRP_BCAST =3D 0x8, + RX_DRP_MCAST =3D 0x9, + RX_DRP_L3BCAST =3D 0xa, + RX_DRP_L3MCAST =3D 0xb, + RX_STATS_ENUM_LAST, +}; #endif /* RVU_STRUCT_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_switch.c index 854045ed3b06..ceb81eebf65e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c @@ -8,7 +8,7 @@ #include #include "rvu.h" =20 -static void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool = enable) +void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool enable) { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); struct nix_hw *nix_hw; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 87d5776e3b88..e38b3eea11f3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -227,7 +227,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) u16 maxlen; int err; =20 - maxlen =3D otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; + maxlen =3D pfvf->hw.max_mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; =20 mutex_lock(&pfvf->mbox.lock); req =3D otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); @@ -236,7 +236,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) return -ENOMEM; } =20 - req->maxlen =3D pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; + req->maxlen =3D mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; =20 /* Use max receive length supported by hardware for loopback devices */ if (is_otx2_lbkvf(pfvf->pdev)) @@ -246,6 +246,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) mutex_unlock(&pfvf->mbox.lock); return err; } +EXPORT_SYMBOL(otx2_hw_set_mtu); =20 int otx2_config_pause_frm(struct otx2_nic *pfvf) { @@ -1782,6 +1783,7 @@ void otx2_free_cints(struct otx2_nic *pfvf, int n) free_irq(vector, &qset->napi[qidx]); } } +EXPORT_SYMBOL(otx2_free_cints); =20 void otx2_set_cints_affinity(struct otx2_nic *pfvf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index f27a3456ae64..772fe01bdf98 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -120,33 +120,6 @@ enum otx2_errcodes_re { ERRCODE_IL4_CSUM =3D 0x22, }; =20 -/* NIX TX stats */ -enum nix_stat_lf_tx { - TX_UCAST =3D 0x0, - TX_BCAST =3D 0x1, - TX_MCAST =3D 0x2, - TX_DROP =3D 0x3, - TX_OCTS =3D 0x4, - TX_STATS_ENUM_LAST, -}; - -/* NIX RX stats */ -enum nix_stat_lf_rx { - RX_OCTS =3D 0x0, - RX_UCAST =3D 0x1, - RX_BCAST =3D 0x2, - RX_MCAST =3D 0x3, - RX_DROP =3D 0x4, - RX_DROP_OCTS =3D 0x5, - RX_FCS =3D 0x6, - RX_ERR =3D 0x7, - RX_DRP_BCAST =3D 0x8, - RX_DRP_MCAST =3D 0x9, - RX_DRP_L3BCAST =3D 0xa, - RX_DRP_L3MCAST =3D 0xb, - RX_STATS_ENUM_LAST, -}; - struct otx2_dev_stats { u64 rx_bytes; u64 rx_frames; @@ -228,6 +201,7 @@ struct otx2_hw { u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; u16 matchall_ipolicer; u32 dwrr_mtu; + u32 max_mtu; u8 smq_link_type; =20 /* HW settings, coalescing etc */ @@ -997,6 +971,21 @@ int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, int pool_id, int numptrs); =20 +int otx2_init_hw_resources(struct otx2_nic *pfvf); +void otx2_free_hw_resources(struct otx2_nic *pf); +int otx2_wq_init(struct otx2_nic *pf); +int otx2_check_pf_usable(struct otx2_nic *pf); +int otx2_pfaf_mbox_init(struct otx2_nic *pf); +int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af); +int otx2_realloc_msix_vectors(struct otx2_nic *pf); +void otx2_pfaf_mbox_destroy(struct otx2_nic *pf); +void otx2_disable_mbox_intr(struct otx2_nic *pf); +void otx2_free_queue_mem(struct otx2_qset *qset); +int otx2_alloc_queue_mem(struct otx2_nic *pf); +void otx2_disable_napi(struct otx2_nic *pf); +irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); +int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf); + /* RSS configuration APIs*/ int otx2_rss_init(struct otx2_nic *pfvf); int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ff05ea20409a..2b2afcc4b921 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1008,7 +1008,7 @@ static irqreturn_t otx2_pfaf_mbox_intr_handler(int ir= q, void *pf_irq) return IRQ_HANDLED; } =20 -static void otx2_disable_mbox_intr(struct otx2_nic *pf) +void otx2_disable_mbox_intr(struct otx2_nic *pf) { int vector =3D pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); =20 @@ -1016,8 +1016,9 @@ static void otx2_disable_mbox_intr(struct otx2_nic *p= f) otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); free_irq(vector, pf); } +EXPORT_SYMBOL(otx2_disable_mbox_intr); =20 -static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) +int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) { struct otx2_hw *hw =3D &pf->hw; struct msg_req *req; @@ -1060,8 +1061,9 @@ static int otx2_register_mbox_intr(struct otx2_nic *p= f, bool probe_af) =20 return 0; } +EXPORT_SYMBOL(otx2_register_mbox_intr); =20 -static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) +void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) { struct mbox *mbox =3D &pf->mbox; =20 @@ -1076,8 +1078,9 @@ static void otx2_pfaf_mbox_destroy(struct otx2_nic *p= f) otx2_mbox_destroy(&mbox->mbox); otx2_mbox_destroy(&mbox->mbox_up); } +EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); =20 -static int otx2_pfaf_mbox_init(struct otx2_nic *pf) +int otx2_pfaf_mbox_init(struct otx2_nic *pf) { struct mbox *mbox =3D &pf->mbox; void __iomem *hwbase; @@ -1124,6 +1127,7 @@ static int otx2_pfaf_mbox_init(struct otx2_nic *pf) otx2_pfaf_mbox_destroy(pf); return err; } +EXPORT_SYMBOL(otx2_pfaf_mbox_init); =20 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) { @@ -1379,7 +1383,7 @@ static irqreturn_t otx2_q_intr_handler(int irq, void = *data) return IRQ_HANDLED; } =20 -static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) +irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) { struct otx2_cq_poll *cq_poll =3D (struct otx2_cq_poll *)cq_irq; struct otx2_nic *pf =3D (struct otx2_nic *)cq_poll->dev; @@ -1398,20 +1402,25 @@ static irqreturn_t otx2_cq_intr_handler(int irq, vo= id *cq_irq) =20 return IRQ_HANDLED; } +EXPORT_SYMBOL(otx2_cq_intr_handler); =20 -static void otx2_disable_napi(struct otx2_nic *pf) +void otx2_disable_napi(struct otx2_nic *pf) { struct otx2_qset *qset =3D &pf->qset; struct otx2_cq_poll *cq_poll; + struct work_struct *work; int qidx; =20 for (qidx =3D 0; qidx < pf->hw.cint_cnt; qidx++) { cq_poll =3D &qset->napi[qidx]; - cancel_work_sync(&cq_poll->dim.work); + work =3D &cq_poll->dim.work; + if (work->func) + cancel_work_sync(work); napi_disable(&cq_poll->napi); netif_napi_del(&cq_poll->napi); } } +EXPORT_SYMBOL(otx2_disable_napi); =20 static void otx2_free_cq_res(struct otx2_nic *pf) { @@ -1477,7 +1486,7 @@ static int otx2_get_rbuf_size(struct otx2_nic *pf, in= t mtu) return ALIGN(rbuf_size, 2048); } =20 -static int otx2_init_hw_resources(struct otx2_nic *pf) +int otx2_init_hw_resources(struct otx2_nic *pf) { struct nix_lf_free_req *free_req; struct mbox *mbox =3D &pf->mbox; @@ -1601,8 +1610,9 @@ static int otx2_init_hw_resources(struct otx2_nic *pf) mutex_unlock(&mbox->lock); return err; } +EXPORT_SYMBOL(otx2_init_hw_resources); =20 -static void otx2_free_hw_resources(struct otx2_nic *pf) +void otx2_free_hw_resources(struct otx2_nic *pf) { struct otx2_qset *qset =3D &pf->qset; struct nix_lf_free_req *free_req; @@ -1688,6 +1698,7 @@ static void otx2_free_hw_resources(struct otx2_nic *p= f) } mutex_unlock(&mbox->lock); } +EXPORT_SYMBOL(otx2_free_hw_resources); =20 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) { @@ -1770,15 +1781,23 @@ static void otx2_dim_work(struct work_struct *w) dim->state =3D DIM_START_MEASURE; } =20 -int otx2_open(struct net_device *netdev) +void otx2_free_queue_mem(struct otx2_qset *qset) +{ + kfree(qset->sq); + qset->sq =3D NULL; + kfree(qset->cq); + qset->cq =3D NULL; + kfree(qset->rq); + qset->rq =3D NULL; + kfree(qset->napi); +} +EXPORT_SYMBOL(otx2_free_queue_mem); +int otx2_alloc_queue_mem(struct otx2_nic *pf) { - struct otx2_nic *pf =3D netdev_priv(netdev); - struct otx2_cq_poll *cq_poll =3D NULL; struct otx2_qset *qset =3D &pf->qset; - int err =3D 0, qidx, vec; - char *irq_name; + struct otx2_cq_poll *cq_poll; + int err =3D -ENOMEM; =20 - netif_carrier_off(netdev); =20 /* RQ and SQs are mapped to different CQs, * so find out max CQ IRQs (i.e CINTs) needed. @@ -1791,14 +1810,13 @@ int otx2_open(struct net_device *netdev) =20 qset->napi =3D kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); if (!qset->napi) - return -ENOMEM; + return err; =20 /* CQ size of RQ */ qset->rqe_cnt =3D qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); /* CQ size of SQ */ qset->sqe_cnt =3D qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); =20 - err =3D -ENOMEM; qset->cq =3D kcalloc(pf->qset.cq_cnt, sizeof(struct otx2_cq_queue), GFP_KERNEL); if (!qset->cq) @@ -1814,6 +1832,28 @@ int otx2_open(struct net_device *netdev) if (!qset->rq) goto err_free_mem; =20 + return 0; + +err_free_mem: + otx2_free_queue_mem(qset); + return err; +} +EXPORT_SYMBOL(otx2_alloc_queue_mem); + +int otx2_open(struct net_device *netdev) +{ + struct otx2_nic *pf =3D netdev_priv(netdev); + struct otx2_cq_poll *cq_poll =3D NULL; + struct otx2_qset *qset =3D &pf->qset; + int err =3D 0, qidx, vec; + char *irq_name; + + netif_carrier_off(netdev); + + err =3D otx2_alloc_queue_mem(pf); + if (err) + return err; + err =3D otx2_init_hw_resources(pf); if (err) goto err_free_mem; @@ -1979,10 +2019,7 @@ int otx2_open(struct net_device *netdev) otx2_disable_napi(pf); otx2_free_hw_resources(pf); err_free_mem: - kfree(qset->sq); - kfree(qset->cq); - kfree(qset->rq); - kfree(qset->napi); + otx2_free_queue_mem(qset); return err; } EXPORT_SYMBOL(otx2_open); @@ -2047,11 +2084,8 @@ int otx2_stop(struct net_device *netdev) for (qidx =3D 0; qidx < netdev->num_tx_queues; qidx++) netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); =20 + otx2_free_queue_mem(qset); =20 - kfree(qset->sq); - kfree(qset->cq); - kfree(qset->rq); - kfree(qset->napi); /* Do not clear RQ/SQ ringsize settings */ memset_startat(qset, 0, sqe_cnt); return 0; @@ -2081,7 +2115,7 @@ static netdev_tx_t otx2_xmit(struct sk_buff *skb, str= uct net_device *netdev) sq =3D &pf->qset.sq[sq_idx]; txq =3D netdev_get_tx_queue(netdev, qidx); =20 - if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { + if (!otx2_sq_append_skb(pf, txq, sq, skb, qidx)) { netif_tx_stop_queue(txq); =20 /* Check again, incase SQBs got freed up */ @@ -2786,7 +2820,7 @@ static const struct net_device_ops otx2_netdev_ops = =3D { .ndo_set_vf_trust =3D otx2_ndo_set_vf_trust, }; =20 -static int otx2_wq_init(struct otx2_nic *pf) +int otx2_wq_init(struct otx2_nic *pf) { pf->otx2_wq =3D create_singlethread_workqueue("otx2_wq"); if (!pf->otx2_wq) @@ -2797,7 +2831,7 @@ static int otx2_wq_init(struct otx2_nic *pf) return 0; } =20 -static int otx2_check_pf_usable(struct otx2_nic *nic) +int otx2_check_pf_usable(struct otx2_nic *nic) { u64 rev; =20 @@ -2814,8 +2848,9 @@ static int otx2_check_pf_usable(struct otx2_nic *nic) } return 0; } +EXPORT_SYMBOL(otx2_check_pf_usable); =20 -static int otx2_realloc_msix_vectors(struct otx2_nic *pf) +int otx2_realloc_msix_vectors(struct otx2_nic *pf) { struct otx2_hw *hw =3D &pf->hw; int num_vec, err; @@ -2837,6 +2872,7 @@ static int otx2_realloc_msix_vectors(struct otx2_nic = *pf) =20 return otx2_register_mbox_intr(pf, false); } +EXPORT_SYMBOL(otx2_realloc_msix_vectors); =20 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) { @@ -2872,6 +2908,88 @@ static void otx2_sriov_vfcfg_cleanup(struct otx2_nic= *pf) } } =20 +int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) +{ + struct device *dev =3D &pdev->dev; + struct otx2_hw *hw =3D &pf->hw; + int num_vec, err; + + num_vec =3D pci_msix_vec_count(pdev); + hw->irq_name =3D devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, + GFP_KERNEL); + if (!hw->irq_name) + return -ENOMEM; + + hw->affinity_mask =3D devm_kcalloc(&hw->pdev->dev, num_vec, + sizeof(cpumask_var_t), GFP_KERNEL); + if (!hw->affinity_mask) + return -ENOMEM; + + /* Map CSRs */ + pf->reg_base =3D pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); + if (!pf->reg_base) { + dev_err(dev, "Unable to map physical function CSRs, aborting\n"); + return -ENOMEM; + } + + err =3D otx2_check_pf_usable(pf); + if (err) + return err; + + err =3D pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, + RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); + if (err < 0) { + dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", + __func__, num_vec); + return err; + } + + otx2_setup_dev_hw_settings(pf); + + /* Init PF <=3D> AF mailbox stuff */ + err =3D otx2_pfaf_mbox_init(pf); + if (err) + goto err_free_irq_vectors; + + /* Register mailbox interrupt */ + err =3D otx2_register_mbox_intr(pf, true); + if (err) + goto err_mbox_destroy; + + /* Request AF to attach NPA and NIX LFs to this PF. + * NIX and NPA LFs are needed for this PF to function as a NIC. + */ + err =3D otx2_attach_npa_nix(pf); + if (err) + goto err_disable_mbox_intr; + + err =3D otx2_realloc_msix_vectors(pf); + if (err) + goto err_detach_rsrc; + + err =3D cn10k_lmtst_init(pf); + if (err) + goto err_detach_rsrc; + + return 0; + +err_detach_rsrc: + if (pf->hw.lmt_info) + free_percpu(pf->hw.lmt_info); + if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) + qmem_free(pf->dev, pf->dync_lmt); + otx2_detach_resources(&pf->mbox); +err_disable_mbox_intr: + otx2_disable_mbox_intr(pf); +err_mbox_destroy: + otx2_pfaf_mbox_destroy(pf); +err_free_irq_vectors: + pci_free_irq_vectors(hw->pdev); + + return err; +} +EXPORT_SYMBOL(otx2_init_rsrc); + static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct device *dev =3D &pdev->dev; @@ -2879,7 +2997,6 @@ static int otx2_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) struct net_device *netdev; struct otx2_nic *pf; struct otx2_hw *hw; - int num_vec; =20 err =3D pcim_enable_device(pdev); if (err) { @@ -2930,71 +3047,14 @@ static int otx2_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) /* Use CQE of 128 byte descriptor size by default */ hw->xqe_size =3D 128; =20 - num_vec =3D pci_msix_vec_count(pdev); - hw->irq_name =3D devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, - GFP_KERNEL); - if (!hw->irq_name) { - err =3D -ENOMEM; - goto err_free_netdev; - } - - hw->affinity_mask =3D devm_kcalloc(&hw->pdev->dev, num_vec, - sizeof(cpumask_var_t), GFP_KERNEL); - if (!hw->affinity_mask) { - err =3D -ENOMEM; - goto err_free_netdev; - } - - /* Map CSRs */ - pf->reg_base =3D pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); - if (!pf->reg_base) { - dev_err(dev, "Unable to map physical function CSRs, aborting\n"); - err =3D -ENOMEM; - goto err_free_netdev; - } - - err =3D otx2_check_pf_usable(pf); + err =3D otx2_init_rsrc(pdev, pf); if (err) goto err_free_netdev; =20 - err =3D pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, - RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); - if (err < 0) { - dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", - __func__, num_vec); - goto err_free_netdev; - } - - otx2_setup_dev_hw_settings(pf); - - /* Init PF <=3D> AF mailbox stuff */ - err =3D otx2_pfaf_mbox_init(pf); - if (err) - goto err_free_irq_vectors; - - /* Register mailbox interrupt */ - err =3D otx2_register_mbox_intr(pf, true); - if (err) - goto err_mbox_destroy; - - /* Request AF to attach NPA and NIX LFs to this PF. - * NIX and NPA LFs are needed for this PF to function as a NIC. - */ - err =3D otx2_attach_npa_nix(pf); - if (err) - goto err_disable_mbox_intr; - - err =3D otx2_realloc_msix_vectors(pf); - if (err) - goto err_detach_rsrc; - err =3D otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); if (err) goto err_detach_rsrc; =20 - err =3D cn10k_lmtst_init(pf); - if (err) - goto err_detach_rsrc; =20 /* Assign default mac address */ otx2_get_mac_from_af(netdev); @@ -3058,6 +3118,7 @@ static int otx2_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) =20 netdev->min_mtu =3D OTX2_MIN_MTU; netdev->max_mtu =3D otx2_get_max_mtu(pf); + hw->max_mtu =3D netdev->max_mtu; =20 /* reset CGX/RPM MAC stats */ otx2_reset_mac_stats(pf); @@ -3118,11 +3179,8 @@ static int otx2_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) qmem_free(pf->dev, pf->dync_lmt); otx2_detach_resources(&pf->mbox); -err_disable_mbox_intr: otx2_disable_mbox_intr(pf); -err_mbox_destroy: otx2_pfaf_mbox_destroy(pf); -err_free_irq_vectors: pci_free_irq_vectors(hw->pdev); err_free_netdev: pci_set_drvdata(pdev, NULL); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c index 3eb85949677a..fbd9fe98259f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c @@ -131,6 +131,7 @@ static void otx2_xdp_snd_pkt_handler(struct otx2_nic *p= fvf, } =20 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, + struct net_device *ndev, struct otx2_cq_queue *cq, struct otx2_snd_queue *sq, struct nix_cqe_tx_s *cqe, @@ -145,7 +146,7 @@ static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, =20 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", - pfvf->netdev->name, cq->cint_idx, + ndev->name, cq->cint_idx, snd_comp->status); =20 sg =3D &sq->sg[snd_comp->sqe_id]; @@ -453,6 +454,7 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, int tx_pkts =3D 0, tx_bytes =3D 0, qidx; struct otx2_snd_queue *sq; struct nix_cqe_tx_s *cqe; + struct net_device *ndev; int processed_cqe =3D 0; =20 if (cq->pend_cqe >=3D budget) @@ -464,6 +466,7 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, process_cqe: qidx =3D cq->cq_idx - pfvf->hw.rx_queues; sq =3D &pfvf->qset.sq[qidx]; + ndev =3D pfvf->netdev; =20 while (likely(processed_cqe < budget) && cq->pend_cqe) { cqe =3D (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); @@ -478,7 +481,8 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, if (cq->cq_type =3D=3D CQ_XDP) otx2_xdp_snd_pkt_handler(pfvf, sq, cqe); else - otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[qidx], + otx2_snd_pkt_handler(pfvf, ndev, cq, + &pfvf->qset.sq[qidx], cqe, budget, &tx_pkts, &tx_bytes); =20 cqe->hdr.cqe_type =3D NIX_XQE_TYPE_INVALID; @@ -505,7 +509,7 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, /* Check if queue was stopped earlier due to ring full */ smp_mb(); if (netif_tx_queue_stopped(txq) && - netif_carrier_ok(pfvf->netdev)) + netif_carrier_ok(ndev)) netif_tx_wake_queue(txq); } return 0; @@ -594,6 +598,7 @@ int otx2_napi_handler(struct napi_struct *napi, int bud= get) } return workdone; } +EXPORT_SYMBOL(otx2_napi_handler); =20 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx) @@ -1141,13 +1146,13 @@ static void otx2_set_txtstamp(struct otx2_nic *pfvf= , struct sk_buff *skb, } } =20 -bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *= sq, +bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq, + struct otx2_snd_queue *sq, struct sk_buff *skb, u16 qidx) { - struct netdev_queue *txq =3D netdev_get_tx_queue(netdev, qidx); - struct otx2_nic *pfvf =3D netdev_priv(netdev); int offset, num_segs, free_desc; struct nix_sqe_hdr_s *sqe_hdr; + struct otx2_nic *pfvf =3D dev; =20 /* Check if there is enough room between producer * and consumer index. diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h index 3f1d2655ff77..e1db5f961877 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h @@ -167,7 +167,8 @@ static inline u64 otx2_iova_to_phys(void *iommu_domain,= dma_addr_t dma_addr) } =20 int otx2_napi_handler(struct napi_struct *napi, int budget); -bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *= sq, +bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq, + struct otx2_snd_queue *sq, struct sk_buff *skb, u16 qidx); void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index 99fcc5661674..0486fca8b573 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -395,7 +395,7 @@ static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, str= uct net_device *netdev) sq =3D &vf->qset.sq[qidx]; txq =3D netdev_get_tx_queue(netdev, qidx); =20 - if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { + if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) { netif_tx_stop_queue(txq); =20 /* Check again, incase SQBs got freed up */ @@ -500,7 +500,7 @@ static const struct net_device_ops otx2vf_netdev_ops = =3D { .ndo_setup_tc =3D otx2_setup_tc, }; =20 -static int otx2_wq_init(struct otx2_nic *vf) +static int otx2_vf_wq_init(struct otx2_nic *vf) { vf->otx2_wq =3D create_singlethread_workqueue("otx2vf_wq"); if (!vf->otx2_wq) @@ -671,6 +671,7 @@ static int otx2vf_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) =20 netdev->min_mtu =3D OTX2_MIN_MTU; netdev->max_mtu =3D otx2_get_max_mtu(vf); + hw->max_mtu =3D netdev->max_mtu; =20 /* To distinguish, for LBK VFs set netdev name explicitly */ if (is_otx2_lbkvf(vf->pdev)) { @@ -688,7 +689,7 @@ static int otx2vf_probe(struct pci_dev *pdev, const str= uct pci_device_id *id) goto err_ptp_destroy; } =20 - err =3D otx2_wq_init(vf); + err =3D otx2_vf_wq_init(vf); if (err) goto err_unreg_netdev; =20 --=20 2.25.1