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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10c6c8dsm11087155ad.26.2024.06.28.02.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 02:38:06 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v6 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Date: Fri, 28 Jun 2024 17:37:06 +0800 Message-Id: <20240628093711.11716-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628093711.11716-1-yongxuan.wang@sifive.com> References: <20240628093711.11716-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang --- .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..c3d053ce7783 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,34 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. =20 + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed P= TE A/D + bit updates as ratified in the 20240213 version of the privile= ged + ISA specification. + + Both Svade and Svadu extensions control the hardware behavior = when + the PTE A/D bits need to be set. The default behavior for the = four + possible combinations of these extensions in the device tree a= re: + 1) Neither Svade nor Svadu present in DT =3D> It is technically + unknown whether the platform uses Svade or Svadu. Superviso= r may + assume Svade to be present and enabled or it can discover b= ased + on mvendorid, marchid, and mimpid. + 2) Only Svade present in DT =3D> Supervisor must assume Svade = to be + always enabled. (Obvious) + 3) Only Svadu present in DT =3D> Supervisor must assume Svadu = to be + always enabled. (Obvious) + 4) Both Svade and Svadu present in DT =3D> Supervisor must ass= ume + Svadu turned-off at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware upd= ating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull req= uest + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to = Svade + dt-binding description for more details. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grain= ed --=20 2.17.1