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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac10c6c8dsm11087155ad.26.2024.06.28.02.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 02:38:02 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , Samuel Holland , Samuel Ortiz , Daniel Henrique Barboza , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , "Mike Rapoport (IBM)" , Kemeng Shi , Charlie Jenkins , Peter Xu , "Matthew Wilcox (Oracle)" , Jisheng Zhang , Leonardo Bras Subject: [PATCH v6 1/4] RISC-V: Add Svade and Svadu Extensions Support Date: Fri, 28 Jun 2024 17:37:05 +0800 Message-Id: <20240628093711.11716-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240628093711.11716-1-yongxuan.wang@sifive.com> References: <20240628093711.11716-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 13 ++++++++++++- arch/riscv/kernel/cpufeature.c | 32 ++++++++++++++++++++++++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0525ee2d63c7..3d705e28ff85 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -36,6 +36,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..35d7aa49785d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADE 75 +#define RISCV_ISA_EXT_SVADU 76 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index aad8b8ca51f1..ec0cdacd7da0 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include =20 #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_S= HIFT) =20 @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } =20 #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include =20 static __always_inline bool has_svnapot(void) { @@ -624,6 +624,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _p= rot) return __pgprot(prot); } =20 +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bit= s need to be set. By + * default the M-mode firmware enables the hardware updating scheme when o= nly Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5ef48cb20ee1..d31f79bc4daf 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), @@ -554,6 +556,21 @@ static void __init riscv_fill_hwcap_from_isa_string(un= signed long *isa2hwcap) clear_bit(RISCV_ISA_EXT_v, isainfo->isa); } =20 + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extens= ion. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't @@ -619,6 +636,21 @@ static int __init riscv_fill_hwcap_from_ext_list(unsig= ned long *isa2hwcap) =20 of_node_put(cpu_node); =20 + /* + * When neither Svade nor Svadu present in DT, it is technically + * unknown whether the platform uses Svade or Svadu. Supervisor may + * assume Svade to be present and enabled or it can discover based + * on mvendorid, marchid, and mimpid. When both Svade and Svadu present + * in DT, supervisor must assume Svadu turned-off at boot time. To use + * Svadu, supervisor must explicitly enable it using the SBI FWFT extens= ion. + */ + if (!test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + !test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + set_bit(RISCV_ISA_EXT_SVADE, isainfo->isa); + else if (test_bit(RISCV_ISA_EXT_SVADE, isainfo->isa) && + test_bit(RISCV_ISA_EXT_SVADU, isainfo->isa)) + clear_bit(RISCV_ISA_EXT_SVADU, isainfo->isa); + /* * All "okay" harts should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't. --=20 2.17.1