From nobody Fri Dec 19 03:04:10 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE6C81A2FDB for ; Thu, 27 Jun 2024 20:39:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719520761; cv=none; b=qFZUAfuHyMQPwIT93zNI1KJ5twlbdsDeeGR6rQlMd93pwzO8vZJoXKqyNaYUi4NmWl+RmbWzuSruQBH4C80scmYEYjkxsr89fuFSsqALyx5HrxwRqYqmdrrO9tjoBbehrwFyr9iv+oq1OnF66JPClXpKM3cns9GwymcCh8IAxCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719520761; c=relaxed/simple; bh=zdAqMUk9VHyJiHDiw90uSeeCYe6sqc1oUAH918cf/OY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g4F2VVR4ZzvNbguLqyafVeM6RdZ9Gcyj/ZbAYG9WDNwh0QMWJtERwk0/7nxXMqyMJhNZxPrbd6wH52Mmundt+WvnZSXMnmWymvnGCQpcv5o1Lstu+uxwhEZsbDCvpcX5960Lij6W3pg0gO/BmDPz2m8OX40Gduj6Pk1LbA9519M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GQ9IeppV; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GQ9IeppV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719520760; x=1751056760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zdAqMUk9VHyJiHDiw90uSeeCYe6sqc1oUAH918cf/OY=; b=GQ9IeppVzkOWtH96/5dMMGTj7KpAfj6kHkZYC4KLDGVAYtXHfV8T+hOM r1yWNP2KLQdYN/PSC0zG3+HzHF3I++c6kEPR+RA4JnpMjYEv0mV51Nf3B 6OVYhoi8nC9QhMg3fOJI6YzKtUA7PVcmiZOjwTC71XooXzg4jamWKOpbn xVpqk3jZl9K3ttTjfSDeNoInZ4oG9Nm29tCx+s6nDIPTip4A58r2qdXBq ov5sE5TyvvGMn3hqCzt9uih3i5vriK24kMLezk7sHsJ0q0HWFBSZGyz6q uhdJh1hnloHEDzgiNvdNL6hlpGRd+dZI92hPgJOI2jyK5t/TUo+XaS3zg A==; X-CSE-ConnectionGUID: trdc3e7LSxSLwp5IEu4ByQ== X-CSE-MsgGUID: zl4YqEzBQMiNPG37AG5UKg== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="16809842" X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="16809842" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:39:11 -0700 X-CSE-ConnectionGUID: Yg5CSV4LQA24iyx2sIpRuw== X-CSE-MsgGUID: pNxhQzCMQDuhEI4i9PSWEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,167,1716274800"; d="scan'208";a="82052922" Received: from agluck-desk3.sc.intel.com ([172.25.222.70]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 13:39:10 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v22 15/18] x86/resctrl: Make __mon_event_count() handle sum domains Date: Thu, 27 Jun 2024 13:38:53 -0700 Message-ID: <20240627203856.66628-16-tony.luck@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240627203856.66628-1-tony.luck@intel.com> References: <20240627203856.66628-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Legacy resctrl monitor files must provide the sum of event values across all Sub-NUMA Cluster (SNC) domains that share an L3 cache instance. There are now two cases: 1) A specific domain is provided in struct rmid_read This is either a non-SNC system, or the request is to read data from just one SNC node. 2) Domain pointer is NULL. In this case the cacheinfo field in struct rmid_read indicates that all SNC nodes that share that L3 cache instance should have the event read and return the sum of all values. Update the CPU sanity check. The existing check that an event is read from a CPU in the requested domain still applies when reading a single domain. But when summing across domains a more relaxed check that the current CPU is in the scope of the L3 cache instance is appropriate since the MSRs to read events are scoped at L3 cache level. Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/resctrl/monitor.c | 51 ++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index ca309c93a56b..ca486d00541e 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -324,9 +324,6 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, stru= ct rdt_mon_domain *d, =20 resctrl_arch_rmid_read_context_check(); =20 - if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask)) - return -EINVAL; - prmid =3D logical_rmid_to_physical_rmid(cpu, rmid); ret =3D __rmid_read_phys(prmid, eventid, &msr_val); if (ret) @@ -592,7 +589,10 @@ static struct mbm_state *get_mbm_state(struct rdt_mon_= domain *d, u32 closid, =20 static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr) { + int cpu =3D smp_processor_id(); + struct rdt_mon_domain *d; struct mbm_state *m; + int err, ret; u64 tval =3D 0; =20 if (rr->first) { @@ -603,14 +603,47 @@ static int __mon_event_count(u32 closid, u32 rmid, st= ruct rmid_read *rr) return 0; } =20 - rr->err =3D resctrl_arch_rmid_read(rr->r, rr->d, closid, rmid, rr->evtid, - &tval, rr->arch_mon_ctx); - if (rr->err) - return rr->err; + if (rr->d) { + /* Reading a single domain, must be on a CPU in that domain. */ + if (!cpumask_test_cpu(cpu, &rr->d->hdr.cpu_mask)) + return -EINVAL; + rr->err =3D resctrl_arch_rmid_read(rr->r, rr->d, closid, rmid, + rr->evtid, &tval, rr->arch_mon_ctx); + if (rr->err) + return rr->err; =20 - rr->val +=3D tval; + rr->val +=3D tval; =20 - return 0; + return 0; + } + + /* Summing domains that share a cache, must be on a CPU for that cache. */ + if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) + return -EINVAL; + + /* + * Legacy files must report the sum of an event across all + * domains that share the same L3 cache instance. + * Report success if a read from any domain succeeds, -EINVAL + * (translated to "Unavailable" for user space) if reading from + * all domains fail for any reason. + */ + ret =3D -EINVAL; + list_for_each_entry(d, &rr->r->mon_domains, hdr.list) { + if (d->ci->id !=3D rr->ci->id) + continue; + err =3D resctrl_arch_rmid_read(rr->r, d, closid, rmid, + rr->evtid, &tval, rr->arch_mon_ctx); + if (!err) { + rr->val +=3D tval; + ret =3D 0; + } + } + + if (ret) + rr->err =3D ret; + + return ret; } =20 /* --=20 2.45.2