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charset="utf-8" From: Lad Prabhakar Add family-specific clock driver for RZ/V2H(P) SoCs. Signed-off-by: Lad Prabhakar --- v2->v3 - Dropped num_hw_resets from struct rzv2h_cpg_priv - Dropped range_check for module clocks - Made mon_index to s8 instead of u8 in struct rzv2h_mod_clk - Added support for critical module clocks with DEF_MOD_CRITICAL - Added check for mon_index in rzv2h_mod_clock_endisable and rzv2h_mod_clock_is_enabled() v1->v2 - Introduced family specific config option - Now using register indexes for CLKON/CLKMON/RST/RSTMON - Introduced PLL_CONF macro - Dropped function pointer to get PLL_CLK1/2 offsets - Added range check for core clks - Dropped NULLified clocks check - Updated commit description --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/rzv2h-cpg.c | 663 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 159 ++++++++ 4 files changed, 827 insertions(+) create mode 100644 drivers/clk/renesas/rzv2h-cpg.c create mode 100644 drivers/clk/renesas/rzv2h-cpg.h diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 4410d16de4e2..f078ccb635bb 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -228,6 +228,10 @@ config CLK_RZG2L bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 +config CLK_RZV2H + bool "RZ/V2H(P) family clock support" if COMPILE_TEST + select RESET_CONTROLLER + # Generic config CLK_RENESAS_CPG_MSSR bool "CPG/MSSR clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index f7e18679c3b8..d81a62e78345 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) +=3D rcar-gen3-cpg.o obj-$(CONFIG_CLK_RCAR_GEN4_CPG) +=3D rcar-gen4-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) +=3D rcar-usb2-clock-sel.o obj-$(CONFIG_CLK_RZG2L) +=3D rzg2l-cpg.o +obj-$(CONFIG_CLK_RZV2H) +=3D rzv2h-cpg.o =20 # Generic obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) +=3D renesas-cpg-mssr.o diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c new file mode 100644 index 000000000000..058d79673ae6 --- /dev/null +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2H(P) Clock Pulse Generator + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * Based on rzg2l-cpg.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2013 Ideas On Board SPRL + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "rzv2h-cpg.h" + +#ifdef DEBUG +#define WARN_DEBUG(x) WARN_ON(x) +#else +#define WARN_DEBUG(x) do { } while (0) +#endif + +#define GET_CLK_ON_OFFSET(x) (0x600 + ((x) * 4)) +#define GET_CLK_MON_OFFSET(x) (0x800 + ((x) * 4)) +#define GET_RST_OFFSET(x) (0x900 + ((x) * 4)) +#define GET_RST_MON_OFFSET(x) (0xA00 + ((x) * 4)) + +#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val))) +#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val)) +#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val)) +#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val)) + +/** + * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data + * + * @info: Pointer to platform data + * @dev: CPG device + * @base: CPG register block base address + * @clks: Array containing all Core and Module Clocks + * @num_core_clks: Number of Core Clocks in clks[] + * @num_mod_clks: Number of Module Clocks in clks[] + * @num_resets: Number of Module Resets in info->resets[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @rcdev: Reset controller entity + */ +struct rzv2h_cpg_priv { + const struct rzv2h_cpg_info *info; + struct device *dev; + void __iomem *base; + + struct clk **clks; + unsigned int num_core_clks; + unsigned int num_mod_clks; + unsigned int num_resets; + unsigned int last_dt_core_clk; + + struct reset_controller_dev rcdev; +}; + +struct pll_clk { + struct rzv2h_cpg_priv *priv; + void __iomem *base; + struct clk_hw hw; + unsigned int conf; + unsigned int type; +}; + +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzv2h_cpg_priv *priv =3D pll_clk->priv; + unsigned int clk1, clk2; + u64 rate; + + if (!PLL_CLK_ACCESS(pll_clk->conf)) + return 0; + + clk1 =3D readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf)); + clk2 =3D readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf)); + + rate =3D mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1), + 16 + SDIV(clk2)); + + return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1)); +} + +static const struct clk_ops rzv2h_cpg_pll_ops =3D { + .recalc_rate =3D rzv2h_cpg_pll_clk_recalc_rate, +}; + +static struct clk * __init +rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, + struct rzv2h_cpg_priv *priv, + const struct clk_ops *ops) +{ + void __iomem *base =3D priv->base; + struct clk **clks =3D priv->clks; + struct device *dev =3D priv->dev; + struct clk_init_data init; + const struct clk *parent; + const char *parent_name; + struct pll_clk *pll_clk; + + parent =3D clks[core->parent & 0xffff]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + pll_clk =3D devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D ops; + init.flags =3D 0; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + pll_clk->hw.init =3D &init; + pll_clk->conf =3D core->conf; + pll_clk->base =3D base; + pll_clk->priv =3D priv; + pll_clk->type =3D core->type; + + return devm_clk_register(dev, &pll_clk->hw); +} + +static struct clk +*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int clkidx =3D clkspec->args[1]; + struct rzv2h_cpg_priv *priv =3D data; + struct device *dev =3D priv->dev; + const char *type; + struct clk *clk; + + switch (clkspec->args[0]) { + case CPG_CORE: + type =3D "core"; + if (clkidx > priv->last_dt_core_clk) { + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); + return ERR_PTR(-EINVAL); + } + clk =3D priv->clks[clkidx]; + break; + + case CPG_MOD: + type =3D "module"; + if (clkidx >=3D priv->num_mod_clks) { + dev_err(dev, "Invalid %s clock index %u\n", type, clkidx); + return ERR_PTR(-EINVAL); + } + clk =3D priv->clks[priv->num_core_clks + clkidx]; + break; + + default: + dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); + return ERR_PTR(-EINVAL); + } + + if (IS_ERR(clk)) + dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, + PTR_ERR(clk)); + else + dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", + clkspec->args[0], clkspec->args[1], clk, + clk_get_rate(clk)); + return clk; +} + +static void __init +rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, + struct rzv2h_cpg_priv *priv) +{ + struct clk *clk =3D ERR_PTR(-EOPNOTSUPP), *parent; + struct device *dev =3D priv->dev; + unsigned int id =3D core->id, div =3D core->div; + const char *parent_name; + + WARN_DEBUG(id >=3D priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) !=3D -ENOENT); + + switch (core->type) { + case CLK_TYPE_IN: + clk =3D of_clk_get_by_name(priv->dev->of_node, core->name); + break; + case CLK_TYPE_FF: + WARN_DEBUG(core->parent >=3D priv->num_core_clks); + parent =3D priv->clks[core->parent]; + if (IS_ERR(parent)) { + clk =3D parent; + goto fail; + } + + parent_name =3D __clk_get_name(parent); + clk =3D clk_register_fixed_factor(NULL, core->name, + parent_name, CLK_SET_RATE_PARENT, + core->mult, div); + break; + case CLK_TYPE_PLL: + clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); + break; + default: + goto fail; + } + + if (IS_ERR_OR_NULL(clk)) + goto fail; + + dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); + priv->clks[id] =3D clk; + return; + +fail: + dev_err(dev, "Failed to register core clock %s: %ld\n", + core->name, PTR_ERR(clk)); +} + +/** + * struct mod_clock - Module clock + * + * @priv: CPG private data + * @hw: handle between common and hardware-specific interfaces + * @on_index: register offset + * @on_bit: ON/MON bit + * @mon_index: monitor register offset + * @mon_bit: montor bit + */ +struct mod_clock { + struct rzv2h_cpg_priv *priv; + struct clk_hw hw; + u8 on_index; + u8 on_bit; + s8 mon_index; + u8 mon_bit; +}; + +#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw) + +static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mod_clock *clock =3D to_mod_clock(hw); + unsigned int reg =3D GET_CLK_ON_OFFSET(clock->on_index); + struct rzv2h_cpg_priv *priv =3D clock->priv; + u32 bitmask =3D BIT(clock->on_bit); + struct device *dev =3D priv->dev; + u32 value; + int error; + + dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk, + enable ? "ON" : "OFF"); + + value =3D bitmask << 16; + if (enable) + value |=3D bitmask; + + writel(value, priv->base + reg); + + if (!enable || clock->mon_index < 0) + return 0; + + reg =3D GET_CLK_MON_OFFSET(clock->mon_index); + bitmask =3D BIT(clock->mon_bit); + error =3D readl_poll_timeout_atomic(priv->base + reg, value, + value & bitmask, 0, 10); + if (error) + dev_err(dev, "Failed to enable CLK_ON %p\n", + priv->base + reg); + + return error; +} + +static int rzv2h_mod_clock_enable(struct clk_hw *hw) +{ + return rzv2h_mod_clock_endisable(hw, true); +} + +static void rzv2h_mod_clock_disable(struct clk_hw *hw) +{ + rzv2h_mod_clock_endisable(hw, false); +} + +static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) +{ + struct mod_clock *clock =3D to_mod_clock(hw); + struct rzv2h_cpg_priv *priv =3D clock->priv; + u32 bitmask; + u32 offset; + + if (clock->mon_index >=3D 0) { + offset =3D GET_CLK_MON_OFFSET(clock->mon_index); + bitmask =3D BIT(clock->mon_bit); + } else { + offset =3D GET_CLK_ON_OFFSET(clock->on_index); + bitmask =3D BIT(clock->on_bit); + } + + return readl(priv->base + offset) & bitmask; +} + +static const struct clk_ops rzv2h_mod_clock_ops =3D { + .enable =3D rzv2h_mod_clock_enable, + .disable =3D rzv2h_mod_clock_disable, + .is_enabled =3D rzv2h_mod_clock_is_enabled, +}; + +static void __init +rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, + struct rzv2h_cpg_priv *priv) +{ + struct mod_clock *clock =3D NULL; + struct device *dev =3D priv->dev; + struct clk_init_data init; + unsigned int id =3D mod->id; + struct clk *parent, *clk; + const char *parent_name; + + WARN_DEBUG(id < priv->num_core_clks); + WARN_DEBUG(id >=3D priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(mod->parent >=3D priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) !=3D -ENOENT); + + parent =3D priv->clks[mod->parent]; + if (IS_ERR(parent)) { + clk =3D parent; + goto fail; + } + + clock =3D devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL); + if (!clock) { + clk =3D ERR_PTR(-ENOMEM); + goto fail; + } + + init.name =3D mod->name; + init.ops =3D &rzv2h_mod_clock_ops; + init.flags =3D CLK_SET_RATE_PARENT; + if (mod->critical) + init.flags |=3D CLK_IS_CRITICAL; + + parent_name =3D __clk_get_name(parent); + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + clock->on_index =3D mod->on_index; + clock->on_bit =3D mod->on_bit; + clock->mon_index =3D mod->mon_index; + clock->mon_bit =3D mod->mon_bit; + clock->priv =3D priv; + clock->hw.init =3D &init; + + clk =3D devm_clk_register(dev, &clock->hw); + if (IS_ERR(clk)) + goto fail; + + priv->clks[id] =3D clk; + + return; + +fail: + dev_err(dev, "Failed to register module clock %s: %ld\n", + mod->name, PTR_ERR(clk)); +} + +#define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) + +static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_cpg_priv *priv =3D rcdev_to_priv(rcdev); + const struct rzv2h_cpg_info *info =3D priv->info; + unsigned int reg =3D GET_RST_OFFSET(info->resets[id].reset_index); + u32 mask =3D BIT(info->resets[id].reset_bit); + u8 monbit =3D info->resets[id].mon_bit; + u32 value =3D mask << 16; + + dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg); + + writel(value, priv->base + reg); + + reg =3D GET_RST_MON_OFFSET(info->resets[id].mon_index); + mask =3D BIT(monbit); + + return readl_poll_timeout_atomic(priv->base + reg, value, + value & mask, 10, 200); +} + +static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_cpg_priv *priv =3D rcdev_to_priv(rcdev); + const struct rzv2h_cpg_info *info =3D priv->info; + unsigned int reg =3D GET_RST_OFFSET(info->resets[id].reset_index); + u32 mask =3D BIT(info->resets[id].reset_bit); + u8 monbit =3D info->resets[id].mon_bit; + u32 value =3D (mask << 16) | mask; + + dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg); + + writel(value, priv->base + reg); + + reg =3D GET_RST_MON_OFFSET(info->resets[id].mon_index); + mask =3D BIT(monbit); + + return readl_poll_timeout_atomic(priv->base + reg, value, + !(value & mask), 10, 200); +} + +static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret =3D rzv2h_cpg_assert(rcdev, id); + if (ret) + return ret; + + return rzv2h_cpg_deassert(rcdev, id); +} + +static int rzv2h_cpg_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct rzv2h_cpg_priv *priv =3D rcdev_to_priv(rcdev); + const struct rzv2h_cpg_info *info =3D priv->info; + unsigned int reg =3D GET_RST_MON_OFFSET(info->resets[id].mon_index); + u8 monbit =3D info->resets[id].mon_bit; + + return !!(readl(priv->base + reg) & BIT(monbit)); +} + +static const struct reset_control_ops rzv2h_cpg_reset_ops =3D { + .reset =3D rzv2h_cpg_reset, + .assert =3D rzv2h_cpg_assert, + .deassert =3D rzv2h_cpg_deassert, + .status =3D rzv2h_cpg_status, +}; + +static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int id =3D reset_spec->args[0]; + + if (id >=3D rcdev->nr_resets) { + dev_err(rcdev->dev, "Invalid reset index %u\n", id); + return -EINVAL; + } + + return id; +} + +static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv) +{ + priv->rcdev.ops =3D &rzv2h_cpg_reset_ops; + priv->rcdev.of_node =3D priv->dev->of_node; + priv->rcdev.dev =3D priv->dev; + priv->rcdev.of_reset_n_cells =3D 1; + priv->rcdev.of_xlate =3D rzv2h_cpg_reset_xlate; + priv->rcdev.nr_resets =3D priv->num_resets; + + return devm_reset_controller_register(priv->dev, &priv->rcdev); +} + +/** + * struct rzv2h_cpg_pd - RZ/V2H power domain data structure + * @priv: pointer to CPG private data structure + * @genpd: generic PM domain + */ +struct rzv2h_cpg_pd { + struct rzv2h_cpg_priv *priv; + struct generic_pm_domain genpd; +}; + +static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct d= evice *dev) +{ + struct device_node *np =3D dev->of_node; + struct of_phandle_args clkspec; + bool once =3D true; + struct clk *clk; + int error; + int i =3D 0; + + while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, + &clkspec)) { + if (once) { + once =3D false; + error =3D pm_clk_create(dev); + if (error) { + of_node_put(clkspec.np); + goto err; + } + } + clk =3D of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + if (IS_ERR(clk)) { + error =3D PTR_ERR(clk); + goto fail_destroy; + } + + error =3D pm_clk_add_clk(dev, clk); + if (error) { + dev_err(dev, "pm_clk_add_clk failed %d\n", + error); + goto fail_put; + } + i++; + } + + return 0; + +fail_put: + clk_put(clk); + +fail_destroy: + pm_clk_destroy(dev); +err: + return error; +} + +static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct = device *dev) +{ + if (!pm_clk_no_clocks(dev)) + pm_clk_destroy(dev); +} + +static void rzv2h_cpg_genpd_remove_simple(void *data) +{ + pm_genpd_remove(data); +} + +static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv) +{ + struct device *dev =3D priv->dev; + struct device_node *np =3D dev->of_node; + struct rzv2h_cpg_pd *pd; + int ret; + + pd =3D devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; + + pd->genpd.name =3D np->name; + pd->priv =3D priv; + pd->genpd.flags |=3D GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLA= G_ACTIVE_WAKEUP; + pd->genpd.attach_dev =3D rzv2h_cpg_attach_dev; + pd->genpd.detach_dev =3D rzv2h_cpg_detach_dev; + ret =3D pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd-= >genpd); + if (ret) + return ret; + + return of_genpd_add_provider_simple(np, &pd->genpd); +} + +static void rzv2h_cpg_del_clk_provider(void *data) +{ + of_clk_del_provider(data); +} + +static int __init rzv2h_cpg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + const struct rzv2h_cpg_info *info; + struct rzv2h_cpg_priv *priv; + unsigned int nclks, i; + struct clk **clks; + int error; + + info =3D of_device_get_match_data(dev); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->info =3D info; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + nclks =3D info->num_total_core_clks + info->num_hw_mod_clks; + clks =3D devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); + if (!clks) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->clks =3D clks; + priv->num_core_clks =3D info->num_total_core_clks; + priv->num_mod_clks =3D info->num_hw_mod_clks; + priv->last_dt_core_clk =3D info->last_dt_core_clk; + priv->num_resets =3D info->num_resets; + + for (i =3D 0; i < nclks; i++) + clks[i] =3D ERR_PTR(-ENOENT); + + for (i =3D 0; i < info->num_core_clks; i++) + rzv2h_cpg_register_core_clk(&info->core_clks[i], priv); + + for (i =3D 0; i < info->num_mod_clks; i++) + rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv); + + error =3D of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv); + if (error) + return error; + + error =3D devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np); + if (error) + return error; + + error =3D rzv2h_cpg_add_pm_domains(priv); + if (error) + return error; + + error =3D rzv2h_cpg_reset_controller_register(priv); + if (error) + return error; + + return 0; +} + +static const struct of_device_id rzv2h_cpg_match[] =3D { + { /* sentinel */ } +}; + +static struct platform_driver rzv2h_cpg_driver =3D { + .driver =3D { + .name =3D "rzv2h-cpg", + .of_match_table =3D rzv2h_cpg_match, + }, +}; + +static int __init rzv2h_cpg_init(void) +{ + return platform_driver_probe(&rzv2h_cpg_driver, rzv2h_cpg_probe); +} + +subsys_initcall(rzv2h_cpg_init); + +MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver"); diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h new file mode 100644 index 000000000000..2358782388c4 --- /dev/null +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/V2H(P) Clock Pulse Generator + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RENESAS_RZV2H_CPG_H__ +#define __RENESAS_RZV2H_CPG_H__ + +/** + * Definitions of CPG Core Clocks + * + * These include: + * - Clock outputs exported to DT + * - External input clocks + * - Internal CPG clocks + */ +struct cpg_core_clk { + const char *name; + unsigned int id; + unsigned int parent; + unsigned int div; + unsigned int mult; + unsigned int type; + unsigned int conf; +}; + +enum clk_types { + /* Generic */ + CLK_TYPE_IN, /* External Clock Input */ + CLK_TYPE_FF, /* Fixed Factor Clock */ + CLK_TYPE_PLL, +}; + +/* BIT(31) indicates if CLK1/2 are accessible or not */ +#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16))) +#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0) +#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16)) +#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4)) + +#define DEF_TYPE(_name, _id, _type...) \ + { .name =3D _name, .id =3D _id, .type =3D _type } +#define DEF_BASE(_name, _id, _type, _parent...) \ + DEF_TYPE(_name, _id, _type, .parent =3D _parent) +#define DEF_PLL(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent =3D _parent, .conf =3D _conf) +#define DEF_INPUT(_name, _id) \ + DEF_TYPE(_name, _id, CLK_TYPE_IN) +#define DEF_FIXED(_name, _id, _parent, _mult, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div =3D _div, .mult =3D _mult) + +/** + * struct rzv2h_mod_clk - Module Clocks definitions + * + * @name: handle between common and hardware-specific interfaces + * @parent: id of parent clock + * @id: clock index in array containing all Core and Module Clocks + * @critical: flag to indicate the clock is critical + * @on_index: control register index + * @on_bit: ON bit + * @mon_index: monitor register index + * @mon_bit: monitor bit + */ +struct rzv2h_mod_clk { + const char *name; + unsigned int parent; + unsigned int id; + bool critical; + u8 on_index; + u8 on_bit; + s8 mon_index; + u8 mon_bit; +}; + +#define DEF_MOD_BASE(_name, _parent, _id, _critical, _onindex, _onbit, _mo= nindex, _monbit) \ + { \ + .name =3D (_name), \ + .parent =3D (_parent), \ + .id =3D (_id), \ + .critical =3D (_critical), \ + .on_index =3D (_onindex), \ + .on_bit =3D (_onbit), \ + .mon_index =3D (_monindex), \ + .mon_bit =3D (_monbit), \ + } + +#define MOD_CLK_ID(x) (MOD_CLK_BASE + (x)) +#define MOD_ID(x, y) ((((x) * 16)) + (y)) + +#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ + DEF_MOD_BASE(_name, _parent, MOD_CLK_ID(MOD_ID(_onindex, _onbit)), \ + false, _onindex, _onbit, _monindex, _monbit) + +#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit) \ + DEF_MOD_BASE(_name, _parent, MOD_CLK_ID(MOD_ID(_onindex, _onbit)), \ + true, _onindex, _onbit, _monindex, _monbit) + +/** + * struct rzv2h_reset - Reset definitions + * + * @reset_index: reset register index + * @reset_bit: reset bit + * @mon_index: monitor register index + * @mon_bit: monitor bit + */ +struct rzv2h_reset { + u8 reset_index; + u8 reset_bit; + u8 mon_index; + u8 mon_bit; +}; + +#define RST_ID(x, y) ((((x) * 16)) + (y)) + +#define DEF_RST_BASE(_id, _resindex, _resbit, _monindex, _monbit) \ + [_id] =3D { \ + .reset_index =3D (_resindex), \ + .reset_bit =3D (_resbit), \ + .mon_index =3D (_monindex), \ + .mon_bit =3D (_monbit), \ + } + +#define DEF_RST(_resindex, _resbit, _monindex, _monbit) \ + DEF_RST_BASE(RST_ID((_resindex), (_resbit)), _resindex, _resbit, _moninde= x, _monbit) + +/** + * struct rzv2h_cpg_info - SoC-specific CPG Description + * + * @core_clks: Array of Core Clock definitions + * @num_core_clks: Number of entries in core_clks[] + * @last_dt_core_clk: ID of the last Core Clock exported to DT + * @num_total_core_clks: Total number of Core Clocks (exported + internal) + * + * @mod_clks: Array of Module Clock definitions + * @num_mod_clks: Number of entries in mod_clks[] + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware + * + * @resets: Array of Module Reset definitions + * @num_resets: Number of entries in resets[] + */ +struct rzv2h_cpg_info { + /* Core Clocks */ + const struct cpg_core_clk *core_clks; + unsigned int num_core_clks; + unsigned int last_dt_core_clk; + unsigned int num_total_core_clks; + + /* Module Clocks */ + const struct rzv2h_mod_clk *mod_clks; + unsigned int num_mod_clks; + unsigned int num_hw_mod_clks; + + /* Resets */ + const struct rzv2h_reset *resets; + unsigned int num_resets; +}; + +#endif /* __RENESAS_RZV2H_CPG_H__ */ --=20 2.34.1