From nobody Thu Dec 18 07:17:30 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7E0C13C831; Thu, 27 Jun 2024 10:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719483025; cv=none; b=dPKpggiwkcUbGlEBJTei/WKIeblex2CzltQK/Qngfm6oC8M9+opQzu5rTJl4FdX39FjO3L5QRxZ1N11y/QMcD3Cg25pVIyHYWyxggSnyyLqsmh7I/kcYec1Hca2ePrqfQ58vhLrmM4M0Ol/ZRfNpJuTLkC+y3R6cIqlxXHmSJSE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719483025; c=relaxed/simple; bh=ngp1FT+UOeOQu3QXLveoVHx3x4aIgCnlqdTftkNgha4=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=qEE65DjYxRGLOIm+AYqCvbRRduHAFwtOHqcR2iVeVe7kqKq0+lxFBWNt7ejaqsu9kG3Mp0mIO1GY90KZMnn7WmJh7A8axoIW6jd6srz0P/7SsXzMrUuz0xBedfSbZxL+MIkMNqW7YWS27/xzAGkl2yh6zwtnBWgfemsbKZaqF1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=YbdrfXp3; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YbdrfXp3" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45RAA82j062259; Thu, 27 Jun 2024 05:10:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1719483008; bh=DbAR1yoE7ko87b798yH4OO+KqU4hl93ILHvTCW1Chgs=; h=From:To:CC:Subject:Date; b=YbdrfXp3mWuFuzcHbiSQ8v9iuo4mjc0s6rL1m3tFo4NbbLwxnoIOEiPyU+/19rsHm MiDECSHiex0qxAJ9BolgaIRbLS3K9oaAMAm8YnuOErd6KrY78VRB0UBO+jhDCrML+y qG0u9G47nZ+lDpOgBxNnePZfne8dnf76qIITMX4A= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45RAA8T6014605 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Jun 2024 05:10:08 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 27 Jun 2024 05:10:08 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jun 2024 05:10:08 -0500 Received: from a0497641-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (a0497641-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.36]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45RAA4ST019141; Thu, 27 Jun 2024 05:10:05 -0500 From: Neha Malcom Francis To: , , , , , CC: , , , , Subject: [PATCH] arm: dts: k3-j721e-mcu-wakeup: Add bootph-all to chipid Date: Thu, 27 Jun 2024 15:40:03 +0530 Message-ID: <20240627101003.3608397-1-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add bootph-all property to the chipid node so that it is available at bootloader stage for obtaining the SoC ID and revision. Signed-off-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 9349ae07c046..c2417ef614cf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -57,6 +57,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible =3D "ti,am654-chipid"; reg =3D <0x14 0x4>; + bootph-all; }; }; =20 --=20 2.34.1