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Wed, 26 Jun 2024 03:28:17 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:59 +0300 Subject: [PATCH vhost v2 23/24] vdpa/mlx5: Don't reset VQs more than necessary Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240626-stage-vdpa-vq-precreate-v2-23-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|IA0PR12MB8304:EE_ X-MS-Office365-Filtering-Correlation-Id: ca6f368a-d223-42ad-efa2-08dc95cabafc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|36860700011|1800799022|7416012|82310400024|376012; X-Microsoft-Antispam-Message-Info: =?utf-8?B?eVZNeTRVMXl3UDR1VEpOZm0rOEVjNU8wYVdFR2JaWkVrbGpYQlgrM0JVTXRN?= =?utf-8?B?anNUZkJlWnhEWHJwbjNKL0cyanIxYU1VTURzSVNQNWtzRlFsV2wrQXcrYzZq?= =?utf-8?B?NDArODVGOGlVUlF2eHZtODFOclpXWFdtQ3NzYjY5aHBrOEx3citDS0R2bDJM?= =?utf-8?B?TWFMb3N2K21ObTdRbGh4TXo3VEZ1OUhYWkVhdFBkS0hDVGE5alhTOGZlMUhx?= =?utf-8?B?NlRoUWVTNmFJOUx6MUhySndVVXpjYnpVcjVyVmxjZGJmaXViSERORk1TMnIv?= =?utf-8?B?Q2hCbGFJWWNlODFmeHlSWW9lTm5sdldFNjdPSFpzemxtV1lFUS9GUUg4Y0do?= =?utf-8?B?QnlNU0dvYjJqVEdORXJlSmhQOFlaR0tRNlhrNjRVYVN2M0xGOHRJM2p4Tmt2?= =?utf-8?B?eGlWS05mcVNicXhlWHJxLzhxakp6dWJhYTNldGVIUnU5UDNuaDJHZ3VLSXJH?= =?utf-8?B?ZVlnZ0tiM1BrQ0tEQWhub3g1ZEFMU3V6WDJ5bzF6cTBCdFltVXdIdTJHekNQ?= =?utf-8?B?bkJhNllCdGFibjNUVHdhYmRZUlJZSHF6UkxMckw1QnJMUFY1UmNuUzhmR3pu?= =?utf-8?B?d1BjbnJnV3RkTEd6VE5xNHd3M0RUSnFyWTlQMnVIeW80NDJ6bnA3dnRzeUxT?= =?utf-8?B?cDFiVEVPcEhFRGZybjBRRE5xTHA5QnNWN0RmcFlvNGJ0KzFsYUhQVXdlaVpG?= =?utf-8?B?Mmx0Zk80K096K1E5VURoL3lQR2ZzRjJZcFRxVnVybCtvRjk2L1ZvRWJ4anVa?= =?utf-8?B?UDNJNWpPVW5vRFpaSFFockU1MTdmTVEySVoxWElQOXQ2eDlESjdoK0Mzd1Zu?= =?utf-8?B?T04xNGhTVW5EOFhGNFJRMjhlanQycjhWbTViWmZUWmdkL3hRbmhrVHg5dTBR?= =?utf-8?B?Mmw3cUcwK1o4RmV0SXB5YVdZUzdTeWVCT2owRnF2Nmx4dDF0SWFTSi82MFpi?= =?utf-8?B?cW9QcjRXTGErdDQyZVF5bW9jSUcxNVVCQUtqOUlubEhJZkJjS0tWVEdUbGxp?= =?utf-8?B?TCtXU2Z1Rlh6eHBYc0pOUVhyR3c0Q1hXaWlJYkF6RnhBb21QMnNpQVQzN3Jv?= =?utf-8?B?S05Tc2pTWlVEUXdraFc2WGs0U0FOVVUyMko5NVRRaUpqU2lwd0lDWGliNmxs?= =?utf-8?B?ZWtQN0lBRlJDMUptWVVJdFhjZUk5elJaRStFWVZtRkY4azBickM5Nk9PS0RV?= =?utf-8?B?enZLUjZWaWJIRUdMMDN4RXYzdEFLRjlOUU8zZDJtTy9YZFdlTGFicC9TRlhW?= =?utf-8?B?b3dtdjRUYThqZGRNcTljYlpJZHFFZWlvaXJCR1o1RERKcCtBSFA4b1RiY21W?= =?utf-8?B?ZVQxR3czZUVncVN0YzMvY3kxQ1VVbXNnSm9BM3h3T0hGRndYRE5ZbzZJdVFS?= =?utf-8?B?TFIzSkJXdXUvK1JPcFZLa1c2VkhaOUxaZTVTTWxBQlBMRmxTRjNLKzk3YmZ6?= =?utf-8?B?OUwvN3Y4WVVvRktNK2hENnl5R1U2b25hcG56RzJTTVVxaFF2ZUl6c21zS3BD?= =?utf-8?B?eDlEQmpZaUV1dCt3RklsVWNJVEpwRUQ5VVNKVmJONkZmTWQrYWtROWpIQ2da?= =?utf-8?B?ZUhlKzhoVTdrRmI5dkY5OUtiWGE5TWdXUjFldW13a0h5VHNNOFp6aFRQa0xU?= =?utf-8?B?TFVNYWNZSE9DN1ZZSXl6RjVZZ2wvOFh0MUFnNVhmQy9vTGgvMEJCTUdQUEkw?= =?utf-8?B?bHM5dzZQV3YwWS9nSVF6YU9pUTByeGdSNVRtdXpudXVaOGQ0R2lPcVRkc3hm?= =?utf-8?B?RDJvcnBHR0dEOC9nSHNVZTRUSG1KdUVaZUZFUUVtaktHUXBjakR0QXdIZHA1?= =?utf-8?B?Wi82VXZ6aTNpWmxORmhGM1RyckhrYmhud3hxd1F4bUp1dUxzU0IzcmdFS2JV?= =?utf-8?B?cXc5MEpQdTZqQVRSNEVCRk9PQlR6b0lUcloxOTVHNWc4UUE9PQ==?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230038)(36860700011)(1800799022)(7416012)(82310400024)(376012);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:33.2057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca6f368a-d223-42ad-efa2-08dc95cabafc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8304 The vdpa device can be reset many times in sequence without any significant state changes in between. Previously this was not a problem: VQs were torn down only on first reset. But after VQ pre-creation was introduced, each reset will delete and re-create the hardware VQs and their associated resources. To solve this problem, avoid resetting hardware VQs if the VQs are still in a blank state. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio P=C3=A9rez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5= _vnet.c index ea4bfd9afce9..573dc01df8c3 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -3134,18 +3134,41 @@ static void init_group_to_asid_map(struct mlx5_vdpa= _dev *mvdev) mvdev->group2asid[i] =3D 0; } =20 +static bool needs_vqs_reset(const struct mlx5_vdpa_dev *mvdev) +{ + struct mlx5_vdpa_net *ndev =3D to_mlx5_vdpa_ndev(mvdev); + struct mlx5_vdpa_virtqueue *mvq =3D &ndev->vqs[0]; + + if (mvdev->status & VIRTIO_CONFIG_S_DRIVER_OK) + return true; + + if (mvq->fw_state !=3D MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT) + return true; + + return mvq->modified_fields & ( + MLX5_VIRTQ_MODIFY_MASK_STATE | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_ADDRS | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_AVAIL_IDX | + MLX5_VIRTQ_MODIFY_MASK_VIRTIO_Q_USED_IDX + ); +} + static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) { struct mlx5_vdpa_dev *mvdev =3D to_mvdev(vdev); struct mlx5_vdpa_net *ndev =3D to_mlx5_vdpa_ndev(mvdev); + bool vq_reset; =20 print_status(mvdev, 0, true); mlx5_vdpa_info(mvdev, "performing device reset\n"); =20 down_write(&ndev->reslock); unregister_link_notifier(ndev); - teardown_vq_resources(ndev); - mvqs_set_defaults(ndev); + vq_reset =3D needs_vqs_reset(mvdev); + if (vq_reset) { + teardown_vq_resources(ndev); + mvqs_set_defaults(ndev); + } =20 if (flags & VDPA_RESET_F_CLEAN_MAP) mlx5_vdpa_destroy_mr_resources(&ndev->mvdev); @@ -3165,7 +3188,8 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device = *vdev, u32 flags) if (mlx5_vdpa_create_dma_mr(mvdev)) mlx5_vdpa_warn(mvdev, "create MR failed\n"); } - setup_vq_resources(ndev, false); + if (vq_reset) + setup_vq_resources(ndev, false); up_write(&ndev->reslock); =20 return 0; --=20 2.45.1