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Wed, 26 Jun 2024 03:28:13 -0700 From: Dragos Tatulea Date: Wed, 26 Jun 2024 13:26:58 +0300 Subject: [PATCH vhost v2 22/24] vdpa/mlx5: Re-create HW VQs under certain conditions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240626-stage-vdpa-vq-precreate-v2-22-560c491078df@nvidia.com> References: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> In-Reply-To: <20240626-stage-vdpa-vq-precreate-v2-0-560c491078df@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Cosmin Ratiu , Dragos Tatulea X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|SA1PR12MB8985:EE_ X-MS-Office365-Filtering-Correlation-Id: b23490ed-89d9-4fbe-6f6f-08dc95cab8ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230038|82310400024|7416012|376012|36860700011|1800799022; X-Microsoft-Antispam-Message-Info: =?utf-8?B?TVM5TFZGaVJVVnZuTnRCRm4rV3BZMlRQWXJHMVlTTDUzUllmSDNUNFBGbDJh?= =?utf-8?B?dk9TUEZDWTNUMm5XblVHM3dpZ0tzajM2TFJFWXB6ajhRNm5aNmUyTng2eWI0?= =?utf-8?B?SE9lYTZyMEVCdTQrbHJ4ZWhlSU1xeWEwVUZVQUxRRno0aW00MmkxcitOdnM2?= =?utf-8?B?WERRek00K2VYdlkxelRPTFUzRklxTmZFdzR6QnZtWHVjYjdaTjU2Y1hwc2VW?= =?utf-8?B?QUxzaW9abzdHakdOSlFDKzV6dXpJeXZ3a0dRbmRzYzN6L2tpOWZWR2Q3U2Iv?= =?utf-8?B?YWxQUGdWRHhNcDUwakpkUENWeVRCWFJONGpHVXhJaG10TUsxaExJL3gvUUJs?= =?utf-8?B?NXQvSGZPeG03Nm9wbUdUZG9oNjVsSzJnN1FtUW1UQTJkQVNhdUxUZ2pneEJ2?= =?utf-8?B?VnJyZ09mUVIyT0dXdE5MT3BrOFdtSHBhOFZQblpuT0l1NlVHa3FFaFpTbjdh?= =?utf-8?B?akMxRFNTSkxEQStBNTh6ZVFOWmhQaUJrT253V2pkSG4wYjVBa2t0M0ZvNEtD?= =?utf-8?B?ZVZwUkJoNEhPMWF2QjIyaWlac1lnYVdPL0k0VzRyK01SdWR3RWlrbnNZUG84?= =?utf-8?B?bFFaVGpyNTNiVEVIaHZlVzFSdEkrd0lpd0xSaHlYd0xlbU85VlliR1FoN1d0?= =?utf-8?B?djVGZGdsOU9DcnVWU3h0OVZjOW9sbnhITmVmZ3lmOTQrUmtoOTlnRUxieFhQ?= =?utf-8?B?QTZod2lESUJMN1pWTDhVRUw4RXlXRVpTd1NWSHVKZ29ORUxPZWxKMHdqbHVt?= =?utf-8?B?cHJUYnVQenNKbHkrM2FjS2hGWm4xQ2NLKzdYRnBFblJuK3k2MThCbDlUQUNW?= =?utf-8?B?WDdGb3Q3Tm9HeEJjY0xRSHB0OHg4TGVnNnVVRVZpRVJCeEZuU3hYaDFXN1Uw?= =?utf-8?B?bXh3Y0pZZ28wMXlVbkN0eHVabmRuMmZRSFRxanRVY2xVc2NkY1lMUFhEZmhx?= =?utf-8?B?UXQ5K3pwcTB1ODV5OFN6WXY2dWJIdUdraGhXRmE5bTZXcjh2Mi8wTHNMZVF4?= =?utf-8?B?N0hrbHk3WnZ2N3pxVm40YjRseitMVHdIbzhYZVlZZDVYZjhpUVhYRGdvaHl4?= =?utf-8?B?azNFYjd2TmxXeHo1MGgvcnF2TnhQY2VmZEJSbVNsYWJoRnJQeU1CTCtvRFRQ?= =?utf-8?B?YW9ldW10VFdYUU1NbmJaVTUrYmRNRXVmYWxXVW5XaEVzbkpZVVRtWFVpU0U5?= =?utf-8?B?REltYmdReHYwc1FlVDV4YVNYZHVwYXV4ZzlpL3FjTFZWUVNyS2lsNVNtT3ZM?= =?utf-8?B?dTA5V2ZTNkRESGhDVWJrajdVOTZaZFQ3YVduejlYYjNMS01mVlZxMEkxYXpE?= =?utf-8?B?S01HK0RvWkdraHB0aWhyaU5uOXkrWkFBY2N1NVBBLzBCTkp2MTVOMU4yanJF?= =?utf-8?B?QktjM1h1REhZcDdKY05KeFJFdHJTUWhndDVSRHo2aUlhaTFJa0JIcnhyRWRL?= =?utf-8?B?WUkwTG5mNmlVSFhyejBmTnRITUVKZExGc0RKcGRRbFdCNWdtdXhSdVY1RXJG?= =?utf-8?B?Y24xVDluaEw4OUVwTjNvVkJ4TWh5emNxdnREWWwwTHhoSFZSbEZxR1VOOU9u?= =?utf-8?B?cEp2VjBWK0ptRDhhTUduTWpXQ2doNlBwZm82Y2xxeUtxaVRhS0hMNitmSDlv?= =?utf-8?B?WURYVWgxZUMxYTZydjl1V2pucitBUktyWDArRmYydHIrdzJDRW12MFpncE1t?= =?utf-8?B?cFM0a2FZRU1jcEU2b1JnczV4aU52WGMwenJOL2ZjUUJQVm5icEJ4OEtrRmk4?= =?utf-8?B?MytYSHUxU25RRzRZczE4eVIwVTYzUVhUcFRkY0RxTExHWkNLcHNYWXdIQWow?= =?utf-8?B?UDg2NGxlMnBqNHIyQ1NXRTU2UmE4eDE2eGQxd1lXRGRndlh6cHZCY2M0VW5i?= =?utf-8?B?NVZUM2xTNlVTSWFqMkhlTSswaVp3enFsTlN0NGNxODZVNndHbEZJc3hlUkNJ?= =?utf-8?Q?MSifUAbqpDVcM0d3GTqt2Nr3+etbndSI?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230038)(82310400024)(7416012)(376012)(36860700011)(1800799022);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2024 10:28:29.4881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b23490ed-89d9-4fbe-6f6f-08dc95cab8ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8985 There are a few conditions under which the hardware VQs need a full teardown and setup: - VQ size changed to something else than default value. Hardware VQ size modification is not supported. - User turns off certain device features: mergeable buffers, checksum virtio 1.0 compliance. In these cases, the TIR and RQT need to be re-created. Add a needs_teardown configuration variable and set it when detecting the above scenarios. On next DRIVER_OK, the resources will be torn down first. Reviewed-by: Cosmin Ratiu Acked-by: Eugenio P=C3=A9rez Signed-off-by: Dragos Tatulea --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 15 +++++++++++++++ drivers/vdpa/mlx5/net/mlx5_vnet.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5= _vnet.c index 8ef703f4c23d..ea4bfd9afce9 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2390,6 +2390,7 @@ static void mlx5_vdpa_set_vq_num(struct vdpa_device *= vdev, u16 idx, u32 num) } =20 mvq =3D &ndev->vqs[idx]; + ndev->needs_teardown =3D num !=3D mvq->num_ent; mvq->num_ent =3D num; } =20 @@ -2800,6 +2801,7 @@ static int mlx5_vdpa_set_driver_features(struct vdpa_= device *vdev, u64 features) struct mlx5_vdpa_dev *mvdev =3D to_mvdev(vdev); struct mlx5_vdpa_net *ndev =3D to_mlx5_vdpa_ndev(mvdev); u64 old_features =3D mvdev->actual_features; + u64 diff_features; int err; =20 print_features(mvdev, features, true); @@ -2822,6 +2824,14 @@ static int mlx5_vdpa_set_driver_features(struct vdpa= _device *vdev, u64 features) } } =20 + /* When below features diverge from initial device features, VQs need a f= ull teardown. */ +#define NEEDS_TEARDOWN_MASK (BIT_ULL(VIRTIO_NET_F_MRG_RXBUF) | \ + BIT_ULL(VIRTIO_NET_F_CSUM) | \ + BIT_ULL(VIRTIO_F_VERSION_1)) + + diff_features =3D mvdev->mlx_features ^ mvdev->actual_features; + ndev->needs_teardown =3D !!(diff_features & NEEDS_TEARDOWN_MASK); + update_cvq_info(mvdev); return err; } @@ -3038,6 +3048,7 @@ static void teardown_vq_resources(struct mlx5_vdpa_ne= t *ndev) destroy_rqt(ndev); teardown_virtqueues(ndev); ndev->setup =3D false; + ndev->needs_teardown =3D false; } =20 static int setup_cvq_vring(struct mlx5_vdpa_dev *mvdev) @@ -3078,6 +3089,10 @@ static void mlx5_vdpa_set_status(struct vdpa_device = *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); + + if (ndev->needs_teardown) + teardown_vq_resources(ndev); + if (ndev->setup) { err =3D resume_vqs(ndev); if (err) { diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.h b/drivers/vdpa/mlx5/net/mlx5= _vnet.h index 90b556a57971..00e79a7d0be8 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.h +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.h @@ -56,6 +56,7 @@ struct mlx5_vdpa_net { struct dentry *rx_dent; struct dentry *rx_table_dent; bool setup; + bool needs_teardown; u32 cur_num_vqs; u32 rqt_size; bool nb_registered; --=20 2.45.1