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Shutemov" , Samuel Holland Subject: [PATCH v2 01/10] dt-bindings: riscv: Add pointer masking ISA extensions Date: Tue, 25 Jun 2024 14:09:12 -0700 Message-ID: <20240625210933.1620802-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RISC-V Pointer Masking specification defines three extensions: Smmpm, Smnpm, and Ssnpm. Document the behavior of these extensions as following the current draft of the specification, which is 1.0.0-rc2. Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Changes in v2: - Update pointer masking specification version reference .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index cfed80ad5540..b6aeedc53676 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,18 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smmpm + description: | + The standard Smmpm extension for M-mode pointer masking as def= ined + at commit 654a5c4a7725 ("Update PDF and version number.") of + riscv-j-extension. + + - const: smnpm + description: | + The standard Smnpm extension for next-mode pointer masking as = defined + at commit 654a5c4a7725 ("Update PDF and version number.") of + riscv-j-extension. + - const: smstateen description: | The standard Smstateen extension for controlling access to CSRs @@ -147,6 +159,12 @@ properties: and mode-based filtering as ratified at commit 01d1df0 ("Add a= bility to manually trigger workflow. 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Shutemov" , Samuel Holland Subject: [PATCH v2 02/10] riscv: Add ISA extension parsing for pointer masking Date: Tue, 25 Jun 2024 14:09:13 -0700 Message-ID: <20240625210933.1620802-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RISC-V Pointer Masking specification defines three extensions: Smmpm, Smnpm, and Ssnpm. Add support for parsing each of them. Which of these three extensions provide pointer masking support in the kernel (SxPM) and in userspace (SUPM) depends on the kernel's privilege mode, so provide macros to abstract this selection. Smmpm implies the existence of the mseccfg CSR. As it is the only user of this CSR so far, there is no need for an Xlinuxmseccfg extension. Signed-off-by: Samuel Holland --- Changes in v2: - Provide macros for the extension affecting the kernel and userspace arch/riscv/include/asm/hwcap.h | 7 +++++++ arch/riscv/kernel/cpufeature.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f64d4e98e67c..5291e08fe026 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,9 @@ #define RISCV_ISA_EXT_ZVE64X 77 #define RISCV_ISA_EXT_ZVE64F 78 #define RISCV_ISA_EXT_ZVE64D 79 +#define RISCV_ISA_EXT_SMMPM 80 +#define RISCV_ISA_EXT_SMNPM 81 +#define RISCV_ISA_EXT_SSNPM 82 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 @@ -94,8 +97,12 @@ =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA +#define RISCV_ISA_EXT_SxPM RISCV_ISA_EXT_SMMPM +#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#define RISCV_ISA_EXT_SxPM RISCV_ISA_EXT_SMNPM +#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d3e3a865b874..b22087244856 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -339,9 +339,12 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), + __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), --=20 2.44.1 From nobody Wed Dec 17 21:15:11 2025 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B75CA17F367 for ; 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Tue, 25 Jun 2024 14:09:41 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb328f57sm85873455ad.110.2024.06.25.14.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 14:09:40 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , Samuel Holland Subject: [PATCH v2 03/10] riscv: Add CSR definitions for pointer masking Date: Tue, 25 Jun 2024 14:09:14 -0700 Message-ID: <20240625210933.1620802-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pointer masking is controlled via a two-bit PMM field, which appears in various CSRs depending on which extensions are implemented. Smmpm adds the field to mseccfg; Smnpm adds the field to menvcfg; Ssnpm adds the field to senvcfg. If the H extension is implemented, Ssnpm also defines henvcfg.PMM and hstatus.HUPMM. Signed-off-by: Samuel Holland --- Changes in v2: - Use the correct name for the hstatus.HUPMM field arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..5c0c0d574f63 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -119,6 +119,10 @@ =20 /* HSTATUS flags */ #ifdef CONFIG_64BIT +#define HSTATUS_HUPMM _AC(0x3000000000000, UL) +#define HSTATUS_HUPMM_PMLEN_0 _AC(0x0000000000000, UL) +#define HSTATUS_HUPMM_PMLEN_7 _AC(0x2000000000000, UL) +#define HSTATUS_HUPMM_PMLEN_16 _AC(0x3000000000000, UL) #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif @@ -195,6 +199,10 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_PMM _AC(0x300000000, ULL) +#define ENVCFG_PMM_PMLEN_0 _AC(0x000000000, ULL) +#define ENVCFG_PMM_PMLEN_7 _AC(0x200000000, ULL) +#define ENVCFG_PMM_PMLEN_16 _AC(0x300000000, ULL) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 @@ -216,6 +224,12 @@ #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) =20 +/* mseccfg bits */ +#define MSECCFG_PMM ENVCFG_PMM +#define MSECCFG_PMM_PMLEN_0 ENVCFG_PMM_PMLEN_0 +#define MSECCFG_PMM_PMLEN_7 ENVCFG_PMM_PMLEN_7 +#define MSECCFG_PMM_PMLEN_16 ENVCFG_PMM_PMLEN_16 + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -382,6 +396,8 @@ #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPADDR0 0x3b0 +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 --=20 2.44.1 From nobody Wed Dec 17 21:15:11 2025 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 785DA17F516 for ; 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Tue, 25 Jun 2024 14:09:42 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb328f57sm85873455ad.110.2024.06.25.14.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 14:09:42 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , Samuel Holland Subject: [PATCH v2 04/10] riscv: Add support for userspace pointer masking Date: Tue, 25 Jun 2024 14:09:15 -0700 Message-ID: <20240625210933.1620802-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RISC-V supports pointer masking with a variable number of tag bits (which is called "PMLEN" in the specification) and which is configured at the next higher privilege level. Wire up the PR_SET_TAGGED_ADDR_CTRL and PR_GET_TAGGED_ADDR_CTRL prctls so userspace can request a lower bound on the number of tag bits and determine the actual number of tag bits. As with arm64's PR_TAGGED_ADDR_ENABLE, the pointer masking configuration is thread-scoped, inherited on clone() and fork() and cleared on execve(). Signed-off-by: Samuel Holland --- Changes in v2: - Rebase on riscv/linux.git for-next - Add and use the envcfg_update_bits() helper function - Inline flush_tagged_addr_state() arch/riscv/Kconfig | 11 ++++ arch/riscv/include/asm/processor.h | 8 +++ arch/riscv/include/asm/switch_to.h | 11 ++++ arch/riscv/kernel/process.c | 99 ++++++++++++++++++++++++++++++ include/uapi/linux/prctl.h | 3 + 5 files changed, 132 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b94176e25be1..8f9980f81ea5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -505,6 +505,17 @@ config RISCV_ISA_C =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_POINTER_MASKING + bool "Smmpm, Smnpm, and Ssnpm extensions for pointer masking" + depends on 64BIT + default y + help + Add support for the pointer masking extensions (Smmpm, Smnpm, + and Ssnpm) when they are detected at boot. + + If this option is disabled, userspace will be unable to use + the prctl(PR_{SET,GET}_TAGGED_ADDR_CTRL) API. + config RISCV_ISA_SVNAPOT bool "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 0838922bd1c8..4f99c85d29ae 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -194,6 +194,14 @@ extern int set_unalign_ctl(struct task_struct *tsk, un= signed int val); #define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_ctx(= arg1, arg2) extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per= _thread); =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); +long get_tagged_addr_ctrl(struct task_struct *task); +#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) +#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) +#endif + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 9685cd85e57c..94e33216b2d9 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -70,6 +70,17 @@ static __always_inline bool has_fpu(void) { return false= ; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif =20 +static inline void envcfg_update_bits(struct task_struct *task, + unsigned long mask, unsigned long val) +{ + unsigned long envcfg; + + envcfg =3D (task->thread.envcfg & ~mask) | val; + task->thread.envcfg =3D envcfg; + if (task =3D=3D current) + csr_write(CSR_ENVCFG, envcfg); +} + static inline void __switch_to_envcfg(struct task_struct *next) { asm volatile (ALTERNATIVE("nop", "csrw " __stringify(CSR_ENVCFG) ", %0", diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e4bc61c4e58a..dec5ccc44697 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -7,6 +7,7 @@ * Copyright (C) 2017 SiFive */ =20 +#include #include #include #include @@ -171,6 +172,10 @@ void flush_thread(void) memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); clear_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + envcfg_update_bits(current, ENVCFG_PMM, ENVCFG_PMM_PMLEN_0); +#endif } =20 void arch_release_task_struct(struct task_struct *tsk) @@ -233,3 +238,97 @@ void __init arch_task_cache_init(void) { riscv_v_setup_ctx_cache(); } + +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static bool have_user_pmlen_7; +static bool have_user_pmlen_16; + +long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) +{ + unsigned long valid_mask =3D PR_PMLEN_MASK; + struct thread_info *ti =3D task_thread_info(task); + unsigned long pmm; + u8 pmlen; + + if (is_compat_thread(ti)) + return -EINVAL; + + if (arg & ~valid_mask) + return -EINVAL; + + pmlen =3D FIELD_GET(PR_PMLEN_MASK, arg); + if (pmlen > 16) { + return -EINVAL; + } else if (pmlen > 7) { + if (have_user_pmlen_16) + pmlen =3D 16; + else + return -EINVAL; + } else if (pmlen > 0) { + /* + * Prefer the smallest PMLEN that satisfies the user's request, + * in case choosing a larger PMLEN has a performance impact. + */ + if (have_user_pmlen_7) + pmlen =3D 7; + else if (have_user_pmlen_16) + pmlen =3D 16; + else + return -EINVAL; + } + + if (pmlen =3D=3D 7) + pmm =3D ENVCFG_PMM_PMLEN_7; + else if (pmlen =3D=3D 16) + pmm =3D ENVCFG_PMM_PMLEN_16; + else + pmm =3D ENVCFG_PMM_PMLEN_0; + + envcfg_update_bits(task, ENVCFG_PMM, pmm); + + return 0; +} + +long get_tagged_addr_ctrl(struct task_struct *task) +{ + struct thread_info *ti =3D task_thread_info(task); + long ret =3D 0; + + if (is_compat_thread(ti)) + return -EINVAL; + + switch (task->thread.envcfg & ENVCFG_PMM) { + case ENVCFG_PMM_PMLEN_7: + ret |=3D FIELD_PREP(PR_PMLEN_MASK, 7); + break; + case ENVCFG_PMM_PMLEN_16: + ret |=3D FIELD_PREP(PR_PMLEN_MASK, 16); + break; + } + + return ret; +} + +static bool try_to_set_pmm(unsigned long value) +{ + csr_set(CSR_ENVCFG, value); + return (csr_read_clear(CSR_ENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D value; +} + +static int __init tagged_addr_init(void) +{ + if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + return 0; + + /* + * envcfg.PMM is a WARL field. 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Shutemov" , Samuel Holland Subject: [PATCH v2 05/10] riscv: Add support for the tagged address ABI Date: Tue, 25 Jun 2024 14:09:16 -0700 Message-ID: <20240625210933.1620802-6-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When pointer masking is enabled for userspace, the kernel can accept tagged pointers as arguments to some system calls. Allow this by untagging the pointers in access_ok() and the uaccess routines. The uaccess routines must peform untagging in software because U-mode and S-mode have entirely separate pointer masking configurations. In fact, hardware may not even implement pointer masking for S-mode. Since the number of tag bits is variable, untagged_addr_remote() needs to know what PMLEN to use for the remote mm. Therefore, the pointer masking mode must be the same for all threads sharing an mm. Enforce this with a lock flag in the mm context, as x86 does for LAM. The flag gets reset in init_new_context() during fork(), as the new mm is no longer multithreaded. Unlike x86, untagged_addr() gets pmlen from struct thread_info instead of a percpu variable, as this both avoids context switch overhead and loads the value more efficiently. Signed-off-by: Samuel Holland --- Changes in v2: - Implement untagged_addr_remote() - Restrict PMLEN changes once a process is multithreaded arch/riscv/include/asm/mmu.h | 7 +++ arch/riscv/include/asm/mmu_context.h | 6 +++ arch/riscv/include/asm/thread_info.h | 3 ++ arch/riscv/include/asm/uaccess.h | 58 +++++++++++++++++++++-- arch/riscv/kernel/process.c | 69 +++++++++++++++++++++++++++- 5 files changed, 136 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 947fd60f9051..361a9623f8c8 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -26,8 +26,15 @@ typedef struct { unsigned long exec_fdpic_loadmap; unsigned long interp_fdpic_loadmap; #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + unsigned long flags; + u8 pmlen; +#endif } mm_context_t; =20 +/* Lock the pointer masking mode because this mm is multithreaded */ +#define MM_CONTEXT_LOCK_PMLEN 0 + #define cntx2asid(cntx) ((cntx) & SATP_ASID_MASK) #define cntx2version(cntx) ((cntx) & ~SATP_ASID_MASK) =20 diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/= mmu_context.h index 7030837adc1a..62a9f76cf257 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -20,6 +20,9 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *= next, static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) { +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + next->context.pmlen =3D 0; +#endif switch_mm(prev, next, NULL); } =20 @@ -29,6 +32,9 @@ static inline int init_new_context(struct task_struct *ts= k, { #ifdef CONFIG_MMU atomic_long_set(&mm->context.id, 0); +#endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + clear_bit(MM_CONTEXT_LOCK_PMLEN, &mm->context.flags); #endif return 0; } diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 5d473343634b..cd355f8a550f 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -60,6 +60,9 @@ struct thread_info { void *scs_base; void *scs_sp; #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + u8 pmlen; +#endif }; =20 #ifdef CONFIG_SHADOW_CALL_STACK diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uacc= ess.h index 72ec1d9bd3f3..153495997bc1 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -9,8 +9,56 @@ #define _ASM_RISCV_UACCESS_H =20 #include +#include #include /* for TASK_SIZE */ =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static inline unsigned long __untagged_addr(unsigned long addr) +{ + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) { + u8 pmlen =3D current->thread_info.pmlen; + + /* Virtual addresses are sign-extended; physical addresses are zero-exte= nded. */ + if (IS_ENABLED(CONFIG_MMU)) + return (long)(addr << pmlen) >> pmlen; + else + return (addr << pmlen) >> pmlen; + } + + return addr; +} + +#define untagged_addr(addr) ({ \ + unsigned long __addr =3D (__force unsigned long)(addr); \ + (__force __typeof__(addr))__untagged_addr(__addr); \ +}) + +static inline unsigned long __untagged_addr_remote(struct mm_struct *mm, u= nsigned long addr) +{ + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) { + u8 pmlen =3D mm->context.pmlen; + + /* Virtual addresses are sign-extended; physical addresses are zero-exte= nded. */ + if (IS_ENABLED(CONFIG_MMU)) + return (long)(addr << pmlen) >> pmlen; + else + return (addr << pmlen) >> pmlen; + } + + return addr; +} + +#define untagged_addr_remote(mm, addr) ({ \ + unsigned long __addr =3D (__force unsigned long)(addr); \ + mmap_assert_locked(mm); \ + (__force __typeof__(addr))__untagged_addr_remote(mm, __addr); \ +}) + +#define access_ok(addr, size) likely(__access_ok(untagged_addr(addr), size= )) +#else +#define untagged_addr(addr) (addr) +#endif + /* * User space memory access functions */ @@ -130,7 +178,7 @@ do { \ */ #define __get_user(x, ptr) \ ({ \ - const __typeof__(*(ptr)) __user *__gu_ptr =3D (ptr); \ + const __typeof__(*(ptr)) __user *__gu_ptr =3D untagged_addr(ptr); \ long __gu_err =3D 0; \ \ __chk_user_ptr(__gu_ptr); \ @@ -246,7 +294,7 @@ do { \ */ #define __put_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__gu_ptr =3D (ptr); \ + __typeof__(*(ptr)) __user *__gu_ptr =3D untagged_addr(ptr); \ __typeof__(*__gu_ptr) __val =3D (x); \ long __pu_err =3D 0; \ \ @@ -293,13 +341,13 @@ unsigned long __must_check __asm_copy_from_user(void = *to, static inline unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n) { - return __asm_copy_from_user(to, from, n); + return __asm_copy_from_user(to, untagged_addr(from), n); } =20 static inline unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n) { - return __asm_copy_to_user(to, from, n); + return __asm_copy_to_user(untagged_addr(to), from, n); } =20 extern long strncpy_from_user(char *dest, const char __user *src, long cou= nt); @@ -314,7 +362,7 @@ unsigned long __must_check clear_user(void __user *to, = unsigned long n) { might_fault(); return access_ok(to, n) ? - __clear_user(to, n) : n; + __clear_user(untagged_addr(to), n) : n; } =20 #define __get_kernel_nofault(dst, src, type, err_label) \ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index dec5ccc44697..7bd445dade92 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -173,8 +173,10 @@ void flush_thread(void) clear_tsk_thread_flag(current, TIF_RISCV_V_DEFER_RESTORE); #endif #ifdef CONFIG_RISCV_ISA_POINTER_MASKING - if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) { envcfg_update_bits(current, ENVCFG_PMM, ENVCFG_PMM_PMLEN_0); + current->thread_info.pmlen =3D 0; + } #endif } =20 @@ -204,6 +206,12 @@ int copy_thread(struct task_struct *p, const struct ke= rnel_clone_args *args) unsigned long tls =3D args->tls; struct pt_regs *childregs =3D task_pt_regs(p); =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + /* Ensure all threads in this mm have the same pointer masking mode. */ + if (p->mm && (clone_flags & CLONE_VM)) + set_bit(MM_CONTEXT_LOCK_PMLEN, &p->mm->context.flags); +#endif + memset(&p->thread.s, 0, sizeof(p->thread.s)); =20 /* p->thread holds context to be restored by __switch_to() */ @@ -243,10 +251,16 @@ void __init arch_task_cache_init(void) static bool have_user_pmlen_7; static bool have_user_pmlen_16; =20 +/* + * Control the relaxed ABI allowing tagged user addresses into the kernel. + */ +static unsigned int tagged_addr_disabled; + long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg) { - unsigned long valid_mask =3D PR_PMLEN_MASK; + unsigned long valid_mask =3D PR_PMLEN_MASK | PR_TAGGED_ADDR_ENABLE; struct thread_info *ti =3D task_thread_info(task); + struct mm_struct *mm =3D task->mm; unsigned long pmm; u8 pmlen; =20 @@ -277,6 +291,14 @@ long set_tagged_addr_ctrl(struct task_struct *task, un= signed long arg) return -EINVAL; } =20 + /* + * Do not allow the enabling of the tagged address ABI if globally + * disabled via sysctl abi.tagged_addr_disabled, if pointer masking + * is disabled for userspace. + */ + if (arg & PR_TAGGED_ADDR_ENABLE && (tagged_addr_disabled || !pmlen)) + return -EINVAL; + if (pmlen =3D=3D 7) pmm =3D ENVCFG_PMM_PMLEN_7; else if (pmlen =3D=3D 16) @@ -284,7 +306,22 @@ long set_tagged_addr_ctrl(struct task_struct *task, un= signed long arg) else pmm =3D ENVCFG_PMM_PMLEN_0; =20 + if (!(arg & PR_TAGGED_ADDR_ENABLE)) + pmlen =3D 0; + + if (mmap_write_lock_killable(mm)) + return -EINTR; + + if (test_bit(MM_CONTEXT_LOCK_PMLEN, &mm->context.flags) && mm->context.pm= len !=3D pmlen) { + mmap_write_unlock(mm); + return -EBUSY; + } + envcfg_update_bits(task, ENVCFG_PMM, pmm); + task->mm->context.pmlen =3D pmlen; + task->thread_info.pmlen =3D pmlen; + + mmap_write_unlock(mm); =20 return 0; } @@ -297,6 +334,13 @@ long get_tagged_addr_ctrl(struct task_struct *task) if (is_compat_thread(ti)) return -EINVAL; =20 + if (task->thread_info.pmlen) + ret =3D PR_TAGGED_ADDR_ENABLE; + + /* + * The task's pmlen is only set if the tagged address ABI is enabled, + * so the effective PMLEN must be extracted from envcfg.PMM. + */ switch (task->thread.envcfg & ENVCFG_PMM) { case ENVCFG_PMM_PMLEN_7: ret |=3D FIELD_PREP(PR_PMLEN_MASK, 7); @@ -315,6 +359,24 @@ static bool try_to_set_pmm(unsigned long value) return (csr_read_clear(CSR_ENVCFG, ENVCFG_PMM) & ENVCFG_PMM) =3D=3D value; } =20 +/* + * Global sysctl to disable the tagged user addresses support. This control + * only prevents the tagged address ABI enabling via prctl() and does not + * disable it for tasks that already opted in to the relaxed ABI. + */ + +static struct ctl_table tagged_addr_sysctl_table[] =3D { + { + .procname =3D "tagged_addr_disabled", + .mode =3D 0644, + .data =3D &tagged_addr_disabled, + .maxlen =3D sizeof(int), + .proc_handler =3D proc_dointvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, +}; + static int __init tagged_addr_init(void) { if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_SUPM)) @@ -328,6 +390,9 @@ static int __init tagged_addr_init(void) have_user_pmlen_7 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_7); have_user_pmlen_16 =3D try_to_set_pmm(ENVCFG_PMM_PMLEN_16); =20 + if (!register_sysctl("abi", tagged_addr_sysctl_table)) + return -EINVAL; + return 0; } core_initcall(tagged_addr_init); --=20 2.44.1 From nobody Wed Dec 17 21:15:11 2025 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 169B517E446 for ; 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Shutemov" , Samuel Holland Subject: [PATCH v2 06/10] riscv: Allow ptrace control of the tagged address ABI Date: Tue, 25 Jun 2024 14:09:17 -0700 Message-ID: <20240625210933.1620802-7-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This allows a tracer to control the ABI of the tracee, as on arm64. Signed-off-by: Samuel Holland --- (no changes since v1) arch/riscv/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 43 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 92731ff8c79a..f8ceecc562fe 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -28,6 +28,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + REGSET_TAGGED_ADDR_CTRL, +#endif }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +155,35 @@ static int riscv_vr_set(struct task_struct *target, } #endif =20 +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING +static int tagged_addr_ctrl_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + long ctrl =3D get_tagged_addr_ctrl(target); + + if (IS_ERR_VALUE(ctrl)) + return ctrl; + + return membuf_write(&to, &ctrl, sizeof(ctrl)); +} + +static int tagged_addr_ctrl_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + long ctrl; + + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, &ctrl, 0, -1); + if (ret) + return ret; + + return set_tagged_addr_ctrl(target, ctrl); +} +#endif + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -182,6 +214,16 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_ISA_POINTER_MASKING + [REGSET_TAGGED_ADDR_CTRL] =3D { + .core_note_type =3D NT_RISCV_TAGGED_ADDR_CTRL, + .n =3D 1, + .size =3D sizeof(long), + .align =3D sizeof(long), + .regset_get =3D tagged_addr_ctrl_get, + .set =3D tagged_addr_ctrl_set, + }, +#endif }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b54b313bcf07..9a32532d7264 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -448,6 +448,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (= prctl()) */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension regist= ers */ --=20 2.44.1 From nobody Wed Dec 17 21:15:11 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C363F180A83 for ; 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Shutemov" , Samuel Holland Subject: [PATCH v2 07/10] selftests: riscv: Add a pointer masking test Date: Tue, 25 Jun 2024 14:09:18 -0700 Message-ID: <20240625210933.1620802-8-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This test covers the behavior of the PR_SET_TAGGED_ADDR_CTRL and PR_GET_TAGGED_ADDR_CTRL prctl() operations, their effects on the userspace ABI, and their effects on the system call ABI. Signed-off-by: Samuel Holland --- Changes in v2: - Rename "tags" directory to "pm" to avoid .gitignore rules - Add .gitignore file to ignore the compiled selftest binary - Write to a pipe to force dereferencing the user pointer - Handle SIGSEGV in the child process to reduce dmesg noise tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/pm/.gitignore | 1 + tools/testing/selftests/riscv/pm/Makefile | 10 + .../selftests/riscv/pm/pointer_masking.c | 330 ++++++++++++++++++ 4 files changed, 342 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/pm/.gitignore create mode 100644 tools/testing/selftests/riscv/pm/Makefile create mode 100644 tools/testing/selftests/riscv/pm/pointer_masking.c diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftes= ts/riscv/Makefile index 7ce03d832b64..2ee1d1548c5f 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?=3D $(shell uname -m 2>/dev/null || echo not) =20 ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?=3D hwprobe vector mm sigreturn +RISCV_SUBTARGETS ?=3D hwprobe mm pm sigreturn vector else RISCV_SUBTARGETS :=3D endif diff --git a/tools/testing/selftests/riscv/pm/.gitignore b/tools/testing/se= lftests/riscv/pm/.gitignore new file mode 100644 index 000000000000..b38358f91c4d --- /dev/null +++ b/tools/testing/selftests/riscv/pm/.gitignore @@ -0,0 +1 @@ +pointer_masking diff --git a/tools/testing/selftests/riscv/pm/Makefile b/tools/testing/self= tests/riscv/pm/Makefile new file mode 100644 index 000000000000..ed82ff9c664e --- /dev/null +++ b/tools/testing/selftests/riscv/pm/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +CFLAGS +=3D -I$(top_srcdir)/tools/include + +TEST_GEN_PROGS :=3D pointer_masking + +include ../../lib.mk + +$(OUTPUT)/pointer_masking: pointer_masking.c + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/pm/pointer_masking.c b/tools/tes= ting/selftests/riscv/pm/pointer_masking.c new file mode 100644 index 000000000000..0fe80f963ace --- /dev/null +++ b/tools/testing/selftests/riscv/pm/pointer_masking.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../kselftest.h" + +#ifndef PR_PMLEN_SHIFT +#define PR_PMLEN_SHIFT 24 +#endif +#ifndef PR_PMLEN_MASK +#define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT) +#endif + +static int dev_zero; + +static int pipefd[2]; + +static sigjmp_buf jmpbuf; + +static void sigsegv_handler(int sig) +{ + siglongjmp(jmpbuf, 1); +} + +static int min_pmlen; +static int max_pmlen; + +static inline bool valid_pmlen(int pmlen) +{ + return pmlen =3D=3D 0 || pmlen =3D=3D 7 || pmlen =3D=3D 16; +} + +static void test_pmlen(void) +{ + ksft_print_msg("Testing available PMLEN values\n"); + + for (int request =3D 0; request <=3D 16; request++) { + int pmlen, ret; + + ret =3D prctl(PR_SET_TAGGED_ADDR_CTRL, request << PR_PMLEN_SHIFT, 0, 0, = 0); + if (ret) + goto pr_set_error; + + ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0); + ksft_test_result(ret >=3D 0, "PMLEN=3D%d PR_GET_TAGGED_ADDR_CTRL\n", req= uest); + if (ret < 0) + goto pr_get_error; + + pmlen =3D (ret & PR_PMLEN_MASK) >> PR_PMLEN_SHIFT; + ksft_test_result(pmlen >=3D request, "PMLEN=3D%d constraint\n", request); + ksft_test_result(valid_pmlen(pmlen), "PMLEN=3D%d validity\n", request); + + if (min_pmlen =3D=3D 0) + min_pmlen =3D pmlen; + if (max_pmlen < pmlen) + max_pmlen =3D pmlen; + + continue; + +pr_set_error: + ksft_test_result_skip("PMLEN=3D%d PR_GET_TAGGED_ADDR_CTRL\n", request); +pr_get_error: + ksft_test_result_skip("PMLEN=3D%d constraint\n", request); + ksft_test_result_skip("PMLEN=3D%d validity\n", request); + } + + if (max_pmlen =3D=3D 0) + ksft_exit_fail_msg("Failed to enable pointer masking\n"); +} + +static int set_tagged_addr_ctrl(int pmlen, bool tagged_addr_abi) +{ + int arg, ret; + + arg =3D pmlen << PR_PMLEN_SHIFT | tagged_addr_abi; + ret =3D prctl(PR_SET_TAGGED_ADDR_CTRL, arg, 0, 0, 0); + if (!ret) { + ret =3D prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0); + if (ret =3D=3D arg) + return 0; + } + + return ret < 0 ? -errno : -ENODATA; +} + +static void test_dereference_pmlen(int pmlen) +{ + static volatile int i; + volatile int *p; + int ret; + + ret =3D set_tagged_addr_ctrl(pmlen, false); + if (ret) + return ksft_test_result_error("PMLEN=3D%d setup (%d)\n", pmlen, ret); + + i =3D pmlen; + + if (pmlen) { + p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen); + + /* These dereferences should succeed. */ + if (sigsetjmp(jmpbuf, 1)) + return ksft_test_result_fail("PMLEN=3D%d valid tag\n", pmlen); + if (*p !=3D pmlen) + return ksft_test_result_fail("PMLEN=3D%d bad value\n", pmlen); + *p++; + } + + p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen - 1); + + /* These dereferences should raise SIGSEGV. */ + if (sigsetjmp(jmpbuf, 1)) + return ksft_test_result_pass("PMLEN=3D%d dereference\n", pmlen); + *p++; + ksft_test_result_fail("PMLEN=3D%d invalid tag\n", pmlen); +} + +static void test_dereference(void) +{ + ksft_print_msg("Testing userspace pointer dereference\n"); + + signal(SIGSEGV, sigsegv_handler); + + test_dereference_pmlen(0); + test_dereference_pmlen(min_pmlen); + test_dereference_pmlen(max_pmlen); + + signal(SIGSEGV, SIG_DFL); +} + +static void execve_child_sigsegv_handler(int sig) +{ + exit(42); +} + +static int execve_child(void) +{ + static volatile int i; + volatile int *p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen = - 7); + + signal(SIGSEGV, execve_child_sigsegv_handler); + + /* This dereference should raise SIGSEGV. */ + return *p; +} + +static void test_fork_exec(void) +{ + int ret, status; + + ksft_print_msg("Testing fork/exec behavior\n"); + + ret =3D set_tagged_addr_ctrl(min_pmlen, false); + if (ret) + return ksft_test_result_error("setup (%d)\n", ret); + + if (fork()) { + wait(&status); + ksft_test_result(WIFEXITED(status) && WEXITSTATUS(status) =3D=3D 42, + "dereference after fork\n"); + } else { + static volatile int i =3D 42; + volatile int *p =3D (volatile int *)((uintptr_t)&i | 1UL << __riscv_xlen= - min_pmlen); + + /* This dereference should succeed. */ + exit(*p); + } + + if (fork()) { + wait(&status); + ksft_test_result(WIFEXITED(status) && WEXITSTATUS(status) =3D=3D 42, + "dereference after fork+exec\n"); + } else { + /* Will call execve_child(). */ + execve("/proc/self/exe", (char *const []) { "", NULL }, NULL); + } +} + +static void test_tagged_addr_abi_sysctl(void) +{ + char value; + int fd; + + ksft_print_msg("Testing tagged address ABI sysctl\n"); + + fd =3D open("/proc/sys/abi/tagged_addr_disabled", O_WRONLY); + if (fd < 0) { + ksft_test_result_skip("failed to open sysctl file\n"); + ksft_test_result_skip("failed to open sysctl file\n"); + return; + } + + value =3D '1'; + pwrite(fd, &value, 1, 0); + ksft_test_result(set_tagged_addr_ctrl(min_pmlen, true) =3D=3D -EINVAL, + "sysctl disabled\n"); + + value =3D '0'; + pwrite(fd, &value, 1, 0); + ksft_test_result(set_tagged_addr_ctrl(min_pmlen, true) =3D=3D 0, + "sysctl enabled\n"); + + set_tagged_addr_ctrl(0, false); + + close(fd); +} + +static void test_tagged_addr_abi_pmlen(int pmlen) +{ + int i, *p, ret; + + i =3D ~pmlen; + + if (pmlen) { + p =3D (int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen); + + ret =3D set_tagged_addr_ctrl(pmlen, false); + if (ret) + return ksft_test_result_error("PMLEN=3D%d ABI disabled setup (%d)\n", + pmlen, ret); + + ret =3D write(pipefd[1], p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled write\n", pmlen); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled read\n", pmlen); + + if (i !=3D ~pmlen) + return ksft_test_result_fail("PMLEN=3D%d ABI disabled value\n", pmlen); + + ret =3D set_tagged_addr_ctrl(pmlen, true); + if (ret) + return ksft_test_result_error("PMLEN=3D%d ABI enabled setup (%d)\n", + pmlen, ret); + + ret =3D write(pipefd[1], p, sizeof(*p)); + if (ret !=3D sizeof(*p)) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled write\n", pmlen); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret !=3D sizeof(*p)) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled read\n", pmlen); + + if (i) + return ksft_test_result_fail("PMLEN=3D%d ABI enabled value\n", pmlen); + + i =3D ~pmlen; + } else { + /* The tagged address ABI cannot be enabled when PMLEN =3D=3D 0. */ + ret =3D set_tagged_addr_ctrl(pmlen, true); + if (ret !=3D -EINVAL) + return ksft_test_result_error("PMLEN=3D%d ABI setup (%d)\n", + pmlen, ret); + } + + p =3D (int *)((uintptr_t)&i | 1UL << __riscv_xlen - pmlen - 1); + + ret =3D write(pipefd[1], p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d invalid tag write (%d)\n", pmle= n, errno); + + ret =3D read(dev_zero, p, sizeof(*p)); + if (ret >=3D 0 || errno !=3D EFAULT) + return ksft_test_result_fail("PMLEN=3D%d invalid tag read\n", pmlen); + + if (i !=3D ~pmlen) + return ksft_test_result_fail("PMLEN=3D%d invalid tag value\n", pmlen); + + ksft_test_result_pass("PMLEN=3D%d tagged address ABI\n", pmlen); +} + +static void test_tagged_addr_abi(void) +{ + ksft_print_msg("Testing tagged address ABI\n"); + + test_tagged_addr_abi_pmlen(0); + test_tagged_addr_abi_pmlen(min_pmlen); + test_tagged_addr_abi_pmlen(max_pmlen); +} + +static struct test_info { + unsigned int nr_tests; + void (*test_fn)(void); +} tests[] =3D { + { .nr_tests =3D 17 * 3, test_pmlen }, + { .nr_tests =3D 3, test_dereference }, + { .nr_tests =3D 2, test_fork_exec }, + { .nr_tests =3D 2, test_tagged_addr_abi_sysctl }, + { .nr_tests =3D 3, test_tagged_addr_abi }, +}; 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Tue, 25 Jun 2024 14:09:49 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb328f57sm85873455ad.110.2024.06.25.14.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 14:09:49 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , Samuel Holland Subject: [PATCH v2 08/10] riscv: hwprobe: Export the Supm ISA extension Date: Tue, 25 Jun 2024 14:09:19 -0700 Message-ID: <20240625210933.1620802-9-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Supm is a virtual ISA extension defined in the RISC-V Pointer Masking specification, which indicates that pointer masking is available in U-mode. It can be provided by either Smnpm or Ssnpm, depending on which mode the kernel runs in. Userspace should not care about this distinction, so export Supm instead of either underlying extension. Hide the extension if the kernel was compiled without support for pointer masking. Signed-off-by: Samuel Holland --- Changes in v2: - New patch for v2 Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 3 +++ 3 files changed, 7 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index fc015b452ebf..75fbefa0af26 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -207,6 +207,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension ma= nual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as + defined in version 1.0.0-rc2 of the RISC-V Pointer Masking manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 7b95fadbea2a..abb7725fd71b 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -65,6 +65,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) +#define RISCV_HWPROBE_EXT_SUPM (1ULL << 42) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 83fcc939df67..b4f4b6d93c00 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -142,6 +142,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZFHMIN); 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Shutemov" , Samuel Holland Subject: [PATCH v2 09/10] RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests Date: Tue, 25 Jun 2024 14:09:20 -0700 Message-ID: <20240625210933.1620802-10-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The interface for controlling pointer masking in VS-mode is henvcfg.PMM, which is part of the Ssnpm extension, even though pointer masking in HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm in the guest requires (only) Ssnpm on the host. Since the guest configures Smnpm through the SBI Firmware Features interface, the extension can be disabled by failing the SBI call. Ssnpm cannot be disabled without intercepting writes to the senvcfg CSR. Signed-off-by: Samuel Holland --- Changes in v2: - New patch for v2 arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu_onereg.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e878e7cc3978..eda2a54c93e3 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF, + KVM_RISCV_ISA_EXT_SMNPM, + KVM_RISCV_ISA_EXT_SSNPM, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index c676275ea0a0..71c6541d7070 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -34,9 +34,11 @@ static const unsigned long kvm_isa_ext_arr[] =3D { [KVM_RISCV_ISA_EXT_M] =3D RISCV_ISA_EXT_m, [KVM_RISCV_ISA_EXT_V] =3D RISCV_ISA_EXT_v, /* Multi letter extensions (alphabetically sorted) */ + [KVM_RISCV_ISA_EXT_SMNPM] =3D RISCV_ISA_EXT_SSNPM, KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), + KVM_ISA_EXT_ARR(SSNPM), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -122,6 +124,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned= long ext) case KVM_RISCV_ISA_EXT_M: /* There is not architectural config bit to disable sscofpmf completely */ case KVM_RISCV_ISA_EXT_SSCOFPMF: + case KVM_RISCV_ISA_EXT_SSNPM: case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: --=20 2.44.1 From nobody Wed Dec 17 21:15:11 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF63C1822D1 for ; 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Tue, 25 Jun 2024 14:09:53 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb328f57sm85873455ad.110.2024.06.25.14.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 14:09:52 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Anup Patel , Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , Samuel Holland Subject: [PATCH v2 10/10] KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test Date: Tue, 25 Jun 2024 14:09:21 -0700 Message-ID: <20240625210933.1620802-11-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.1 In-Reply-To: <20240625210933.1620802-1-samuel.holland@sifive.com> References: <20240625210933.1620802-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add testing for the pointer masking extensions exposed to KVM guests. Signed-off-by: Samuel Holland --- Changes in v2: - New patch for v2 tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 222198dd6d04..301761a5364d 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -41,9 +41,11 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _I: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _M: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _V: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SMNPM: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSCOFPMF: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSNPM: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _SVNAPOT: @@ -407,9 +409,11 @@ static const char *isa_ext_single_id_to_str(__u64 reg_= off) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SMNPM), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), + KVM_ISA_EXT_ARR(SSNPM), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -932,8 +936,10 @@ KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA); KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); +KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); +KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); @@ -988,8 +994,10 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_fp_f, &config_fp_d, &config_h, + &config_smnpm, &config_smstateen, &config_sscofpmf, + &config_ssnpm, &config_sstc, &config_svinval, &config_svnapot, --=20 2.44.1