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R. Silva" , Jonathan Corbet , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 2/2] RISC-V: hwprobe: Add SCALAR to misaligned perf defines Date: Tue, 25 Jun 2024 09:51:21 -0700 Message-Id: <20240625165121.2160354-3-evan@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625165121.2160354-1-evan@rivosinc.com> References: <20240625165121.2160354-1-evan@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for misaligned vector performance hwprobe keys, rename the hwprobe key values associated with misaligned scalar accesses to include the term SCALAR. Signed-off-by: Evan Green Reviewed-by: Charlie Jenkins --- Changes in v2: - Added patch to rename misaligned perf key values (Palmer) Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- arch/riscv/kernel/traps_misaligned.c | 6 +++--- arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ 5 files changed, 29 insertions(+), 29 deletions(-) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index c9f570b1ab60..83f7f3c1347f 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -215,22 +215,22 @@ The following keys are defined: the performance of misaligned scalar word accesses on the selected set of processors. =20 - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misali= gned - accesses is unknown. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of + misaligned accesses is unknown. =20 - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned access= es are emulated via software, either in or below the kernel. These accesses = are always extremely slow. =20 - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are - slower than equivalent byte accesses. Misaligned accesses may be supp= orted - directly in hardware, or trapped and emulated by software. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word acces= ses + are slower than equivalent byte accesses. Misaligned accesses may be + supported directly in hardware, or trapped and emulated by software. =20 - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are - faster than equivalent byte accesses. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word acces= ses + are faster than equivalent byte accesses. =20 - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses a= re - not supported at all and will generate a misaligned address fault. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned acc= esses + are not supported at all and will generate a misaligned address fault. =20 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 22073533cea8..e11684d8ae1c 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -66,11 +66,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 -#define RISCV_HWPROBE_MISALIGNED_FAST 3 -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 #define RISCV_HWPROBE_MISALIGNED_MASK 7 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 7 diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 991ceba67717..fbf952e7383e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -170,13 +170,13 @@ static u64 hwprobe_misaligned(const struct cpumask *c= pus) perf =3D this_perf; =20 if (perf !=3D this_perf) { - perf =3D RISCV_HWPROBE_MISALIGNED_UNKNOWN; + perf =3D RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; break; } } =20 if (perf =3D=3D -1ULL) - return RISCV_HWPROBE_MISALIGNED_UNKNOWN; + return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; =20 return perf; } @@ -184,12 +184,12 @@ static u64 hwprobe_misaligned(const struct cpumask *c= pus) static u64 hwprobe_misaligned(const struct cpumask *cpus) { if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS)) - return RISCV_HWPROBE_MISALIGNED_FAST; + return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; =20 if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_a= vailable()) - return RISCV_HWPROBE_MISALIGNED_EMULATED; + return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; =20 - return RISCV_HWPROBE_MISALIGNED_SLOW; + return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; } #endif =20 diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index b62d5a2f4541..192cd5603e95 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS - *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_EMUL= ATED; + *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_SCAL= AR_EMULATED; #endif =20 if (!unaligned_enabled) @@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu) unsigned long tmp_var, tmp_val; bool misaligned_emu_detected; =20 - *mas_ptr =3D RISCV_HWPROBE_MISALIGNED_UNKNOWN; + *mas_ptr =3D RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; =20 __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=3Dr" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); =20 - misaligned_emu_detected =3D (*mas_ptr =3D=3D RISCV_HWPROBE_MISALIGNED_EMU= LATED); + misaligned_emu_detected =3D (*mas_ptr =3D=3D RISCV_HWPROBE_MISALIGNED_SCA= LAR_EMULATED); /* * If unaligned_ctl is already set, this means that we detected that all * CPUS uses emulated misaligned access at boot time. If that changed diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index a9a6bcb02acf..160628a2116d 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -34,9 +34,9 @@ static int check_unaligned_access(void *param) struct page *page =3D param; void *dst; void *src; - long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; + long speed =3D RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; =20 - if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) + if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_S= CALAR_UNKNOWN) return 0; =20 /* Make an unaligned destination buffer. */ @@ -95,14 +95,14 @@ static int check_unaligned_access(void *param) } =20 if (word_cycles < byte_cycles) - speed =3D RISCV_HWPROBE_MISALIGNED_FAST; + speed =3D RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; =20 ratio =3D div_u64((byte_cycles * 100), word_cycles); pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.= %02d, unaligned accesses are %s\n", cpu, ratio / 100, ratio % 100, - (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); + (speed =3D=3D RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) ? "fast" : "slow"); =20 per_cpu(misaligned_access_speed, cpu) =3D speed; =20 @@ -110,7 +110,7 @@ static int check_unaligned_access(void *param) * Set the value of fast_misaligned_access of a CPU. These operations * are atomic to avoid race conditions. */ - if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) + if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) cpumask_set_cpu(cpu, &fast_misaligned_access); else cpumask_clear_cpu(cpu, &fast_misaligned_access); @@ -188,7 +188,7 @@ static int riscv_online_cpu(unsigned int cpu) static struct page *buf; =20 /* We are already set since the last check */ - if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_U= NKNOWN) + if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED_S= CALAR_UNKNOWN) goto exit; =20 buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); --=20 2.34.1