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Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ec1c10a12470..000037f4a712 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -895,6 +895,7 @@ properties: - items: - enum: - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 - const: qcom,sa8775p =20 - items: --=20 2.43.0 From nobody Wed Dec 17 19:20:55 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6D4217C7B0 for ; Tue, 25 Jun 2024 15:14:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 25 Jun 2024 08:14:44 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:dc:7e00:2b2c:4971:1887:588b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3663a2f694asm13215884f8f.77.2024.06.25.08.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 08:14:44 -0700 (PDT) From: Bartosz Golaszewski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v2 2/3] arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsi Date: Tue, 25 Jun 2024 17:14:29 +0200 Message-ID: <20240625151430.34024-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240625151430.34024-1-brgl@bgdev.pl> References: <20240625151430.34024-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski In order to support multiple revisions of the sa8775p-ride board, create a .dtsi containing the common parts and split out the ethernet bits into the actual board file as they will change in revision 3. Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 836 +-------------------- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 814 ++++++++++++++++++++ 2 files changed, 836 insertions(+), 814 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8775p-ride.dts index 26ad05bd3b3f..2e87fd760dbd 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,835 +5,43 @@ =20 /dts-v1/; =20 -#include -#include - -#include "sa8775p.dtsi" -#include "sa8775p-pmics.dtsi" +#include "sa8775p-ride.dtsi" =20 / { model =3D "Qualcomm SA8775P Ride"; compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; - - aliases { - ethernet0 =3D ðernet0; - ethernet1 =3D ðernet1; - i2c11 =3D &i2c11; - i2c18 =3D &i2c18; - serial0 =3D &uart10; - serial1 =3D &uart12; - serial2 =3D &uart17; - spi16 =3D &spi16; - ufshc1 =3D &ufs_mem_hc; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible =3D "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id =3D "a"; - - vreg_s4a: smps4 { - regulator-name =3D "vreg_s4a"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1816000>; - regulator-initial-mode =3D ; - }; - - vreg_s5a: smps5 { - regulator-name =3D "vreg_s5a"; - regulator-min-microvolt =3D <1850000>; - regulator-max-microvolt =3D <1996000>; - regulator-initial-mode =3D ; - }; - - vreg_s9a: smps9 { - regulator-name =3D "vreg_s9a"; - regulator-min-microvolt =3D <535000>; - regulator-max-microvolt =3D <1120000>; - regulator-initial-mode =3D ; - }; - - vreg_l4a: ldo4 { - regulator-name =3D "vreg_l4a"; - regulator-min-microvolt =3D <788000>; - regulator-max-microvolt =3D <1050000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l5a: ldo5 { - regulator-name =3D "vreg_l5a"; - regulator-min-microvolt =3D <870000>; - regulator-max-microvolt =3D <950000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l6a: ldo6 { - regulator-name =3D "vreg_l6a"; - regulator-min-microvolt =3D <870000>; - regulator-max-microvolt =3D <970000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l7a: ldo7 { - regulator-name =3D "vreg_l7a"; - regulator-min-microvolt =3D <720000>; - regulator-max-microvolt =3D <950000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l8a: ldo8 { - regulator-name =3D "vreg_l8a"; - regulator-min-microvolt =3D <2504000>; - regulator-max-microvolt =3D <3300000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l9a: ldo9 { - regulator-name =3D "vreg_l9a"; - regulator-min-microvolt =3D <2970000>; - regulator-max-microvolt =3D <3544000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - }; - - regulators-1 { - compatible =3D "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id =3D "c"; - - vreg_l1c: ldo1 { - regulator-name =3D "vreg_l1c"; - regulator-min-microvolt =3D <1140000>; - regulator-max-microvolt =3D <1260000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l2c: ldo2 { - regulator-name =3D "vreg_l2c"; - regulator-min-microvolt =3D <900000>; - regulator-max-microvolt =3D <1100000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l3c: ldo3 { - regulator-name =3D "vreg_l3c"; - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1300000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l4c: ldo4 { - regulator-name =3D "vreg_l4c"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - /* - * FIXME: This should have regulator-allow-set-load but - * we're getting an over-current fault from the PMIC - * when switching to LPM. - */ - }; - - vreg_l5c: ldo5 { - regulator-name =3D "vreg_l5c"; - regulator-min-microvolt =3D <1100000>; - regulator-max-microvolt =3D <1300000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l6c: ldo6 { - regulator-name =3D "vreg_l6c"; - regulator-min-microvolt =3D <1620000>; - regulator-max-microvolt =3D <1980000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l7c: ldo7 { - regulator-name =3D "vreg_l7c"; - regulator-min-microvolt =3D <1620000>; - regulator-max-microvolt =3D <2000000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l8c: ldo8 { - regulator-name =3D "vreg_l8c"; - regulator-min-microvolt =3D <2400000>; - regulator-max-microvolt =3D <3300000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l9c: ldo9 { - regulator-name =3D "vreg_l9c"; - regulator-min-microvolt =3D <1650000>; - regulator-max-microvolt =3D <2700000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - }; - - regulators-2 { - compatible =3D "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id =3D "e"; - - vreg_s4e: smps4 { - regulator-name =3D "vreg_s4e"; - regulator-min-microvolt =3D <970000>; - regulator-max-microvolt =3D <1520000>; - regulator-initial-mode =3D ; - }; - - vreg_s7e: smps7 { - regulator-name =3D "vreg_s7e"; - regulator-min-microvolt =3D <1010000>; - regulator-max-microvolt =3D <1170000>; - regulator-initial-mode =3D ; - }; - - vreg_s9e: smps9 { - regulator-name =3D "vreg_s9e"; - regulator-min-microvolt =3D <300000>; - regulator-max-microvolt =3D <570000>; - regulator-initial-mode =3D ; - }; - - vreg_l6e: ldo6 { - regulator-name =3D "vreg_l6e"; - regulator-min-microvolt =3D <1280000>; - regulator-max-microvolt =3D <1450000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l8e: ldo8 { - regulator-name =3D "vreg_l8e"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1950000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - }; }; =20 ðernet0 { phy-mode =3D "sgmii"; - phy-handle =3D <&sgmii_phy0>; - - pinctrl-0 =3D <ðernet0_default>; - pinctrl-names =3D "default"; - - snps,mtl-rx-config =3D <&mtl_rx_setup>; - snps,mtl-tx-config =3D <&mtl_tx_setup>; - snps,ps-speed =3D <1000>; - - status =3D "okay"; - - mdio { - compatible =3D "snps,dwmac-mdio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sgmii_phy0: phy@8 { - compatible =3D "ethernet-phy-id0141.0dd4"; - reg =3D <0x8>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; - - sgmii_phy1: phy@a { - compatible =3D "ethernet-phy-id0141.0dd4"; - reg =3D <0xa>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use =3D <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x0>; - snps,route-up; - snps,priority =3D <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x3>; - snps,priority =3D <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use =3D <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - }; }; =20 ðernet1 { phy-mode =3D "sgmii"; - phy-handle =3D <&sgmii_phy1>; +}; =20 - snps,mtl-rx-config =3D <&mtl_rx_setup1>; - snps,mtl-tx-config =3D <&mtl_tx_setup1>; - snps,ps-speed =3D <1000>; +&mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; =20 - status =3D "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use =3D <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x0>; - snps,route-up; - snps,priority =3D <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x3>; - snps,priority =3D <0xc>; - }; + sgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; }; =20 - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use =3D <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; + sgmii_phy1: phy@a { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0xa>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; }; }; - -&i2c11 { - clock-frequency =3D <400000>; - pinctrl-0 =3D <&qup_i2c11_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&i2c18 { - clock-frequency =3D <400000>; - pinctrl-0 =3D <&qup_i2c18_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&pmm8654au_0_gpios { - gpio-line-names =3D "DS_EN", - "POFF_COMPLETE", - "UFS0_VER_ID", - "FAST_POFF", - "DBU1_PON_DONE", - "AOSS_SLEEP", - "CAM_DES0_EN", - "CAM_DES1_EN", - "CAM_DES2_EN", - "CAM_DES3_EN", - "UEFI", - "ANALOG_PON_OPT"; -}; - -&pmm8654au_0_pon_resin { - linux,code =3D ; - status =3D "okay"; -}; - -&pmm8654au_1_gpios { - gpio-line-names =3D "PMIC_C_ID0", - "PMIC_C_ID1", - "UFS1_VER_ID", - "IPA_PWR", - "", - "WLAN_DBU4_EN", - "WLAN_EN", - "BT_EN", - "USB2_PWR_EN", - "USB2_FAULT"; - - usb2_en_state: usb2-en-state { - pins =3D "gpio9"; - function =3D "normal"; - output-high; - power-source =3D <0>; - }; -}; - -&pmm8654au_2_gpios { - gpio-line-names =3D "PMIC_E_ID0", - "PMIC_E_ID1", - "USB0_PWR_EN", - "USB0_FAULT", - "SENSOR_IRQ_1", - "SENSOR_IRQ_2", - "SENSOR_RST", - "SGMIIO0_RST", - "SGMIIO1_RST", - "USB1_PWR_ENABLE", - "USB1_FAULT", - "VMON_SPX8"; - - usb0_en_state: usb0-en-state { - pins =3D "gpio3"; - function =3D "normal"; - output-high; - power-source =3D <0>; - }; - - usb1_en_state: usb1-en-state { - pins =3D "gpio10"; - function =3D "normal"; - output-high; - power-source =3D <0>; - }; -}; - -&pmm8654au_3_gpios { - gpio-line-names =3D "PMIC_G_ID0", - "PMIC_G_ID1", - "GNSS_RST", - "GNSS_EN", - "GNSS_BOOT_MODE"; -}; - -&qupv3_id_1 { - status =3D "okay"; -}; - -&qupv3_id_2 { - status =3D "okay"; -}; - -&serdes0 { - phy-supply =3D <&vreg_l5a>; - status =3D "okay"; -}; - -&serdes1 { - phy-supply =3D <&vreg_l5a>; - status =3D "okay"; -}; - -&sleep_clk { - clock-frequency =3D <32764>; -}; - -&spi16 { - pinctrl-0 =3D <&qup_spi16_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&tlmm { - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins =3D "gpio8"; - function =3D "emac0_mdc"; - drive-strength =3D <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins =3D "gpio9"; - function =3D "emac0_mdio"; - drive-strength =3D <16>; - bias-pull-up; - }; - }; - - qup_uart10_default: qup-uart10-state { - pins =3D "gpio46", "gpio47"; - function =3D "qup1_se3"; - }; - - qup_spi16_default: qup-spi16-state { - pins =3D "gpio86", "gpio87", "gpio88", "gpio89"; - function =3D "qup2_se2"; - drive-strength =3D <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-state { - pins =3D "gpio48", "gpio49"; - function =3D "qup1_se4"; - drive-strength =3D <2>; - bias-pull-up; - }; - - qup_i2c18_default: qup-i2c18-state { - pins =3D "gpio95", "gpio96"; - function =3D "qup2_se4"; - drive-strength =3D <2>; - bias-pull-up; - }; - - qup_uart12_default: qup-uart12-state { - qup_uart12_cts: qup-uart12-cts-pins { - pins =3D "gpio52"; - function =3D "qup1_se5"; - bias-disable; - }; - - qup_uart12_rts: qup-uart12-rts-pins { - pins =3D "gpio53"; - function =3D "qup1_se5"; - bias-pull-down; - }; - - qup_uart12_tx: qup-uart12-tx-pins { - pins =3D "gpio54"; - function =3D "qup1_se5"; - bias-pull-up; - }; - - qup_uart12_rx: qup-uart12-rx-pins { - pins =3D "gpio55"; - function =3D "qup1_se5"; - bias-pull-down; - }; - }; - - qup_uart17_default: qup-uart17-state { - qup_uart17_cts: qup-uart17-cts-pins { - pins =3D "gpio91"; - function =3D "qup2_se3"; - bias-disable; - }; - - qup_uart17_rts: qup0-uart17-rts-pins { - pins =3D "gpio92"; - function =3D "qup2_se3"; - bias-pull-down; - }; - - qup_uart17_tx: qup0-uart17-tx-pins { - pins =3D "gpio93"; - function =3D "qup2_se3"; - bias-pull-up; - }; - - qup_uart17_rx: qup0-uart17-rx-pins { - pins =3D "gpio94"; - function =3D "qup2_se3"; - bias-pull-down; - }; - }; - - pcie0_default_state: pcie0-default-state { - perst-pins { - pins =3D "gpio2"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-down; - }; - - clkreq-pins { - pins =3D "gpio1"; - function =3D "pcie0_clkreq"; - drive-strength =3D <2>; - bias-pull-up; - }; - - wake-pins { - pins =3D "gpio0"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default-state { - perst-pins { - pins =3D "gpio4"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-down; - }; - - clkreq-pins { - pins =3D "gpio3"; - function =3D "pcie1_clkreq"; - drive-strength =3D <2>; - bias-pull-up; - }; - - wake-pins { - pins =3D "gpio5"; - function =3D "gpio"; - drive-strength =3D <2>; - bias-pull-up; - }; - }; -}; - -&pcie0 { - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie0_default_state>; - - status =3D "okay"; -}; - -&pcie1 { - perst-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pcie1_default_state>; - - status =3D "okay"; -}; - -&pcie0_phy { - vdda-phy-supply =3D <&vreg_l5a>; - vdda-pll-supply =3D <&vreg_l1c>; - - status =3D "okay"; -}; - -&pcie1_phy { - vdda-phy-supply =3D <&vreg_l5a>; - vdda-pll-supply =3D <&vreg_l1c>; - - status =3D "okay"; -}; - -&uart10 { - compatible =3D "qcom,geni-debug-uart"; - pinctrl-0 =3D <&qup_uart10_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&uart12 { - pinctrl-0 =3D <&qup_uart12_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&uart17 { - pinctrl-0 =3D <&qup_uart17_default>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - -&ufs_mem_hc { - reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; - vcc-supply =3D <&vreg_l8a>; - vcc-max-microamp =3D <1100000>; - vccq-supply =3D <&vreg_l4c>; - vccq-max-microamp =3D <1200000>; - - status =3D "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply =3D <&vreg_l4a>; - vdda-pll-supply =3D <&vreg_l1c>; - - status =3D "okay"; -}; - -&usb_0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&usb0_en_state>; - - status =3D "okay"; -}; - -&usb_0_dwc3 { - dr_mode =3D "peripheral"; -}; - -&usb_0_hsphy { - vdda-pll-supply =3D <&vreg_l7a>; - vdda18-supply =3D <&vreg_l6c>; - vdda33-supply =3D <&vreg_l9a>; - - status =3D "okay"; -}; - -&usb_0_qmpphy { - vdda-phy-supply =3D <&vreg_l1c>; - vdda-pll-supply =3D <&vreg_l7a>; - - status =3D "okay"; -}; - -&usb_1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&usb1_en_state>; - - status =3D "okay"; -}; - -&usb_1_dwc3 { - dr_mode =3D "host"; -}; - -&usb_1_hsphy { - vdda-pll-supply =3D <&vreg_l7a>; - vdda18-supply =3D <&vreg_l6c>; - vdda33-supply =3D <&vreg_l9a>; - - status =3D "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply =3D <&vreg_l1c>; - vdda-pll-supply =3D <&vreg_l7a>; - - status =3D "okay"; -}; - -&usb_2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&usb2_en_state>; - - status =3D "okay"; -}; - -&usb_2_dwc3 { - dr_mode =3D "host"; -}; - -&usb_2_hsphy { - vdda-pll-supply =3D <&vreg_l7a>; - vdda18-supply =3D <&vreg_l6c>; - vdda33-supply =3D <&vreg_l9a>; - - status =3D "okay"; -}; - -&xo_board_clk { - clock-frequency =3D <38400000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi new file mode 100644 index 000000000000..2a6170623ea9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include + +#include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" + +/ { + aliases { + ethernet0 =3D ðernet0; + ethernet1 =3D ðernet1; + i2c11 =3D &i2c11; + i2c18 =3D &i2c18; + serial0 =3D &uart10; + serial1 =3D &uart12; + serial2 =3D &uart17; + spi16 =3D &spi16; + ufshc1 =3D &ufs_mem_hc; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1816000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1850000>; + regulator-max-microvolt =3D <1996000>; + regulator-initial-mode =3D ; + }; + + vreg_s9a: smps9 { + regulator-name =3D "vreg_s9a"; + regulator-min-microvolt =3D <535000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <788000>; + regulator-max-microvolt =3D <1050000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c: ldo3 { + regulator-name =3D "vreg_l3c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name =3D "vreg_l5c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vreg_s4e: smps4 { + regulator-name =3D "vreg_s4e"; + regulator-min-microvolt =3D <970000>; + regulator-max-microvolt =3D <1520000>; + regulator-initial-mode =3D ; + }; + + vreg_s7e: smps7 { + regulator-name =3D "vreg_s7e"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1170000>; + regulator-initial-mode =3D ; + }; + + vreg_s9e: smps9 { + regulator-name =3D "vreg_s9e"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_l6e: ldo6 { + regulator-name =3D "vreg_l6e"; + regulator-min-microvolt =3D <1280000>; + regulator-max-microvolt =3D <1450000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8e: ldo8 { + regulator-name =3D "vreg_l8e"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +ðernet0 { + phy-handle =3D <&sgmii_phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle =3D <&sgmii_phy1>; + + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&i2c11 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&qup_i2c11_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&i2c18 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&qup_i2c18_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&pmm8654au_0_gpios { + gpio-line-names =3D "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_0_pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&pmm8654au_1_gpios { + gpio-line-names =3D "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; + + usb2_en_state: usb2-en-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; + +&pmm8654au_2_gpios { + gpio-line-names =3D "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; + + usb0_en_state: usb0-en-state { + pins =3D "gpio3"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; + + usb1_en_state: usb1-en-state { + pins =3D "gpio10"; + function =3D "normal"; + output-high; + power-source =3D <0>; + }; +}; + +&pmm8654au_3_gpios { + gpio-line-names =3D "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&qupv3_id_2 { + status =3D "okay"; +}; + +&serdes0 { + phy-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&serdes1 { + phy-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&spi16 { + pinctrl-0 =3D <&qup_spi16_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio8"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio9"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + qup_uart10_default: qup-uart10-state { + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se3"; + }; + + qup_spi16_default: qup-spi16-state { + pins =3D "gpio86", "gpio87", "gpio88", "gpio89"; + function =3D "qup2_se2"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_i2c11_default: qup-i2c11-state { + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-state { + pins =3D "gpio95", "gpio96"; + function =3D "qup2_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins =3D "gpio52"; + function =3D "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins =3D "gpio53"; + function =3D "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins =3D "gpio54"; + function =3D "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins =3D "gpio55"; + function =3D "qup1_se5"; + bias-pull-down; + }; + }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins =3D "gpio91"; + function =3D "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins =3D "gpio92"; + function =3D "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins =3D "gpio93"; + function =3D "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins =3D "gpio94"; + function =3D "qup2_se3"; + bias-pull-down; + }; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio3"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_state>; + + status =3D "okay"; +}; + +&pcie1 { + perst-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_state>; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&uart10 { + compatible =3D "qcom,geni-debug-uart"; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart12 { + pinctrl-0 =3D <&qup_uart12_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart17 { + pinctrl-0 =3D <&qup_uart17_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l8a>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l4c>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l1c>; + + status =3D "okay"; +}; + +&usb_0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb0_en_state>; + + status =3D "okay"; +}; + +&usb_0_dwc3 { + dr_mode =3D "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l6c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l7a>; + + status =3D "okay"; +}; + +&usb_1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb1_en_state>; + + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l6c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l1c>; + vdda-pll-supply =3D <&vreg_l7a>; + + status =3D "okay"; +}; + +&usb_2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb2_en_state>; + + status =3D "okay"; +}; + +&usb_2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_2_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l6c>; 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charset="utf-8" From: Bartosz Golaszewski Revision 3 of the sa8775p-ride board uses a different PHY for the two ethernet ports and supports 2.5G speed. Create a new file for the board reflecting the changes. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 47 ++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5576c7d6ea06..8b7a81b82213 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-acer-aspire1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sc7180-trogdor-coachz-r1.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot= /dts/qcom/sa8775p-ride-r3.dts new file mode 100644 index 000000000000..d214a87d69b2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p-ride.dtsi" + +/ { + model =3D "Qualcomm SA8775P Ride Rev3"; + compatible =3D "qcom,sa8775p-ride-r3", "qcom,sa8775p"; +}; + +ðernet0 { + phy-mode =3D "ocsgmii"; +}; + +ðernet1 { + phy-mode =3D "ocsgmii"; +}; + +&mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id31c3.1c33"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + + sgmii_phy1: phy@0 { + compatible =3D "ethernet-phy-id31c3.1c33"; + reg =3D <0x0>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; +}; --=20 2.43.0