From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 44C5F14F9E0; Tue, 25 Jun 2024 13:32:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322342; cv=none; b=fnRXdyOiRiRV8RU3CjPONdhVSHNPIcUU2DxO2d7qfmyUHJgBQRk/ed+2DhQT7/wpjV/DufH30hl/bJ8D3dzFcwThQprtOOgRbf6+2k6DzAhc0TAnqety7edho44RGFoEtG6lJUSHp6JSPo3wA3/7pPTSqiAcVOgoX+l0Ql/ydZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322342; c=relaxed/simple; bh=S+3M+P7EydDYx1VSdqESFH1tohdKDaVHTpOBTv5Xols=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UJPo2xAo8WtwAcmvnnAKDUkwftRIIVzysbVKMcjkL49AU2sQuhkOToC+Q+MWlaESFAaLeIMyNzXtNEaH61ooV/7J6wMAavIUmgnudlM9U5i5mZdT/tE4+B+ZTKtp3UppQ6S/R9ueKH3umoMSC+/0qGGgpaIMYd/DBefmhlBhXTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77F1ADA7; Tue, 25 Jun 2024 06:32:44 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2F4733F73B; Tue, 25 Jun 2024 06:32:16 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 01/17] perf: cs-etm: Create decoders after both AUX and HW_ID search passes Date: Tue, 25 Jun 2024 14:30:44 +0100 Message-Id: <20240625133105.671245-2-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both of these passes gather information about how to create the decoders. AUX records determine formatted/unformatted, and the HW_IDs determine the traceID/metadata mappings. Therefore it makes sense to cache the information and wait until both passes are over until creating the decoders, rather than creating them at the first HW_ID found. This will allow a simplification of the creation process where cs_etm_queue->traceid_list will exclusively used to create the decoders, rather than the current two methods depending on whether the trace is formatted or not. Previously the sample CPU from the AUX record was used to initialize the decoder CPU, but actually sample CPU =3D=3D AUX queue index in per-CPU mode, so saving the sample CPU isn't required. Similarly formatted/unformatted was used upfront to create the decoders, but now it's cached until later. Signed-off-by: James Clark --- tools/perf/util/cs-etm.c | 167 ++++++++++++++++++++++++--------------- 1 file changed, 102 insertions(+), 65 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 32818bd7cd17..f09004c4ba44 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -103,6 +103,7 @@ struct cs_etm_queue { struct auxtrace_buffer *buffer; unsigned int queue_nr; u8 pending_timestamp_chan_id; + bool formatted; u64 offset; const unsigned char *buf; size_t buf_len, buf_used; @@ -738,8 +739,7 @@ static int cs_etm__init_trace_params(struct cs_etm_trac= e_params *t_params, =20 static int cs_etm__init_decoder_params(struct cs_etm_decoder_params *d_par= ams, struct cs_etm_queue *etmq, - enum cs_etm_decoder_operation mode, - bool formatted) + enum cs_etm_decoder_operation mode) { int ret =3D -EINVAL; =20 @@ -749,7 +749,7 @@ static int cs_etm__init_decoder_params(struct cs_etm_de= coder_params *d_params, d_params->packet_printer =3D cs_etm__packet_dump; d_params->operation =3D mode; d_params->data =3D etmq; - d_params->formatted =3D formatted; + d_params->formatted =3D etmq->formatted; d_params->fsyncs =3D false; d_params->hsyncs =3D false; d_params->frame_aligned =3D true; @@ -1041,81 +1041,34 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *= etmq, u8 trace_chan_id, return ret; } =20 -static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *et= m, - bool formatted, int sample_cpu) +static struct cs_etm_queue *cs_etm__alloc_queue(void) { - struct cs_etm_decoder_params d_params; - struct cs_etm_trace_params *t_params =3D NULL; - struct cs_etm_queue *etmq; - /* - * Each queue can only contain data from one CPU when unformatted, so onl= y one decoder is - * needed. - */ - int decoders =3D formatted ? etm->num_cpu : 1; - - etmq =3D zalloc(sizeof(*etmq)); + struct cs_etm_queue *etmq =3D zalloc(sizeof(*etmq)); if (!etmq) return NULL; =20 etmq->traceid_queues_list =3D intlist__new(NULL); if (!etmq->traceid_queues_list) - goto out_free; - - /* Use metadata to fill in trace parameters for trace decoder */ - t_params =3D zalloc(sizeof(*t_params) * decoders); + free(etmq); =20 - if (!t_params) - goto out_free; - - if (cs_etm__init_trace_params(t_params, etm, formatted, sample_cpu, decod= ers)) - goto out_free; - - /* Set decoder parameters to decode trace packets */ - if (cs_etm__init_decoder_params(&d_params, etmq, - dump_trace ? CS_ETM_OPERATION_PRINT : - CS_ETM_OPERATION_DECODE, - formatted)) - goto out_free; - - etmq->decoder =3D cs_etm_decoder__new(decoders, &d_params, - t_params); - - if (!etmq->decoder) - goto out_free; - - /* - * Register a function to handle all memory accesses required by - * the trace decoder library. - */ - if (cs_etm_decoder__add_mem_access_cb(etmq->decoder, - 0x0L, ((u64) -1L), - cs_etm__mem_access)) - goto out_free_decoder; - - zfree(&t_params); return etmq; - -out_free_decoder: - cs_etm_decoder__free(etmq->decoder); -out_free: - intlist__delete(etmq->traceid_queues_list); - free(etmq); - - return NULL; } =20 static int cs_etm__setup_queue(struct cs_etm_auxtrace *etm, struct auxtrace_queue *queue, - unsigned int queue_nr, - bool formatted, - int sample_cpu) + unsigned int queue_nr, bool formatted) { struct cs_etm_queue *etmq =3D queue->priv; =20 + if (etmq && formatted !=3D etmq->formatted) { + pr_err("CS_ETM: mixed formatted and unformatted trace not supported\n"); + return -EINVAL; + } + if (list_empty(&queue->head) || etmq) return 0; =20 - etmq =3D cs_etm__alloc_queue(etm, formatted, sample_cpu); + etmq =3D cs_etm__alloc_queue(); =20 if (!etmq) return -ENOMEM; @@ -1123,7 +1076,9 @@ static int cs_etm__setup_queue(struct cs_etm_auxtrace= *etm, queue->priv =3D etmq; etmq->etm =3D etm; etmq->queue_nr =3D queue_nr; + queue->cpu =3D queue_nr; /* Placeholder, may be reset to -1 in per-thread= mode */ etmq->offset =3D 0; + etmq->formatted =3D formatted; =20 return 0; } @@ -2843,7 +2798,7 @@ static int cs_etm__process_auxtrace_event(struct perf= _session *session, * formatted in piped mode (true). */ err =3D cs_etm__setup_queue(etm, &etm->queues.queue_array[idx], - idx, true, -1); + idx, true); if (err) return err; =20 @@ -3048,8 +3003,8 @@ static int cs_etm__queue_aux_fragment(struct perf_ses= sion *session, off_t file_o =20 idx =3D auxtrace_event->idx; formatted =3D !(aux_event->flags & PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); - return cs_etm__setup_queue(etm, &etm->queues.queue_array[idx], - idx, formatted, sample->cpu); + + return cs_etm__setup_queue(etm, &etm->queues.queue_array[idx], idx, form= atted); } =20 /* Wasn't inside this buffer, but there were no parse errors. 1 =3D=3D 'n= ot found' */ @@ -3233,6 +3188,84 @@ static int cs_etm__clear_unused_trace_ids_metadata(i= nt num_cpu, u64 **metadata) return 0; } =20 +/* + * Use the data gathered by the peeks for HW_ID (trace ID mappings) and AUX + * (formatted or not) packets to create the decoders. + */ +static int cs_etm__create_queue_decoders(struct cs_etm_queue *etmq) +{ + struct cs_etm_decoder_params d_params; + + /* + * Each queue can only contain data from one CPU when unformatted, so onl= y one decoder is + * needed. + */ + int decoders =3D etmq->formatted ? etmq->etm->num_cpu : 1; + + /* Use metadata to fill in trace parameters for trace decoder */ + struct cs_etm_trace_params *t_params =3D zalloc(sizeof(*t_params) * deco= ders); + + if (!t_params) + goto out_free; + + if (cs_etm__init_trace_params(t_params, etmq->etm, etmq->formatted, + etmq->queue_nr, decoders)) + goto out_free; + + /* Set decoder parameters to decode trace packets */ + if (cs_etm__init_decoder_params(&d_params, etmq, + dump_trace ? CS_ETM_OPERATION_PRINT : + CS_ETM_OPERATION_DECODE)) + goto out_free; + + etmq->decoder =3D cs_etm_decoder__new(decoders, &d_params, + t_params); + + if (!etmq->decoder) + goto out_free; + + /* + * Register a function to handle all memory accesses required by + * the trace decoder library. + */ + if (cs_etm_decoder__add_mem_access_cb(etmq->decoder, + 0x0L, ((u64) -1L), + cs_etm__mem_access)) + goto out_free_decoder; + + zfree(&t_params); + return 0; + +out_free_decoder: + cs_etm_decoder__free(etmq->decoder); +out_free: + zfree(&t_params); + return -EINVAL; +} + +static int cs_etm__create_decoders(struct cs_etm_auxtrace *etm) +{ + struct auxtrace_queues *queues =3D &etm->queues; + + for (unsigned int i =3D 0; i < queues->nr_queues; i++) { + bool empty =3D list_empty(&queues->queue_array[i].head); + struct cs_etm_queue *etmq =3D queues->queue_array[i].priv; + int ret; + + /* + * Don't create decoders for empty queues, mainly because + * etmq->formatted is unknown for empty queues. + */ + if (empty) + continue; + + ret =3D cs_etm__create_queue_decoders(etmq); + if (ret) + return ret; + } + return 0; +} + int cs_etm__process_auxtrace_info_full(union perf_event *event, struct perf_session *session) { @@ -3396,6 +3429,10 @@ int cs_etm__process_auxtrace_info_full(union perf_ev= ent *event, if (err) goto err_free_queues; =20 + err =3D cs_etm__queue_aux_records(session); + if (err) + goto err_free_queues; + /* * Map Trace ID values to CPU metadata. * @@ -3418,7 +3455,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, * flags if present. */ =20 - /* first scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU = metadata */ + /* Scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU metada= ta */ aux_hw_id_found =3D 0; err =3D perf_session__peek_events(session, session->header.data_offset, session->header.data_size, @@ -3436,7 +3473,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, if (err) goto err_free_queues; =20 - err =3D cs_etm__queue_aux_records(session); + err =3D cs_etm__create_decoders(etm); if (err) goto err_free_queues; =20 --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DE7AA15FA74; Tue, 25 Jun 2024 13:32:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322350; cv=none; b=JomcdtETbynTL+7QLnLrn30DTYw0CYQy1QkAuwCTx7hHeyzMF/KN1XF/05v5HQCp6tcgWU46PpySscDhzqqJGspKs2rB4d7ajVKy8vXe8mN3pGNkN0PU+GOfQ7mB6SwFuDF+EoGWaxoJsJuzTniXQXLEnPgMBvXfT5HaaPEY3eY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322350; c=relaxed/simple; bh=s4r6cbrh972BjS7NDNvJSGqER/fgktiqUPF6kh9zjDQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m4isito/mZ63Tu/cOq8nqyn9uai5A9rhDn477prDhjbJQixcWgBy1mSqIz+iutaQiKbNLAZpsc6fJuJSoFyjyejGm1X0rv2C8gxiUZ/4V0vRNfieAbP9f0jxkKNSnmYU9MX8V8xoPStMGiJp4uotgo4J4ft00VQOFLfPSPE3HqI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 523C6DA7; Tue, 25 Jun 2024 06:32:53 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 977D73F73B; Tue, 25 Jun 2024 06:32:24 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 02/17] perf: cs-etm: Allocate queues for all CPUs Date: Tue, 25 Jun 2024 14:30:45 +0100 Message-Id: <20240625133105.671245-3-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make cs_etm__setup_queue() setup a queue even if it's empty, and pre-allocate queues based on the max CPU that was recorded. In per-CPU mode aux queues are indexed based on CPU ID even if all CPUs aren't recorded, sparse queue arrays aren't used. This will allow HW_IDs to be saved even if no aux data was received in that queue without having to call cs_etm__setup_queue() from two different places. Signed-off-by: James Clark --- tools/perf/util/cs-etm.c | 76 +++++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 36 deletions(-) diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index f09004c4ba44..1a95c4bb898f 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -97,13 +97,19 @@ struct cs_etm_traceid_queue { struct cs_etm_packet_queue packet_queue; }; =20 +enum cs_etm_format { + UNSET, + FORMATTED, + UNFORMATTED +}; + struct cs_etm_queue { struct cs_etm_auxtrace *etm; struct cs_etm_decoder *decoder; struct auxtrace_buffer *buffer; unsigned int queue_nr; u8 pending_timestamp_chan_id; - bool formatted; + enum cs_etm_format format; u64 offset; const unsigned char *buf; size_t buf_len, buf_used; @@ -697,7 +703,7 @@ static void cs_etm__set_trace_param_ete(struct cs_etm_t= race_params *t_params, =20 static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, struct cs_etm_auxtrace *etm, - bool formatted, + enum cs_etm_format format, int sample_cpu, int decoders) { @@ -706,7 +712,7 @@ static int cs_etm__init_trace_params(struct cs_etm_trac= e_params *t_params, u64 architecture; =20 for (t_idx =3D 0; t_idx < decoders; t_idx++) { - if (formatted) + if (format =3D=3D FORMATTED) m_idx =3D t_idx; else { m_idx =3D get_cpu_data_idx(etm, sample_cpu); @@ -749,7 +755,7 @@ static int cs_etm__init_decoder_params(struct cs_etm_de= coder_params *d_params, d_params->packet_printer =3D cs_etm__packet_dump; d_params->operation =3D mode; d_params->data =3D etmq; - d_params->formatted =3D etmq->formatted; + d_params->formatted =3D etmq->format =3D=3D FORMATTED; d_params->fsyncs =3D false; d_params->hsyncs =3D false; d_params->frame_aligned =3D true; @@ -1056,16 +1062,11 @@ static struct cs_etm_queue *cs_etm__alloc_queue(voi= d) =20 static int cs_etm__setup_queue(struct cs_etm_auxtrace *etm, struct auxtrace_queue *queue, - unsigned int queue_nr, bool formatted) + unsigned int queue_nr) { struct cs_etm_queue *etmq =3D queue->priv; =20 - if (etmq && formatted !=3D etmq->formatted) { - pr_err("CS_ETM: mixed formatted and unformatted trace not supported\n"); - return -EINVAL; - } - - if (list_empty(&queue->head) || etmq) + if (etmq) return 0; =20 etmq =3D cs_etm__alloc_queue(); @@ -1078,7 +1079,6 @@ static int cs_etm__setup_queue(struct cs_etm_auxtrace= *etm, etmq->queue_nr =3D queue_nr; queue->cpu =3D queue_nr; /* Placeholder, may be reset to -1 in per-thread= mode */ etmq->offset =3D 0; - etmq->formatted =3D formatted; =20 return 0; } @@ -2791,17 +2791,6 @@ static int cs_etm__process_auxtrace_event(struct per= f_session *session, if (err) return err; =20 - /* - * Knowing if the trace is formatted or not requires a lookup of - * the aux record so only works in non-piped mode where data is - * queued in cs_etm__queue_aux_records(). Always assume - * formatted in piped mode (true). - */ - err =3D cs_etm__setup_queue(etm, &etm->queues.queue_array[idx], - idx, true); - if (err) - return err; - if (dump_trace) if (auxtrace_buffer__get_data(buffer, fd)) { cs_etm__dump_event(etm->queues.queue_array[idx].priv, buffer); @@ -2918,8 +2907,7 @@ static int cs_etm__queue_aux_fragment(struct perf_ses= sion *session, off_t file_o struct perf_record_auxtrace *auxtrace_event; union perf_event auxtrace_fragment; __u64 aux_offset, aux_size; - __u32 idx; - bool formatted; + enum cs_etm_format format; =20 struct cs_etm_auxtrace *etm =3D container_of(session->auxtrace, struct cs_etm_auxtrace, @@ -2985,6 +2973,8 @@ static int cs_etm__queue_aux_fragment(struct perf_ses= sion *session, off_t file_o =20 if (aux_offset >=3D auxtrace_event->offset && aux_offset + aux_size <=3D auxtrace_event->offset + auxtrace_event->s= ize) { + struct cs_etm_queue *etmq =3D etm->queues.queue_array[auxtrace_event->id= x].priv; + /* * If this AUX event was inside this buffer somewhere, create a new auxt= race event * based on the sizes of the aux event, and queue that fragment. @@ -3001,10 +2991,14 @@ static int cs_etm__queue_aux_fragment(struct perf_s= ession *session, off_t file_o if (err) return err; =20 - idx =3D auxtrace_event->idx; - formatted =3D !(aux_event->flags & PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW); - - return cs_etm__setup_queue(etm, &etm->queues.queue_array[idx], idx, form= atted); + format =3D (aux_event->flags & PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW) ? + UNFORMATTED : FORMATTED; + if (etmq->format !=3D UNSET && format !=3D etmq->format) { + pr_err("CS_ETM: mixed formatted and unformatted trace not supported\n"); + return -EINVAL; + } + etmq->format =3D format; + return 0; } =20 /* Wasn't inside this buffer, but there were no parse errors. 1 =3D=3D 'n= ot found' */ @@ -3200,7 +3194,7 @@ static int cs_etm__create_queue_decoders(struct cs_et= m_queue *etmq) * Each queue can only contain data from one CPU when unformatted, so onl= y one decoder is * needed. */ - int decoders =3D etmq->formatted ? etmq->etm->num_cpu : 1; + int decoders =3D etmq->format =3D=3D FORMATTED ? etmq->etm->num_cpu : 1; =20 /* Use metadata to fill in trace parameters for trace decoder */ struct cs_etm_trace_params *t_params =3D zalloc(sizeof(*t_params) * deco= ders); @@ -3208,7 +3202,7 @@ static int cs_etm__create_queue_decoders(struct cs_et= m_queue *etmq) if (!t_params) goto out_free; =20 - if (cs_etm__init_trace_params(t_params, etmq->etm, etmq->formatted, + if (cs_etm__init_trace_params(t_params, etmq->etm, etmq->format, etmq->queue_nr, decoders)) goto out_free; =20 @@ -3256,6 +3250,7 @@ static int cs_etm__create_decoders(struct cs_etm_auxt= race *etm) * Don't create decoders for empty queues, mainly because * etmq->formatted is unknown for empty queues. */ + assert(empty =3D=3D (etmq->format =3D=3D UNSET)); if (empty) continue; =20 @@ -3275,10 +3270,10 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, int event_header_size =3D sizeof(struct perf_event_header); int total_size =3D auxtrace_info->header.size; int priv_size =3D 0; - int num_cpu; + int num_cpu, max_cpu =3D 0; int err =3D 0; int aux_hw_id_found; - int i, j; + int i; u64 *ptr =3D NULL; u64 **metadata =3D NULL; =20 @@ -3309,7 +3304,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, * required by the trace decoder to properly decode the trace due * to its highly compressed nature. */ - for (j =3D 0; j < num_cpu; j++) { + for (int j =3D 0; j < num_cpu; j++) { if (ptr[i] =3D=3D __perf_cs_etmv3_magic) { metadata[j] =3D cs_etm__create_meta_blk(ptr, &i, @@ -3333,6 +3328,9 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, err =3D -ENOMEM; goto err_free_metadata; } + + if ((int) metadata[j][CS_ETM_CPU] > max_cpu) + max_cpu =3D metadata[j][CS_ETM_CPU]; } =20 /* @@ -3362,10 +3360,16 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, */ etm->pid_fmt =3D cs_etm__init_pid_fmt(metadata[0]); =20 - err =3D auxtrace_queues__init(&etm->queues); + err =3D auxtrace_queues__init_nr(&etm->queues, max_cpu + 1); if (err) goto err_free_etm; =20 + for (unsigned int j =3D 0; j < etm->queues.nr_queues; ++j) { + err =3D cs_etm__setup_queue(etm, &etm->queues.queue_array[j], j); + if (err) + goto err_free_queues; + } + if (session->itrace_synth_opts->set) { etm->synth_opts =3D *session->itrace_synth_opts; } else { @@ -3487,7 +3491,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, zfree(&etm); err_free_metadata: /* No need to check @metadata[j], free(NULL) is supported */ - for (j =3D 0; j < num_cpu; j++) + for (int j =3D 0; j < num_cpu; j++) zfree(&metadata[j]); zfree(&metadata); err_free_traceid_list: --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3DCCB158D83; Tue, 25 Jun 2024 13:32:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322362; cv=none; b=O4iM7FiLNn619MsA6bemqi+XaiBgNHoDvAPFnjrKDtZJh6Fvq8Yoflim1gZgI1wdga/g0G0QYGqhCWyZB3wbjB0uLFh+slsSU5ufYBH4Y/pXzx5vpfllxFARPWdhadLRN1Hkj8IjC+kB31gX2j19tC/i536UN0htmagA8pAjopc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322362; c=relaxed/simple; bh=qoeQqkIy0BU9+pL+dHJUasFXtFRJZMk/1x6V1zh82/A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z2ClnWSvQ3gJF9m76EchWKUiweS6DX/nBhgnkgE029Z1DDWuT++/QFdPP3wpRr4M4+QS2DGzP4XVFdWsP/N8yFNyCOr+MfkyOCOkVxTfgu66KJDRFaV6b2yHXDDNLdB2dmddLj2sgIukhs/aBVYC6glo8BSv1dDq8KWC1xKja7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6CFD3DA7; Tue, 25 Jun 2024 06:33:04 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B697B3F73B; Tue, 25 Jun 2024 06:32:33 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 03/17] perf: cs-etm: Move traceid_list to each queue Date: Tue, 25 Jun 2024 14:30:46 +0100 Message-Id: <20240625133105.671245-4-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global list won't work for per-sink trace ID allocations, so put a list in each queue where the IDs will be unique to that queue. To keep the same behavior as before, for version 0 of the HW_ID packets, copy all the HW_ID mappings into all queues. This change doesn't effect the decoders, only trace ID lookups on the Perf side. The decoders are still created with global mappings which will be fixed in a later commit. Signed-off-by: James Clark --- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 28 ++- tools/perf/util/cs-etm.c | 215 +++++++++++------- tools/perf/util/cs-etm.h | 2 +- 3 files changed, 147 insertions(+), 98 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.c index e917985bbbe6..0c9c48cedbf1 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -388,7 +388,8 @@ cs_etm_decoder__reset_timestamp(struct cs_etm_packet_qu= eue *packet_queue) } =20 static ocsd_datapath_resp_t -cs_etm_decoder__buffer_packet(struct cs_etm_packet_queue *packet_queue, +cs_etm_decoder__buffer_packet(struct cs_etm_queue *etmq, + struct cs_etm_packet_queue *packet_queue, const u8 trace_chan_id, enum cs_etm_sample_type sample_type) { @@ -398,7 +399,7 @@ cs_etm_decoder__buffer_packet(struct cs_etm_packet_queu= e *packet_queue, if (packet_queue->packet_count >=3D CS_ETM_PACKET_MAX_BUFFER - 1) return OCSD_RESP_FATAL_SYS_ERR; =20 - if (cs_etm__get_cpu(trace_chan_id, &cpu) < 0) + if (cs_etm__get_cpu(etmq, trace_chan_id, &cpu) < 0) return OCSD_RESP_FATAL_SYS_ERR; =20 et =3D packet_queue->tail; @@ -436,7 +437,7 @@ cs_etm_decoder__buffer_range(struct cs_etm_queue *etmq, int ret =3D 0; struct cs_etm_packet *packet; =20 - ret =3D cs_etm_decoder__buffer_packet(packet_queue, trace_chan_id, + ret =3D cs_etm_decoder__buffer_packet(etmq, packet_queue, trace_chan_id, CS_ETM_RANGE); if (ret !=3D OCSD_RESP_CONT && ret !=3D OCSD_RESP_WAIT) return ret; @@ -496,7 +497,8 @@ cs_etm_decoder__buffer_range(struct cs_etm_queue *etmq, } =20 static ocsd_datapath_resp_t -cs_etm_decoder__buffer_discontinuity(struct cs_etm_packet_queue *queue, +cs_etm_decoder__buffer_discontinuity(struct cs_etm_queue *etmq, + struct cs_etm_packet_queue *queue, const uint8_t trace_chan_id) { /* @@ -504,18 +506,19 @@ cs_etm_decoder__buffer_discontinuity(struct cs_etm_pa= cket_queue *queue, * reset time statistics. */ cs_etm_decoder__reset_timestamp(queue); - return cs_etm_decoder__buffer_packet(queue, trace_chan_id, + return cs_etm_decoder__buffer_packet(etmq, queue, trace_chan_id, CS_ETM_DISCONTINUITY); } =20 static ocsd_datapath_resp_t -cs_etm_decoder__buffer_exception(struct cs_etm_packet_queue *queue, +cs_etm_decoder__buffer_exception(struct cs_etm_queue *etmq, + struct cs_etm_packet_queue *queue, const ocsd_generic_trace_elem *elem, const uint8_t trace_chan_id) { int ret =3D 0; struct cs_etm_packet *packet; =20 - ret =3D cs_etm_decoder__buffer_packet(queue, trace_chan_id, + ret =3D cs_etm_decoder__buffer_packet(etmq, queue, trace_chan_id, CS_ETM_EXCEPTION); if (ret !=3D OCSD_RESP_CONT && ret !=3D OCSD_RESP_WAIT) return ret; @@ -527,10 +530,11 @@ cs_etm_decoder__buffer_exception(struct cs_etm_packet= _queue *queue, } =20 static ocsd_datapath_resp_t -cs_etm_decoder__buffer_exception_ret(struct cs_etm_packet_queue *queue, +cs_etm_decoder__buffer_exception_ret(struct cs_etm_queue *etmq, + struct cs_etm_packet_queue *queue, const uint8_t trace_chan_id) { - return cs_etm_decoder__buffer_packet(queue, trace_chan_id, + return cs_etm_decoder__buffer_packet(etmq, queue, trace_chan_id, CS_ETM_EXCEPTION_RET); } =20 @@ -599,7 +603,7 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_e= lem_printer( case OCSD_GEN_TRC_ELEM_EO_TRACE: case OCSD_GEN_TRC_ELEM_NO_SYNC: case OCSD_GEN_TRC_ELEM_TRACE_ON: - resp =3D cs_etm_decoder__buffer_discontinuity(packet_queue, + resp =3D cs_etm_decoder__buffer_discontinuity(etmq, packet_queue, trace_chan_id); break; case OCSD_GEN_TRC_ELEM_INSTR_RANGE: @@ -607,11 +611,11 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace= _elem_printer( trace_chan_id); break; case OCSD_GEN_TRC_ELEM_EXCEPTION: - resp =3D cs_etm_decoder__buffer_exception(packet_queue, elem, + resp =3D cs_etm_decoder__buffer_exception(etmq, packet_queue, elem, trace_chan_id); break; case OCSD_GEN_TRC_ELEM_EXCEPTION_RET: - resp =3D cs_etm_decoder__buffer_exception_ret(packet_queue, + resp =3D cs_etm_decoder__buffer_exception_ret(etmq, packet_queue, trace_chan_id); break; case OCSD_GEN_TRC_ELEM_TIMESTAMP: diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 1a95c4bb898f..0cd7d3843411 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -116,16 +116,18 @@ struct cs_etm_queue { /* Conversion between traceID and index in traceid_queues array */ struct intlist *traceid_queues_list; struct cs_etm_traceid_queue **traceid_queues; + /* Conversion between traceID and metadata pointers */ + struct intlist *traceid_list; }; =20 -/* RB tree for quick conversion between traceID and metadata pointers */ -static struct intlist *traceid_list; - static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm); static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm, pid_t tid); static int cs_etm__get_data_block(struct cs_etm_queue *etmq); static int cs_etm__decode_data_block(struct cs_etm_queue *etmq); +static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metad= ata); +static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu); +static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metada= ta); =20 /* PTMs ETMIDR [11:8] set to b0011 */ #define ETMIDR_PTM_VERSION 0x00000300 @@ -151,12 +153,12 @@ static u32 cs_etm__get_v7_protocol_version(u32 etmidr) return CS_ETM_PROTO_ETMV3; } =20 -static int cs_etm__get_magic(u8 trace_chan_id, u64 *magic) +static int cs_etm__get_magic(struct cs_etm_queue *etmq, u8 trace_chan_id, = u64 *magic) { struct int_node *inode; u64 *metadata; =20 - inode =3D intlist__find(traceid_list, trace_chan_id); + inode =3D intlist__find(etmq->traceid_list, trace_chan_id); if (!inode) return -EINVAL; =20 @@ -165,12 +167,12 @@ static int cs_etm__get_magic(u8 trace_chan_id, u64 *m= agic) return 0; } =20 -int cs_etm__get_cpu(u8 trace_chan_id, int *cpu) +int cs_etm__get_cpu(struct cs_etm_queue *etmq, u8 trace_chan_id, int *cpu) { struct int_node *inode; u64 *metadata; =20 - inode =3D intlist__find(traceid_list, trace_chan_id); + inode =3D intlist__find(etmq->traceid_list, trace_chan_id); if (!inode) return -EINVAL; =20 @@ -222,30 +224,108 @@ enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct cs_et= m_queue *etmq) return etmq->etm->pid_fmt; } =20 -static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +static int cs_etm__insert_trace_id_node(struct cs_etm_queue *etmq, + u8 trace_chan_id, u64 *cpu_metadata) { - struct int_node *inode; - /* Get an RB node for this CPU */ - inode =3D intlist__findnew(traceid_list, trace_chan_id); + struct int_node *inode =3D intlist__findnew(etmq->traceid_list, trace_cha= n_id); =20 /* Something went wrong, no need to continue */ if (!inode) return -ENOMEM; =20 + /* Disallow re-mapping a different traceID to metadata pair. */ + if (inode->priv) { + u64 *curr_cpu_data =3D inode->priv; + u8 curr_chan_id; + int err; + + if (curr_cpu_data[CS_ETM_CPU] !=3D cpu_metadata[CS_ETM_CPU]) { + pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + return -EINVAL; + } + + /* check that the mapped ID matches */ + err =3D cs_etm__metadata_get_trace_id(&curr_chan_id, curr_cpu_data); + if (err) + return err; + + if (curr_chan_id !=3D trace_chan_id) { + pr_err("CS_ETM: mismatch between CPU trace ID and HW_ID packet ID\n"); + return -EINVAL; + } + + /* Skip re-adding the same mappings if everything matched */ + return 0; + } + + /* Not one we've seen before, associate the traceID with the metadata poi= nter */ + inode->priv =3D cpu_metadata; + + return 0; +} + +static struct cs_etm_queue *cs_etm__get_queue(struct cs_etm_auxtrace *etm,= int cpu) +{ + if (etm->per_thread_decoding) + return etm->queues.queue_array[0].priv; + else + return etm->queues.queue_array[cpu].priv; +} + +static int cs_etm__map_trace_id_v0(struct cs_etm_auxtrace *etm, u8 trace_c= han_id, + u64 *cpu_metadata) +{ + struct cs_etm_queue *etmq; + /* - * The node for that CPU should not be taken. - * Back out if that's the case. + * If the queue is unformatted then only save one mapping in the + * queue associated with that CPU so only one decoder is made. */ - if (inode->priv) - return -EINVAL; + etmq =3D cs_etm__get_queue(etm, cpu_metadata[CS_ETM_CPU]); + if (etmq->format =3D=3D UNFORMATTED) + return cs_etm__insert_trace_id_node(etmq, trace_chan_id, + cpu_metadata); =20 - /* All good, associate the traceID with the metadata pointer */ - inode->priv =3D cpu_metadata; + /* + * Otherwise, version 0 trace IDs are global so save them into every + * queue. + */ + for (unsigned int i =3D 0; i < etm->queues.nr_queues; ++i) { + int ret; + + etmq =3D etm->queues.queue_array[i].priv; + ret =3D cs_etm__insert_trace_id_node(etmq, trace_chan_id, + cpu_metadata); + if (ret) + return ret; + } =20 return 0; } =20 +static int cs_etm__process_trace_id_v0(struct cs_etm_auxtrace *etm, int cp= u, + u64 hw_id) +{ + int err; + u64 *cpu_data; + u8 trace_chan_id =3D FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); + + cpu_data =3D get_cpu_data(etm, cpu); + if (cpu_data =3D=3D NULL) + return -EINVAL; + + err =3D cs_etm__map_trace_id_v0(etm, trace_chan_id, cpu_data); + if (err) + return err; + + /* + * if we are picking up the association from the packet, need to plug + * the correct trace ID into the metadata for setting up decoders later. + */ + return cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); +} + static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metad= ata) { u64 cs_etm_magic =3D cpu_metadata[CS_ETM_MAGIC]; @@ -329,17 +409,13 @@ static int cs_etm__process_aux_output_hw_id(struct pe= rf_session *session, { struct cs_etm_auxtrace *etm; struct perf_sample sample; - struct int_node *inode; struct evsel *evsel; - u64 *cpu_data; u64 hw_id; int cpu, version, err; - u8 trace_chan_id, curr_chan_id; =20 /* extract and parse the HW ID */ hw_id =3D event->aux_output_hw_id.hw_id; version =3D FIELD_GET(CS_AUX_HW_ID_VERSION_MASK, hw_id); - trace_chan_id =3D FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); =20 /* check that we can handle this version */ if (version > CS_AUX_HW_ID_CURR_VERSION) { @@ -367,43 +443,7 @@ static int cs_etm__process_aux_output_hw_id(struct per= f_session *session, return -EINVAL; } =20 - /* See if the ID is mapped to a CPU, and it matches the current CPU */ - inode =3D intlist__find(traceid_list, trace_chan_id); - if (inode) { - cpu_data =3D inode->priv; - if ((int)cpu_data[CS_ETM_CPU] !=3D cpu) { - pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); - return -EINVAL; - } - - /* check that the mapped ID matches */ - err =3D cs_etm__metadata_get_trace_id(&curr_chan_id, cpu_data); - if (err) - return err; - if (curr_chan_id !=3D trace_chan_id) { - pr_err("CS_ETM: mismatch between CPU trace ID and HW_ID packet ID\n"); - return -EINVAL; - } - - /* mapped and matched - return OK */ - return 0; - } - - cpu_data =3D get_cpu_data(etm, cpu); - if (cpu_data =3D=3D NULL) - return err; - - /* not one we've seen before - lets map it */ - err =3D cs_etm__map_trace_id(trace_chan_id, cpu_data); - if (err) - return err; - - /* - * if we are picking up the association from the packet, need to plug - * the correct trace ID into the metadata for setting up decoders later. - */ - err =3D cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); - return err; + return cs_etm__process_trace_id_v0(etm, cpu, hw_id); } =20 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, @@ -856,6 +896,7 @@ static void cs_etm__free_traceid_queues(struct cs_etm_q= ueue *etmq) =20 static void cs_etm__free_queue(void *priv) { + struct int_node *inode, *tmp; struct cs_etm_queue *etmq =3D priv; =20 if (!etmq) @@ -863,6 +904,14 @@ static void cs_etm__free_queue(void *priv) =20 cs_etm_decoder__free(etmq->decoder); cs_etm__free_traceid_queues(etmq); + + /* First remove all traceID/metadata nodes for the RB tree */ + intlist__for_each_entry_safe(inode, tmp, etmq->traceid_list) + intlist__remove(etmq->traceid_list, inode); + + /* Then the RB tree itself */ + intlist__delete(etmq->traceid_list); + free(etmq); } =20 @@ -885,19 +934,12 @@ static void cs_etm__free_events(struct perf_session *= session) static void cs_etm__free(struct perf_session *session) { int i; - struct int_node *inode, *tmp; struct cs_etm_auxtrace *aux =3D container_of(session->auxtrace, struct cs_etm_auxtrace, auxtrace); cs_etm__free_events(session); session->auxtrace =3D NULL; =20 - /* First remove all traceID/metadata nodes for the RB tree */ - intlist__for_each_entry_safe(inode, tmp, traceid_list) - intlist__remove(traceid_list, inode); - /* Then the RB tree itself */ - intlist__delete(traceid_list); - for (i =3D 0; i < aux->num_cpu; i++) zfree(&aux->metadata[i]); =20 @@ -1055,9 +1097,24 @@ static struct cs_etm_queue *cs_etm__alloc_queue(void) =20 etmq->traceid_queues_list =3D intlist__new(NULL); if (!etmq->traceid_queues_list) - free(etmq); + goto out_free; + + /* + * Create an RB tree for traceID-metadata tuple. Since the conversion + * has to be made for each packet that gets decoded, optimizing access + * in anything other than a sequential array is worth doing. + */ + etmq->traceid_list =3D intlist__new(NULL); + if (!etmq->traceid_list) + goto out_free; =20 return etmq; + +out_free: + intlist__delete(etmq->traceid_queues_list); + free(etmq); + + return NULL; } =20 static int cs_etm__setup_queue(struct cs_etm_auxtrace *etm, @@ -2207,7 +2264,7 @@ static int cs_etm__set_sample_flags(struct cs_etm_que= ue *etmq, PERF_IP_FLAG_TRACE_END; break; case CS_ETM_EXCEPTION: - ret =3D cs_etm__get_magic(packet->trace_chan_id, &magic); + ret =3D cs_etm__get_magic(etmq, packet->trace_chan_id, &magic); if (ret) return ret; =20 @@ -3124,7 +3181,8 @@ static bool cs_etm__has_virtual_ts(u64 **metadata, in= t num_cpu) } =20 /* map trace ids to correct metadata block, from information in metadata */ -static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) +static int cs_etm__map_trace_ids_metadata(struct cs_etm_auxtrace *etm, int= num_cpu, + u64 **metadata) { u64 cs_etm_magic; u8 trace_chan_id; @@ -3146,7 +3204,7 @@ static int cs_etm__map_trace_ids_metadata(int num_cpu= , u64 **metadata) /* unknown magic number */ return -EINVAL; } - err =3D cs_etm__map_trace_id(trace_chan_id, metadata[i]); + err =3D cs_etm__map_trace_id_v0(etm, trace_chan_id, metadata[i]); if (err) return err; } @@ -3277,23 +3335,12 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, u64 *ptr =3D NULL; u64 **metadata =3D NULL; =20 - /* - * Create an RB tree for traceID-metadata tuple. Since the conversion - * has to be made for each packet that gets decoded, optimizing access - * in anything other than a sequential array is worth doing. - */ - traceid_list =3D intlist__new(NULL); - if (!traceid_list) - return -ENOMEM; - /* First the global part */ ptr =3D (u64 *) auxtrace_info->priv; num_cpu =3D ptr[CS_PMU_TYPE_CPUS] & 0xffffffff; metadata =3D zalloc(sizeof(*metadata) * num_cpu); - if (!metadata) { - err =3D -ENOMEM; - goto err_free_traceid_list; - } + if (!metadata) + return -ENOMEM; =20 /* Start parsing after the common part of the header */ i =3D CS_HEADER_VERSION_MAX; @@ -3472,7 +3519,7 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, err =3D cs_etm__clear_unused_trace_ids_metadata(num_cpu, metadata); /* otherwise, this is a file with metadata values only, map from metadata= */ else - err =3D cs_etm__map_trace_ids_metadata(num_cpu, metadata); + err =3D cs_etm__map_trace_ids_metadata(etm, num_cpu, metadata); =20 if (err) goto err_free_queues; @@ -3494,7 +3541,5 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, for (int j =3D 0; j < num_cpu; j++) zfree(&metadata[j]); zfree(&metadata); -err_free_traceid_list: - intlist__delete(traceid_list); return err; } diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 4696267a32f0..f4f69f7cc0f3 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -252,7 +252,7 @@ enum cs_etm_pid_fmt { =20 #ifdef HAVE_CSTRACE_SUPPORT #include -int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); +int cs_etm__get_cpu(struct cs_etm_queue *etmq, u8 trace_chan_id, int *cpu); enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct cs_etm_queue *etmq); int cs_etm__etmq_set_tid_el(struct cs_etm_queue *etmq, pid_t tid, u8 trace_chan_id, ocsd_ex_level el); --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2E4A1607B3; Tue, 25 Jun 2024 13:32:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322370; cv=none; b=olwL5PwuUk4kWaJgdE+ShvEz8b6upNNODTFeXohhH7LaNzNu8Uum7oPGjCGpwBmCmtx7tXr24oBVoJkrnSb3tWIG7239/g7chv4EkaLFKGdOSpU1MlXnjS1NFAExmUhWb6COAR+L/2zlupfjzD/uDXm4Lf49k9IXLwyHwJy+gkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322370; c=relaxed/simple; bh=2isQWgfao2P975rr7ZoeGF0mmFaM9slQWu7fjZVRN0E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZYxnL2x5nV8jxUZ/V8ksvWHTUYaW0gwlGyK2oMe7D2NZd8Wu3KaRIJr4CKXXP33V+0iGcwk2M0YMLYvJGzZa3PtrqkRg0V8qOiosX4pIfE7x8VPXy2/A+DbrHyY7pFwaiUs0ARILYqL1QWM1VdCy6oOEzqHfJ29ElQpwHE9wLkQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D4EEDA7; Tue, 25 Jun 2024 06:33:13 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B125F3F73B; Tue, 25 Jun 2024 06:32:44 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 04/17] perf: cs-etm: Create decoders based on the trace ID mappings Date: Tue, 25 Jun 2024 14:30:47 +0100 Message-Id: <20240625133105.671245-5-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that each queue has a unique set of trace ID mappings, use this list to create the decoders. In unformatted mode just add a single mapping so only one decoder is made. Previously each queue would have a decoder created for each traced CPU on the system but this won't work anymore because CPUs can have overlapping trace IDs. This also means that the CORESIGHT_TRACE_ID_UNUSED_FLAG isn't needed any more. If mappings aren't added then decoders aren't created, rather than needing a flag to suppress creation. Signed-off-by: James Clark --- tools/perf/arch/arm/util/cs-etm.c | 8 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 4 - tools/perf/util/cs-etm.c | 155 ++++++------------ tools/perf/util/cs-etm.h | 10 -- 4 files changed, 55 insertions(+), 122 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index da6231367993..b0118546cd4d 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -654,8 +654,7 @@ static void cs_etm_save_etmv4_header(__u64 data[], stru= ct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] =3D cs_etmv4_get_config(itr); /* traceID set to legacy version, in case new perf running on older syste= m */ - data[CS_ETMV4_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu) | - CORESIGHT_TRACE_ID_UNUSED_FLAG; + data[CS_ETMV4_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu); =20 /* Get read-only information from sysFS */ cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0], @@ -687,7 +686,7 @@ static void cs_etm_save_ete_header(__u64 data[], struct= auxtrace_record *itr, st /* Get trace configuration register */ data[CS_ETE_TRCCONFIGR] =3D cs_etmv4_get_config(itr); /* traceID set to legacy version, in case new perf running on older syste= m */ - data[CS_ETE_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu) | CORESIGHT_= TRACE_ID_UNUSED_FLAG; + data[CS_ETE_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu); =20 /* Get read-only information from sysFS */ cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR0], &data[CS_= ETE_TRCIDR0]); @@ -743,8 +742,7 @@ static void cs_etm_get_metadata(struct perf_cpu cpu, u3= 2 *offset, /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] =3D cs_etm_get_config(itr); /* traceID set to legacy value in case new perf running on old system */ - info->priv[*offset + CS_ETM_ETMTRACEIDR] =3D cs_etm_get_legacy_trace_id(= cpu) | - CORESIGHT_TRACE_ID_UNUSED_FLAG; + info->priv[*offset + CS_ETM_ETMTRACEIDR] =3D cs_etm_get_legacy_trace_id(= cpu); /* Get read-only information from sysFS */ cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv3_ro[CS_ETM_ETMCCER], &info->priv[*offset + CS_ETM_ETMCCER]); diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.c index 0c9c48cedbf1..d49c3e9c7c21 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -684,10 +684,6 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decod= er_params *d_params, return -1; } =20 - /* if the CPU has no trace ID associated, no decoder needed */ - if (csid =3D=3D CORESIGHT_TRACE_ID_UNUSED_VAL) - return 0; - if (d_params->operation =3D=3D CS_ETM_OPERATION_DECODE) { if (ocsd_dt_create_decoder(decoder->dcd_tree, decoder->decoder_name, diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 0cd7d3843411..954a6f7bedf3 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -348,7 +348,6 @@ static int cs_etm__metadata_get_trace_id(u8 *trace_chan= _id, u64 *cpu_metadata) =20 /* * update metadata trace ID from the value found in the AUX_HW_INFO packet. - * This will also clear the CORESIGHT_TRACE_ID_UNUSED_FLAG flag if present. */ static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metada= ta) { @@ -700,80 +699,58 @@ static void cs_etm__packet_dump(const char *pkt_strin= g) } =20 static void cs_etm__set_trace_param_etmv3(struct cs_etm_trace_params *t_pa= rams, - struct cs_etm_auxtrace *etm, int t_idx, - int m_idx, u32 etmidr) + u64 *metadata, u32 etmidr) { - u64 **metadata =3D etm->metadata; - - t_params[t_idx].protocol =3D cs_etm__get_v7_protocol_version(etmidr); - t_params[t_idx].etmv3.reg_ctrl =3D metadata[m_idx][CS_ETM_ETMCR]; - t_params[t_idx].etmv3.reg_trc_id =3D metadata[m_idx][CS_ETM_ETMTRACEIDR]; + t_params->protocol =3D cs_etm__get_v7_protocol_version(etmidr); + t_params->etmv3.reg_ctrl =3D metadata[CS_ETM_ETMCR]; + t_params->etmv3.reg_trc_id =3D metadata[CS_ETM_ETMTRACEIDR]; } =20 static void cs_etm__set_trace_param_etmv4(struct cs_etm_trace_params *t_pa= rams, - struct cs_etm_auxtrace *etm, int t_idx, - int m_idx) + u64 *metadata) { - u64 **metadata =3D etm->metadata; - - t_params[t_idx].protocol =3D CS_ETM_PROTO_ETMV4i; - t_params[t_idx].etmv4.reg_idr0 =3D metadata[m_idx][CS_ETMV4_TRCIDR0]; - t_params[t_idx].etmv4.reg_idr1 =3D metadata[m_idx][CS_ETMV4_TRCIDR1]; - t_params[t_idx].etmv4.reg_idr2 =3D metadata[m_idx][CS_ETMV4_TRCIDR2]; - t_params[t_idx].etmv4.reg_idr8 =3D metadata[m_idx][CS_ETMV4_TRCIDR8]; - t_params[t_idx].etmv4.reg_configr =3D metadata[m_idx][CS_ETMV4_TRCCONFIGR= ]; - t_params[t_idx].etmv4.reg_traceidr =3D metadata[m_idx][CS_ETMV4_TRCTRACEI= DR]; + t_params->protocol =3D CS_ETM_PROTO_ETMV4i; + t_params->etmv4.reg_idr0 =3D metadata[CS_ETMV4_TRCIDR0]; + t_params->etmv4.reg_idr1 =3D metadata[CS_ETMV4_TRCIDR1]; + t_params->etmv4.reg_idr2 =3D metadata[CS_ETMV4_TRCIDR2]; + t_params->etmv4.reg_idr8 =3D metadata[CS_ETMV4_TRCIDR8]; + t_params->etmv4.reg_configr =3D metadata[CS_ETMV4_TRCCONFIGR]; + t_params->etmv4.reg_traceidr =3D metadata[CS_ETMV4_TRCTRACEIDR]; } =20 static void cs_etm__set_trace_param_ete(struct cs_etm_trace_params *t_para= ms, - struct cs_etm_auxtrace *etm, int t_idx, - int m_idx) + u64 *metadata) { - u64 **metadata =3D etm->metadata; - - t_params[t_idx].protocol =3D CS_ETM_PROTO_ETE; - t_params[t_idx].ete.reg_idr0 =3D metadata[m_idx][CS_ETE_TRCIDR0]; - t_params[t_idx].ete.reg_idr1 =3D metadata[m_idx][CS_ETE_TRCIDR1]; - t_params[t_idx].ete.reg_idr2 =3D metadata[m_idx][CS_ETE_TRCIDR2]; - t_params[t_idx].ete.reg_idr8 =3D metadata[m_idx][CS_ETE_TRCIDR8]; - t_params[t_idx].ete.reg_configr =3D metadata[m_idx][CS_ETE_TRCCONFIGR]; - t_params[t_idx].ete.reg_traceidr =3D metadata[m_idx][CS_ETE_TRCTRACEIDR]; - t_params[t_idx].ete.reg_devarch =3D metadata[m_idx][CS_ETE_TRCDEVARCH]; + t_params->protocol =3D CS_ETM_PROTO_ETE; + t_params->ete.reg_idr0 =3D metadata[CS_ETE_TRCIDR0]; + t_params->ete.reg_idr1 =3D metadata[CS_ETE_TRCIDR1]; + t_params->ete.reg_idr2 =3D metadata[CS_ETE_TRCIDR2]; + t_params->ete.reg_idr8 =3D metadata[CS_ETE_TRCIDR8]; + t_params->ete.reg_configr =3D metadata[CS_ETE_TRCCONFIGR]; + t_params->ete.reg_traceidr =3D metadata[CS_ETE_TRCTRACEIDR]; + t_params->ete.reg_devarch =3D metadata[CS_ETE_TRCDEVARCH]; } =20 static int cs_etm__init_trace_params(struct cs_etm_trace_params *t_params, - struct cs_etm_auxtrace *etm, - enum cs_etm_format format, - int sample_cpu, - int decoders) -{ - int t_idx, m_idx; - u32 etmidr; - u64 architecture; - - for (t_idx =3D 0; t_idx < decoders; t_idx++) { - if (format =3D=3D FORMATTED) - m_idx =3D t_idx; - else { - m_idx =3D get_cpu_data_idx(etm, sample_cpu); - if (m_idx =3D=3D -1) { - pr_warning("CS_ETM: unknown CPU, falling back to first metadata\n"); - m_idx =3D 0; - } - } + struct cs_etm_queue *etmq) +{ + struct int_node *inode; =20 - architecture =3D etm->metadata[m_idx][CS_ETM_MAGIC]; + intlist__for_each_entry(inode, etmq->traceid_list) { + u64 *metadata =3D inode->priv; + u64 architecture =3D metadata[CS_ETM_MAGIC]; + u32 etmidr; =20 switch (architecture) { case __perf_cs_etmv3_magic: - etmidr =3D etm->metadata[m_idx][CS_ETM_ETMIDR]; - cs_etm__set_trace_param_etmv3(t_params, etm, t_idx, m_idx, etmidr); + etmidr =3D metadata[CS_ETM_ETMIDR]; + cs_etm__set_trace_param_etmv3(t_params++, metadata, etmidr); break; case __perf_cs_etmv4_magic: - cs_etm__set_trace_param_etmv4(t_params, etm, t_idx, m_idx); + cs_etm__set_trace_param_etmv4(t_params++, metadata); break; case __perf_cs_ete_magic: - cs_etm__set_trace_param_ete(t_params, etm, t_idx, m_idx); + cs_etm__set_trace_param_ete(t_params++, metadata); break; default: return -EINVAL; @@ -3211,35 +3188,6 @@ static int cs_etm__map_trace_ids_metadata(struct cs_= etm_auxtrace *etm, int num_c return 0; } =20 -/* - * If we found AUX_HW_ID packets, then set any metadata marked as unused t= o the - * unused value to reduce the number of unneeded decoders created. - */ -static int cs_etm__clear_unused_trace_ids_metadata(int num_cpu, u64 **meta= data) -{ - u64 cs_etm_magic; - int i; - - for (i =3D 0; i < num_cpu; i++) { - cs_etm_magic =3D metadata[i][CS_ETM_MAGIC]; - switch (cs_etm_magic) { - case __perf_cs_etmv3_magic: - if (metadata[i][CS_ETM_ETMTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) - metadata[i][CS_ETM_ETMTRACEIDR] =3D CORESIGHT_TRACE_ID_UNUSED_VAL; - break; - case __perf_cs_etmv4_magic: - case __perf_cs_ete_magic: - if (metadata[i][CS_ETMV4_TRCTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) - metadata[i][CS_ETMV4_TRCTRACEIDR] =3D CORESIGHT_TRACE_ID_UNUSED_VAL; - break; - default: - /* unknown magic number */ - return -EINVAL; - } - } - return 0; -} - /* * Use the data gathered by the peeks for HW_ID (trace ID mappings) and AUX * (formatted or not) packets to create the decoders. @@ -3247,21 +3195,26 @@ static int cs_etm__clear_unused_trace_ids_metadata(= int num_cpu, u64 **metadata) static int cs_etm__create_queue_decoders(struct cs_etm_queue *etmq) { struct cs_etm_decoder_params d_params; + struct cs_etm_trace_params *t_params; + int decoders =3D intlist__nr_entries(etmq->traceid_list); + + if (decoders =3D=3D 0) + return 0; =20 /* * Each queue can only contain data from one CPU when unformatted, so onl= y one decoder is * needed. */ - int decoders =3D etmq->format =3D=3D FORMATTED ? etmq->etm->num_cpu : 1; + if (etmq->format =3D=3D UNFORMATTED) + assert(decoders =3D=3D 1); =20 /* Use metadata to fill in trace parameters for trace decoder */ - struct cs_etm_trace_params *t_params =3D zalloc(sizeof(*t_params) * deco= ders); + t_params =3D zalloc(sizeof(*t_params) * decoders); =20 if (!t_params) goto out_free; =20 - if (cs_etm__init_trace_params(t_params, etmq->etm, etmq->format, - etmq->queue_nr, decoders)) + if (cs_etm__init_trace_params(t_params, etmq)) goto out_free; =20 /* Set decoder parameters to decode trace packets */ @@ -3487,9 +3440,9 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, /* * Map Trace ID values to CPU metadata. * - * Trace metadata will always contain Trace ID values from the legacy alg= orithm. If the - * files has been recorded by a "new" perf updated to handle AUX_HW_ID th= en the metadata - * ID value will also have the CORESIGHT_TRACE_ID_UNUSED_FLAG set. + * Trace metadata will always contain Trace ID values from the legacy alg= orithm + * in case it's read by a version of Perf that doesn't know about HW_ID p= ackets + * or the kernel doesn't emit them. * * The updated kernel drivers that use AUX_HW_ID to sent Trace IDs will a= ttempt to use * the same IDs as the old algorithm as far as is possible, unless there = are clashes @@ -3498,12 +3451,11 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, * * For a perf able to interpret AUX_HW_ID packets we first check for the = presence of * those packets. If they are there then the values will be mapped and pl= ugged into - * the metadata. We then set any remaining metadata values with the used = flag to a - * value CORESIGHT_TRACE_ID_UNUSED_VAL - which indicates no decoder is re= quired. + * the metadata and decoders are only created for each mapping received. * * If no AUX_HW_ID packets are present - which means a file recorded on a= n old kernel - * then we map Trace ID values to CPU directly from the metadata - cleari= ng any unused - * flags if present. + * then we map Trace ID values to CPU directly from the metadata and crea= te decoders + * for all mappings. */ =20 /* Scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU metada= ta */ @@ -3514,15 +3466,12 @@ int cs_etm__process_auxtrace_info_full(union perf_e= vent *event, if (err) goto err_free_queues; =20 - /* if HW ID found then clear any unused metadata ID values */ - if (aux_hw_id_found) - err =3D cs_etm__clear_unused_trace_ids_metadata(num_cpu, metadata); - /* otherwise, this is a file with metadata values only, map from metadata= */ - else + /* if no HW ID found this is a file with metadata values only, map from m= etadata */ + if (!aux_hw_id_found) { err =3D cs_etm__map_trace_ids_metadata(etm, num_cpu, metadata); - - if (err) - goto err_free_queues; + if (err) + goto err_free_queues; + } =20 err =3D cs_etm__create_decoders(etm); if (err) diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index f4f69f7cc0f3..a8caeea720aa 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -230,16 +230,6 @@ struct cs_etm_packet_queue { /* CoreSight trace ID is currently the bottom 7 bits of the value */ #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) =20 -/* - * perf record will set the legacy meta data values as unused initially. - * This allows perf report to manage the decoders created when dynamic - * allocation in operation. - */ -#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) - -/* Value to set for unused trace ID values */ -#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F - int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session); void cs_etm_get_default_config(const struct perf_pmu *pmu, struct perf_eve= nt_attr *attr); --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3B87D1607B3; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 79007DA7; Tue, 25 Jun 2024 06:33:21 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 229623F73B; Tue, 25 Jun 2024 06:32:53 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 05/17] perf: cs-etm: Only save valid trace IDs into files Date: Tue, 25 Jun 2024 14:30:48 +0100 Message-Id: <20240625133105.671245-6-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This isn't a bug because Perf always masks with CORESIGHT_TRACE_ID_VAL_MASK before using these values, but to avoid it looking like it could be, make an effort to not save bad values. Signed-off-by: James Clark --- tools/perf/arch/arm/util/cs-etm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index b0118546cd4d..14b8afabce3a 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -643,7 +643,8 @@ static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, = struct perf_cpu cpu) =20 static __u64 cs_etm_get_legacy_trace_id(struct perf_cpu cpu) { - return CORESIGHT_LEGACY_CPU_TRACE_ID(cpu.cpu); + /* Wrap at 48 so that invalid trace IDs aren't saved into files. */ + return CORESIGHT_LEGACY_CPU_TRACE_ID(cpu.cpu % 48); } =20 static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record = *itr, struct perf_cpu cpu) --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B01C2146A6C; Tue, 25 Jun 2024 13:33:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322388; cv=none; b=C5IKGumAEnIttNiqxJ/oqEv3vbZsT4UdzRPtgNyUgIWtcC2suLjjU0/jouH9yHYPIndJ86SYexjVbFh7tRcKUCJZ1zbly+Wt2LgTVNGT+C1zIgKqmvJ0mLK1akH96f4vzRLrcjlohjP4FgQQipdKiywxzynIB4EOpKG189gksxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322388; c=relaxed/simple; bh=dEDijOAcvPurEw8O+EaEQkPF5YjwB716dwuVfYRcc5k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CKpNqAhOVtxOOssbes/fTmPitQ2o95i3FMCyP12BGc6PsZInl57muv7DVnC9tzF890uD06j2X2BsyMGgUwNUYo5PVxFajY1omVLdYgTZztaO2pZ6nR/9m42PxErTfsTw/iW6HVvAlDd1V+waWZsARa5X6f2elJ2UPZ21gUpQpmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 329A0DA7; Tue, 25 Jun 2024 06:33:31 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 177913F73B; Tue, 25 Jun 2024 06:33:01 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 06/17] perf: cs-etm: Support version 0.1 of HW_ID packets Date: Tue, 25 Jun 2024 14:30:49 +0100 Message-Id: <20240625133105.671245-7-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" v0.1 HW_ID packets have a new field that describes which sink each CPU writes to. Use the sink ID to link trace ID maps to each other so that mappings are shared wherever the sink is shared. Also update the error message to show that overlapping IDs aren't an error in per-thread mode, just not supported. In the future we can use the CPU ID from the AUX records, or watch for changing sink IDs on HW_ID packets to use the correct decoders. Signed-off-by: James Clark --- tools/include/linux/coresight-pmu.h | 17 +++-- tools/perf/util/cs-etm.c | 100 +++++++++++++++++++++++++--- 2 files changed, 103 insertions(+), 14 deletions(-) diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/core= sight-pmu.h index 51ac441a37c3..89b0ac0014b0 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -49,12 +49,21 @@ * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. * Used to associate a CPU with the CoreSight Trace ID. * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. - * [59:08] - Unused (SBZ) - * [63:60] - Version + * [39:08] - Sink ID - as reported in /sys/bus/event_source/devices/cs_etm= /sinks/ + * Added in minor version 1. + * [55:40] - Unused (SBZ) + * [59:56] - Minor Version - previously existing fields are compatible with + * all minor versions. + * [63:60] - Major Version - previously existing fields mean different thi= ngs + * in new major versions. */ #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) -#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) +#define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8) =20 -#define CS_AUX_HW_ID_CURR_VERSION 0 +#define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56) +#define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_MAJOR_VERSION 0 +#define CS_AUX_HW_ID_MINOR_VERSION 1 =20 #endif diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 954a6f7bedf3..87e983da19be 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -118,6 +118,12 @@ struct cs_etm_queue { struct cs_etm_traceid_queue **traceid_queues; /* Conversion between traceID and metadata pointers */ struct intlist *traceid_list; + /* + * Same as traceid_list, but traceid_list may be a reference to another + * queue's which has a matching sink ID. + */ + struct intlist *own_traceid_list; + u32 sink_id; }; =20 static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm); @@ -142,6 +148,7 @@ static int cs_etm__metadata_set_trace_id(u8 trace_chan_= id, u64 *cpu_metadata); (queue_nr << 16 | trace_chan_id) #define TO_QUEUE_NR(cs_queue_nr) (cs_queue_nr >> 16) #define TO_TRACE_CHAN_ID(cs_queue_nr) (cs_queue_nr & 0x0000ffff) +#define SINK_UNSET ((u32) -1) =20 static u32 cs_etm__get_v7_protocol_version(u32 etmidr) { @@ -241,7 +248,16 @@ static int cs_etm__insert_trace_id_node(struct cs_etm_= queue *etmq, int err; =20 if (curr_cpu_data[CS_ETM_CPU] !=3D cpu_metadata[CS_ETM_CPU]) { - pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + /* + * With > CORESIGHT_TRACE_IDS_MAX ETMs, overlapping IDs + * are expected (but not supported) in per-thread mode, + * rather than signifying an error. + */ + if (etmq->etm->per_thread_decoding) + pr_err("CS_ETM: overlapping Trace IDs aren't currently supported in pe= r-thread mode\n"); + else + pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + return -EINVAL; } =20 @@ -326,6 +342,64 @@ static int cs_etm__process_trace_id_v0(struct cs_etm_a= uxtrace *etm, int cpu, return cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); } =20 +static int cs_etm__process_trace_id_v0_1(struct cs_etm_auxtrace *etm, int = cpu, + u64 hw_id) +{ + struct cs_etm_queue *etmq =3D cs_etm__get_queue(etm, cpu); + int ret; + u64 *cpu_data; + u32 sink_id =3D FIELD_GET(CS_AUX_HW_ID_SINK_ID_MASK, hw_id); + u8 trace_id =3D FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); + + /* + * Check sink id hasn't changed in per-cpu mode. In per-thread mode, + * let it pass for now until an actual overlapping trace ID is hit. In + * most cases IDs won't overlap even if the sink changes. + */ + if (!etmq->etm->per_thread_decoding && etmq->sink_id !=3D SINK_UNSET && + etmq->sink_id !=3D sink_id) { + pr_err("CS_ETM: mismatch between sink IDs\n"); + return -EINVAL; + } + + etmq->sink_id =3D sink_id; + + /* Find which other queues use this sink and link their ID maps */ + for (unsigned int i =3D 0; i < etm->queues.nr_queues; ++i) { + struct cs_etm_queue *other_etmq =3D etm->queues.queue_array[i].priv; + + /* Different sinks, skip */ + if (other_etmq->sink_id !=3D etmq->sink_id) + continue; + + /* Already linked, skip */ + if (other_etmq->traceid_list =3D=3D etmq->traceid_list) + continue; + + /* At the point of first linking, this one should be empty */ + if (!intlist__empty(etmq->traceid_list)) { + pr_err("CS_ETM: Can't link populated trace ID lists\n"); + return -EINVAL; + } + + etmq->own_traceid_list =3D NULL; + intlist__delete(etmq->traceid_list); + etmq->traceid_list =3D other_etmq->traceid_list; + break; + } + + cpu_data =3D get_cpu_data(etm, cpu); + ret =3D cs_etm__insert_trace_id_node(etmq, trace_id, cpu_data); + if (ret) + return ret; + + ret =3D cs_etm__metadata_set_trace_id(trace_id, cpu_data); + if (ret) + return ret; + + return 0; +} + static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metad= ata) { u64 cs_etm_magic =3D cpu_metadata[CS_ETM_MAGIC]; @@ -414,10 +488,10 @@ static int cs_etm__process_aux_output_hw_id(struct pe= rf_session *session, =20 /* extract and parse the HW ID */ hw_id =3D event->aux_output_hw_id.hw_id; - version =3D FIELD_GET(CS_AUX_HW_ID_VERSION_MASK, hw_id); + version =3D FIELD_GET(CS_AUX_HW_ID_MAJOR_VERSION_MASK, hw_id); =20 /* check that we can handle this version */ - if (version > CS_AUX_HW_ID_CURR_VERSION) { + if (version > CS_AUX_HW_ID_MAJOR_VERSION) { pr_err("CS ETM Trace: PERF_RECORD_AUX_OUTPUT_HW_ID version %d not suppor= ted. Please update Perf.\n", version); return -EINVAL; @@ -442,7 +516,10 @@ static int cs_etm__process_aux_output_hw_id(struct per= f_session *session, return -EINVAL; } =20 - return cs_etm__process_trace_id_v0(etm, cpu, hw_id); + if (FIELD_GET(CS_AUX_HW_ID_MINOR_VERSION_MASK, hw_id) =3D=3D 0) + return cs_etm__process_trace_id_v0(etm, cpu, hw_id); + else + return cs_etm__process_trace_id_v0_1(etm, cpu, hw_id); } =20 void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, @@ -882,12 +959,14 @@ static void cs_etm__free_queue(void *priv) cs_etm_decoder__free(etmq->decoder); cs_etm__free_traceid_queues(etmq); =20 - /* First remove all traceID/metadata nodes for the RB tree */ - intlist__for_each_entry_safe(inode, tmp, etmq->traceid_list) - intlist__remove(etmq->traceid_list, inode); + if (etmq->own_traceid_list) { + /* First remove all traceID/metadata nodes for the RB tree */ + intlist__for_each_entry_safe(inode, tmp, etmq->own_traceid_list) + intlist__remove(etmq->own_traceid_list, inode); =20 - /* Then the RB tree itself */ - intlist__delete(etmq->traceid_list); + /* Then the RB tree itself */ + intlist__delete(etmq->own_traceid_list); + } =20 free(etmq); } @@ -1081,7 +1160,7 @@ static struct cs_etm_queue *cs_etm__alloc_queue(void) * has to be made for each packet that gets decoded, optimizing access * in anything other than a sequential array is worth doing. */ - etmq->traceid_list =3D intlist__new(NULL); + etmq->traceid_list =3D etmq->own_traceid_list =3D intlist__new(NULL); if (!etmq->traceid_list) goto out_free; =20 @@ -1113,6 +1192,7 @@ static int cs_etm__setup_queue(struct cs_etm_auxtrace= *etm, etmq->queue_nr =3D queue_nr; queue->cpu =3D queue_nr; /* Placeholder, may be reset to -1 in per-thread= mode */ etmq->offset =3D 0; + etmq->sink_id =3D SINK_UNSET; =20 return 0; } --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B1B231DDC9; Tue, 25 Jun 2024 13:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322397; cv=none; b=rw+7rbbFeIFbQod5pu8KKsA+HO5U4bHFE1rW2QfufEZh+e3KgH7fMzYyrXTr90hp0nYIHR4ZXo6GroLfaM2oVLEzqry8rePzFnxM12xI9HxMs2zN11nPwDvASn4uwtRTxOq0CVhDKdVrPnbH7XMBw7lUH0blNZJzztKwAPxkuvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322397; c=relaxed/simple; bh=eujB/BmdvKJot5kDSOgIqZuBhQic3PS+amFCha2fFDA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N2ugfFmaxKy20ZfX7h1c6AjInLsfik71YyBBSuozh+we0Capdqk2fQ5lJDYFbhxsa6ib6WlsafmqRpDGXM33i9xRIhwup6/w4AXDt8mmlKMjgSdYH2BVgJZbCmHkNgb/edC2AXxrw9DX6mfZTnzCodcFnywIVDx0cYDC9+v5E9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB132DA7; Tue, 25 Jun 2024 06:33:39 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A6E533F73B; Tue, 25 Jun 2024 06:33:11 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 07/17] perf: cs-etm: Print queue number in raw trace dump Date: Tue, 25 Jun 2024 14:30:50 +0100 Message-Id: <20240625133105.671245-8-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that we have overlapping trace IDs it's also useful to know what the queue number is to be able to distinguish the source of the trace so print it inline. Signed-off-by: James Clark --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 4 ++-- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 2 +- tools/perf/util/cs-etm.c | 7 ++++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.c index d49c3e9c7c21..b78ef0262135 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -41,7 +41,7 @@ const u32 INSTR_PER_NS =3D 10; =20 struct cs_etm_decoder { void *data; - void (*packet_printer)(const char *msg); + void (*packet_printer)(const char *msg, void *data); bool suppress_printing; dcd_tree_handle_t dcd_tree; cs_etm_mem_cb_type mem_access; @@ -202,7 +202,7 @@ static void cs_etm_decoder__print_str_cb(const void *p_= context, const struct cs_etm_decoder *decoder =3D p_context; =20 if (p_context && str_len && !decoder->suppress_printing) - decoder->packet_printer(msg); + decoder->packet_printer(msg, decoder->data); } =20 static int diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.h index 272c2efe78ee..12c782fa6db2 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -60,7 +60,7 @@ struct cs_etm_trace_params { =20 struct cs_etm_decoder_params { int operation; - void (*packet_printer)(const char *msg); + void (*packet_printer)(const char *msg, void *data); cs_etm_mem_cb_type mem_acc_cb; bool formatted; bool fsyncs; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 87e983da19be..49fadf46f42b 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -762,15 +762,16 @@ static void cs_etm__packet_swap(struct cs_etm_auxtrac= e *etm, } } =20 -static void cs_etm__packet_dump(const char *pkt_string) +static void cs_etm__packet_dump(const char *pkt_string, void *data) { const char *color =3D PERF_COLOR_BLUE; int len =3D strlen(pkt_string); + struct cs_etm_queue *etmq =3D data; =20 if (len && (pkt_string[len-1] =3D=3D '\n')) - color_fprintf(stdout, color, " %s", pkt_string); + color_fprintf(stdout, color, " Qnr:%d; %s", etmq->queue_nr, pkt_string); else - color_fprintf(stdout, color, " %s\n", pkt_string); + color_fprintf(stdout, color, " Qnr:%d; %s\n", etmq->queue_nr, pkt_string= ); =20 fflush(stdout); } --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 81851158D83; Tue, 25 Jun 2024 13:33:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322406; cv=none; b=hcUufM/zKWElDqUUfsfqWYA4j1N3fRs/tdo83SmpKaz26hAO21sfM6KaQbyIZR/WB2fAvN5byUu8eYpQaA1+/bSsjDu98c9j48Jf+syPloUlJQU4i9hvEnPFfbwj0kG6mfS/zbn9WLcS0aIBJqMyMyMq2w0Edwk+YpevV6uVW74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322406; c=relaxed/simple; bh=sFCq76/ReKigOw24t2/rKzVdHlb+dXBaVLMq8dLOOwQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V41iwUBiVE5afVVOyJwmJYbunJVHvxJRXJQcCFc7OAYIrozktb1ezoFNLgkVkDAbfPnJmymFP7tTPSp9vdPPgAdsBpbfH4Cg8CAn1jWvha1Ug3SyO8ag5GIqd24CugJWSkkR8vGdMThd3bb9Eu5SAfCScsCvMqRVOm808G7gr0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4CA8DA7; Tue, 25 Jun 2024 06:33:48 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 70ECF3F73B; Tue, 25 Jun 2024 06:33:20 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 08/17] perf: cs-etm: Add runtime version check for OpenCSD Date: Tue, 25 Jun 2024 14:30:51 +0100 Message-Id: <20240625133105.671245-9-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OpenCSD is dynamically linked so although there is a build time check, at runtime the user might still have the wrong version. To avoid hard to debug errors, add a runtime version check. Signed-off-by: James Clark --- tools/build/feature/test-libopencsd.c | 4 ++-- tools/perf/Makefile.config | 2 +- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 13 +++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm-decoder/cs-etm-min-version.h | 13 +++++++++++++ tools/perf/util/cs-etm.c | 3 +++ 6 files changed, 33 insertions(+), 3 deletions(-) create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-min-version.h diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/te= st-libopencsd.c index 4cfcef9da3e4..d092a0c662f4 100644 --- a/tools/build/feature/test-libopencsd.c +++ b/tools/build/feature/test-libopencsd.c @@ -1,12 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include "cs-etm-decoder/cs-etm-min-version.h" =20 /* * Check OpenCSD library version is sufficient to provide required features */ -#define OCSD_MIN_VER ((1 << 16) | (2 << 8) | (1)) #if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER) -#error "OpenCSD >=3D 1.2.1 is required" +#error "OpenCSD minimum version (OCSD_MIN_VER) not met." #endif =20 int main(void) diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 7f1e016a9253..2d21be42820e 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -141,7 +141,7 @@ endif ifdef CSLIBS LIBOPENCSD_LDFLAGS :=3D -L$(CSLIBS) endif -FEATURE_CHECK_CFLAGS-libopencsd :=3D $(LIBOPENCSD_CFLAGS) +FEATURE_CHECK_CFLAGS-libopencsd :=3D $(LIBOPENCSD_CFLAGS) -I$(src-perf)/ut= il FEATURE_CHECK_LDFLAGS-libopencsd :=3D $(LIBOPENCSD_LDFLAGS) $(OPENCSDLIBS) =20 # for linking with debug library, run like: diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.c index b78ef0262135..5e1b4503aab1 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -16,6 +16,7 @@ =20 #include "cs-etm.h" #include "cs-etm-decoder.h" +#include "cs-etm-min-version.h" #include "debug.h" #include "intlist.h" =20 @@ -835,3 +836,15 @@ const char *cs_etm_decoder__get_name(struct cs_etm_dec= oder *decoder) { return decoder->decoder_name; } + +int cs_etm_decoder__check_ver(void) +{ + if (ocsd_get_version() < OCSD_MIN_VER) { + pr_err("OpenCSD >=3D %d.%d.%d is required\n", OCSD_MIN_MAJOR, + OCSD_MIN_MINOR, + OCSD_MIN_PATCH); + return -EINVAL; + } + + return 0; +} diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/u= til/cs-etm-decoder/cs-etm-decoder.h index 12c782fa6db2..2ec426ee16dc 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -107,5 +107,6 @@ int cs_etm_decoder__get_packet(struct cs_etm_packet_que= ue *packet_queue, =20 int cs_etm_decoder__reset(struct cs_etm_decoder *decoder); const char *cs_etm_decoder__get_name(struct cs_etm_decoder *decoder); +int cs_etm_decoder__check_ver(void); =20 #endif /* INCLUDE__CS_ETM_DECODER_H__ */ diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-min-version.h b/tools/pe= rf/util/cs-etm-decoder/cs-etm-min-version.h new file mode 100644 index 000000000000..c69597e9d0af --- /dev/null +++ b/tools/perf/util/cs-etm-decoder/cs-etm-min-version.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef INCLUDE__CS_ETM_MIN_VERSION_H__ +#define INCLUDE__CS_ETM_MIN_VERSION_H__ + +#define OCSD_MIN_MAJOR 1 +#define OCSD_MIN_MINOR 2 +#define OCSD_MIN_PATCH 1 + +#define OCSD_MIN_VER ((OCSD_MIN_MAJOR << 16) | \ + (OCSD_MIN_MINOR << 8) | \ + (OCSD_MIN_PATCH)) + +#endif /* INCLUDE__CS_ETM_MIN_VERSION_H__ */ diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 49fadf46f42b..2385d5ed5ea5 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -3369,6 +3369,9 @@ int cs_etm__process_auxtrace_info_full(union perf_eve= nt *event, u64 *ptr =3D NULL; u64 **metadata =3D NULL; =20 + if (cs_etm_decoder__check_ver()) + return -EINVAL; + /* First the global part */ ptr =3D (u64 *) auxtrace_info->priv; num_cpu =3D ptr[CS_PMU_TYPE_CPUS] & 0xffffffff; --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CE82615ADBB; Tue, 25 Jun 2024 13:33:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322414; cv=none; b=EFnbju0ihXDgePawamNMFpIqiEujOJP0Ar1VM2n5XVUO3hn1KnAPyoipjEk8OzlrBy2P+3jV2/5/ExqpTYliIDGtvQUvAvswrc4QJjzvh9gLp0jDH3w7YOwLGWs6Cv5iIbiMh1hr1WuvY3muN6HYeyzP0dt59cFgoYOEQiJrdNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322414; c=relaxed/simple; bh=6nj9MSKICn8rw0/teN5JEls/J6Alp3u6VNBhggwcorQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Yy0owwju9KOURpZ88Drke6R7XbBAnNDBMw8u86xgvJXARIbYd3W+k6DiqiSWYBcIqWHFGlni1N7GUzmWnUvHWLRxlulEimn19HLQJ1MX4KUW0iGE5gBwUaHluIetJYuZTqAv9iPibZUi1n+L+UUw/dhlciQQcN8NxisAqI6A9ek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 440CDDA7; Tue, 25 Jun 2024 06:33:57 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EFCA93F73B; Tue, 25 Jun 2024 06:33:28 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 09/17] coresight: Remove unused ETM Perf stubs Date: Tue, 25 Jun 2024 14:30:52 +0100 Message-Id: <20240625133105.671245-10-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This file is never included anywhere if CONFIG_CORESIGHT is not set so they are unused and aren't currently compile tested with any config so remove them. Reviewed-by: Anshuman Khandual Reviewed-by: Mike Leach Signed-off-by: James Clark --- .../hwtracing/coresight/coresight-etm-perf.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwt= racing/coresight/coresight-etm-perf.h index bebbadee2ceb..744531158d6b 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -62,7 +62,6 @@ struct etm_event_data { struct list_head * __percpu *path; }; =20 -#if IS_ENABLED(CONFIG_CORESIGHT) int etm_perf_symlink(struct coresight_device *csdev, bool link); int etm_perf_add_symlink_sink(struct coresight_device *csdev); void etm_perf_del_symlink_sink(struct coresight_device *csdev); @@ -77,23 +76,6 @@ static inline void *etm_perf_sink_config(struct perf_out= put_handle *handle) int etm_perf_add_symlink_cscfg(struct device *dev, struct cscfg_config_desc *config_desc); void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc); -#else -static inline int etm_perf_symlink(struct coresight_device *csdev, bool li= nk) -{ return -EINVAL; } -int etm_perf_add_symlink_sink(struct coresight_device *csdev) -{ return -EINVAL; } -void etm_perf_del_symlink_sink(struct coresight_device *csdev) {} -static inline void *etm_perf_sink_config(struct perf_output_handle *handle) -{ - return NULL; -} -int etm_perf_add_symlink_cscfg(struct device *dev, - struct cscfg_config_desc *config_desc) -{ return -EINVAL; } -void etm_perf_del_symlink_cscfg(struct cscfg_config_desc *config_desc) {} - -#endif /* CONFIG_CORESIGHT */ - int __init etm_perf_init(void); void etm_perf_exit(void); =20 --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 705BC16B397; Tue, 25 Jun 2024 13:33:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322422; cv=none; b=egWohO6JR3LyxH/VWdfH6oLVE6gGqhYzWm6wQoVML/o1VmMgZz2hctUQ+XaEZGc9iryv3S5dLZ1hWOOo0MEqoT9y7z9IUeVb4bu1Ms0Fi9viNOGWIEe0yxuyMRw4ikn2uWZeoAx2MrKoZNIVNcyuL6q2QdOlCrLFn4ciMLsR46g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322422; c=relaxed/simple; bh=wFlpTBjQ7b6ixH+wxY/aRCo3v9tll5/p+Sl/xnV6xpw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f2mL4meojZ/EDuqOvlRZPVoFCjx7i8Rvk6TXTBm6MVy8SnmYOSGFxJk+tHeO7KH3ApDm5WzsbsDvxEb1d3ne2O+SHkuBjP+bjYIBKvIsxDANkLvYdEFu1KLSJb6GUvKqqFLLWkdph/oghfYUufopl3hy3oBpncG6EDFIFNKbrqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A603CDA7; Tue, 25 Jun 2024 06:34:05 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 57DE13F73B; Tue, 25 Jun 2024 06:33:37 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 10/17] coresight: Clarify comments around the PID of the sink owner Date: Tue, 25 Jun 2024 14:30:53 +0100 Message-Id: <20240625133105.671245-11-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" "Process being monitored" and "pid of the process to monitor" imply that this would be the same PID if there were two sessions targeting the same process. But this is actually the PID of the process that did the Perf event open call, rather than the target of the session. So update the comments to make this clearer. Reviewed-by: Anshuman Khandual Reviewed-by: Mike Leach Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++-- drivers/hwtracing/coresight/coresight-tmc.h | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index e75428fa1592..8962fc27d04f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -36,7 +36,8 @@ struct etr_buf_hw { * etr_perf_buffer - Perf buffer used for ETR * @drvdata - The ETR drvdaga this buffer has been allocated for. * @etr_buf - Actual buffer used by the ETR - * @pid - The PID this etr_perf_buffer belongs to. + * @pid - The PID of the session owner that etr_perf_buffer + * belongs to. * @snaphost - Perf session mode * @nr_pages - Number of pages in the ring buffer. * @pages - Array of Pages in the ring buffer. @@ -1662,7 +1663,7 @@ static int tmc_enable_etr_sink_perf(struct coresight_= device *csdev, void *data) goto unlock_out; } =20 - /* Get a handle on the pid of the process to monitor */ + /* Get a handle on the pid of the session owner */ pid =3D etr_perf->pid; =20 /* Do not proceed if this device is associated with another session */ diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index c77763b49de0..2671926be62a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -171,8 +171,9 @@ struct etr_buf { * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.tmc" entry. * @spinlock: only one at a time pls. - * @pid: Process ID of the process being monitored by the session - * that is using this component. + * @pid: Process ID of the process that owns the session that is using + * this component. For example this would be the pid of the Perf + * process. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2FE9A15F3F9; Tue, 25 Jun 2024 13:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322431; cv=none; b=QkacynJgzCIHjsOvYk+cS9fu3JnE4eaz0TMMG8DOoq8QqsQhq42awX2pT9ae4418liiRomYpGt25qklKb6SGM6+fzUeup0wZWQOKWCmdd7AmjK9Q7yhUIfZxsU3iOfSSJ731qy1veL9HDMVmztnz9B31afAMXpcvzqFgiUIBZSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322431; c=relaxed/simple; bh=dURqEr78iL4SJ+PjS1h9hXb4BsJXz45pIuev3F2tKPI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MQUK18tcTTeMJtyWxdhbi1w27ugs2ABVe65HFKlkwujTYkoXG0fmtJleRyfcl7CfYg4vYMN08nkjIPOAwUnohXG3kHrh9j1Xa5BMcNrxrhMoWfT/nZDluu01g6mTjFErmN+MjYwL/Gm/Co7I18NmYuqsjhObM3J6U7iC1F9KTjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E05E150C; Tue, 25 Jun 2024 06:34:14 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0CE683F73B; Tue, 25 Jun 2024 06:33:45 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 11/17] coresight: Move struct coresight_trace_id_map to common header Date: Tue, 25 Jun 2024 14:30:54 +0100 Message-Id: <20240625133105.671245-12-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The trace ID maps will need to be created and stored by the core and Perf code so move the definition up to the common header. Reviewed-by: Anshuman Khandual Reviewed-by: Mike Leach Signed-off-by: James Clark --- .../hwtracing/coresight/coresight-trace-id.c | 1 + .../hwtracing/coresight/coresight-trace-id.h | 19 ------------------- include/linux/coresight.h | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index af5b4ef59cea..19005b5b4dc4 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -3,6 +3,7 @@ * Copyright (c) 2022, Linaro Limited, All rights reserved. * Author: Mike Leach */ +#include #include #include #include diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwt= racing/coresight/coresight-trace-id.h index 3797777d367e..49438a96fcc6 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.h +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -32,10 +32,6 @@ #include #include =20 - -/* architecturally we have 128 IDs some of which are reserved */ -#define CORESIGHT_TRACE_IDS_MAX 128 - /* ID 0 is reserved */ #define CORESIGHT_TRACE_ID_RES_0 0 =20 @@ -46,21 +42,6 @@ #define IS_VALID_CS_TRACE_ID(id) \ ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) =20 -/** - * Trace ID map. - * - * @used_ids: Bitmap to register available (bit =3D 0) and in use (bit =3D= 1) IDs. - * Initialised so that the reserved IDs are permanently marked as - * in use. - * @pend_rel_ids: CPU IDs that have been released by the trace source but = not - * yet marked as available, to allow re-allocation to the same - * CPU during a perf session. - */ -struct coresight_trace_id_map { - DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); - DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); -}; - /* Allocate and release IDs for a single default trace ID map */ =20 /** diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f09ace92176e..c16c61a8411d 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -218,6 +218,24 @@ struct coresight_sysfs_link { const char *target_name; }; =20 +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/** + * Trace ID map. + * + * @used_ids: Bitmap to register available (bit =3D 0) and in use (bit =3D= 1) IDs. + * Initialised so that the reserved IDs are permanently marked as + * in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but = not + * yet marked as available, to allow re-allocation to the same + * CPU during a perf session. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); +}; + /** * struct coresight_device - representation of a device as used by the fra= mework * @pdata: Platform data with device connections associated to this device. --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF6BB15F41D; Tue, 25 Jun 2024 13:33:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322440; cv=none; b=H+0Dfld/jIxL4NweeY1cP+6Y01Phd/u9H2RdQLJvhamn9/jqWMXM2jsJYcq3nZSWoiiHCyzt2mmx9jVBUvn1dvIO4ddJKkFuAiRdQFUY+kui+LiWfvt6GoGzqquCKgjgZTrFb6zzUQEXEb06yQ+k/MSwH7KT1qH/SbpdpcpMyxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322440; c=relaxed/simple; bh=P1WyyQPLwTQFk5WbskNdpN+wvmgxvGdDio47JAr50cM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TsShK7GA78RiUJLwHKtO7OVQGjaHho+KdSw6CeE/1ZnzUFMjDFtV8VHv+eHtA546iJfDtPzVTLgGPdB4mKA0eS17b3XqHvYctePf8oVNi66KSyjwhpFPadJZkGkUdT5FR8FdoQf6uLCFujumGrntE0OIDOHYD9hzDWJ+rBH+Qws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01B58DA7; Tue, 25 Jun 2024 06:34:23 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B5A9F3F73B; Tue, 25 Jun 2024 06:33:54 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 12/17] coresight: Expose map arguments in trace ID API Date: Tue, 25 Jun 2024 14:30:55 +0100 Message-Id: <20240625133105.671245-13-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The trace ID API is currently hard coded to always use the global map. Add public versions that allow the map to be passed in so that Perf mode can use per-sink maps. Keep the non-map versions so that sysfs mode can continue to use the default global map. System ID functions are unchanged because they will always use the default map. Signed-off-by: James Clark --- .../hwtracing/coresight/coresight-trace-id.c | 36 ++++++++++++++----- .../hwtracing/coresight/coresight-trace-id.h | 20 +++++++++-- 2 files changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index 19005b5b4dc4..5561989a03fa 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -12,7 +12,7 @@ =20 #include "coresight-trace-id.h" =20 -/* Default trace ID map. Used on systems that don't require per sink mappi= ngs */ +/* Default trace ID map. Used in sysfs mode and for system sources */ static struct coresight_trace_id_map id_map_default; =20 /* maintain a record of the mapping of IDs and pending releases per cpu */ @@ -47,7 +47,7 @@ static void coresight_trace_id_dump_table(struct coresigh= t_trace_id_map *id_map, #endif =20 /* unlocked read of current trace ID value for given CPU */ -static int _coresight_trace_id_read_cpu_id(int cpu) +static int _coresight_trace_id_read_cpu_id(int cpu, struct coresight_trace= _id_map *id_map) { return atomic_read(&per_cpu(cpu_id, cpu)); } @@ -152,7 +152,7 @@ static void coresight_trace_id_release_all_pending(void) DUMP_ID_MAP(id_map); } =20 -static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_tra= ce_id_map *id_map) +static int _coresight_trace_id_get_cpu_id(int cpu, struct coresight_trace_= id_map *id_map) { unsigned long flags; int id; @@ -160,7 +160,7 @@ static int coresight_trace_id_map_get_cpu_id(int cpu, s= truct coresight_trace_id_ spin_lock_irqsave(&id_map_lock, flags); =20 /* check for existing allocation for this CPU */ - id =3D _coresight_trace_id_read_cpu_id(cpu); + id =3D _coresight_trace_id_read_cpu_id(cpu, id_map); if (id) goto get_cpu_id_clr_pend; =20 @@ -196,13 +196,13 @@ static int coresight_trace_id_map_get_cpu_id(int cpu,= struct coresight_trace_id_ return id; } =20 -static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_tr= ace_id_map *id_map) +static void _coresight_trace_id_put_cpu_id(int cpu, struct coresight_trace= _id_map *id_map) { unsigned long flags; int id; =20 /* check for existing allocation for this CPU */ - id =3D _coresight_trace_id_read_cpu_id(cpu); + id =3D _coresight_trace_id_read_cpu_id(cpu, id_map); if (!id) return; =20 @@ -254,22 +254,40 @@ static void coresight_trace_id_map_put_system_id(stru= ct coresight_trace_id_map * =20 int coresight_trace_id_get_cpu_id(int cpu) { - return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); + return _coresight_trace_id_get_cpu_id(cpu, &id_map_default); } EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); =20 +int coresight_trace_id_get_cpu_id_map(int cpu, struct coresight_trace_id_m= ap *id_map) +{ + return _coresight_trace_id_get_cpu_id(cpu, id_map); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id_map); + void coresight_trace_id_put_cpu_id(int cpu) { - coresight_trace_id_map_put_cpu_id(cpu, &id_map_default); + _coresight_trace_id_put_cpu_id(cpu, &id_map_default); } EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); =20 +void coresight_trace_id_put_cpu_id_map(int cpu, struct coresight_trace_id_= map *id_map) +{ + _coresight_trace_id_put_cpu_id(cpu, id_map); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id_map); + int coresight_trace_id_read_cpu_id(int cpu) { - return _coresight_trace_id_read_cpu_id(cpu); + return _coresight_trace_id_read_cpu_id(cpu, &id_map_default); } EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); =20 +int coresight_trace_id_read_cpu_id_map(int cpu, struct coresight_trace_id_= map *id_map) +{ + return _coresight_trace_id_read_cpu_id(cpu, id_map); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id_map); + int coresight_trace_id_get_system_id(void) { return coresight_trace_id_map_get_system_id(&id_map_default); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwt= racing/coresight/coresight-trace-id.h index 49438a96fcc6..840babdd0794 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.h +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -42,8 +42,6 @@ #define IS_VALID_CS_TRACE_ID(id) \ ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) =20 -/* Allocate and release IDs for a single default trace ID map */ - /** * Read and optionally allocate a CoreSight trace ID and associate with a = CPU. * @@ -59,6 +57,12 @@ */ int coresight_trace_id_get_cpu_id(int cpu); =20 +/** + * Version of coresight_trace_id_get_cpu_id() that allows the ID map to op= erate + * on to be provided. + */ +int coresight_trace_id_get_cpu_id_map(int cpu, struct coresight_trace_id_m= ap *id_map); + /** * Release an allocated trace ID associated with the CPU. * @@ -72,6 +76,12 @@ int coresight_trace_id_get_cpu_id(int cpu); */ void coresight_trace_id_put_cpu_id(int cpu); =20 +/** + * Version of coresight_trace_id_put_cpu_id() that allows the ID map to op= erate + * on to be provided. + */ +void coresight_trace_id_put_cpu_id_map(int cpu, struct coresight_trace_id_= map *id_map); + /** * Read the current allocated CoreSight Trace ID value for the CPU. * @@ -92,6 +102,12 @@ void coresight_trace_id_put_cpu_id(int cpu); */ int coresight_trace_id_read_cpu_id(int cpu); =20 +/** + * Version of coresight_trace_id_read_cpu_id() that allows the ID map to o= perate + * on to be provided. + */ +int coresight_trace_id_read_cpu_id_map(int cpu, struct coresight_trace_id_= map *id_map); + /** * Allocate a CoreSight trace ID for a system component. * --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E2C316B74A; Tue, 25 Jun 2024 13:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; 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Tue, 25 Jun 2024 06:34:32 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B43D63F73B; Tue, 25 Jun 2024 06:34:03 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 13/17] coresight: Make CPU id map a property of a trace ID map Date: Tue, 25 Jun 2024 14:30:56 +0100 Message-Id: <20240625133105.671245-14-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global CPU ID mappings won't work for per-sink ID maps so move it to the ID map struct. coresight_trace_id_release_all_pending() is hard coded to operate on the default map, but once Perf sessions use their own maps the pending release mechanism will be deleted. So it doesn't need to be extended to accept a trace ID map argument at this point. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-trace-id.c | 16 +++++++++------- include/linux/coresight.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index 5561989a03fa..8a777c0af6ea 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -13,10 +13,12 @@ #include "coresight-trace-id.h" =20 /* Default trace ID map. Used in sysfs mode and for system sources */ -static struct coresight_trace_id_map id_map_default; +static DEFINE_PER_CPU(atomic_t, id_map_default_cpu_ids) =3D ATOMIC_INIT(0); +static struct coresight_trace_id_map id_map_default =3D { + .cpu_map =3D &id_map_default_cpu_ids +}; =20 -/* maintain a record of the mapping of IDs and pending releases per cpu */ -static DEFINE_PER_CPU(atomic_t, cpu_id) =3D ATOMIC_INIT(0); +/* maintain a record of the pending releases per cpu */ static cpumask_t cpu_id_release_pending; =20 /* perf session active counter */ @@ -49,7 +51,7 @@ static void coresight_trace_id_dump_table(struct coresigh= t_trace_id_map *id_map, /* unlocked read of current trace ID value for given CPU */ static int _coresight_trace_id_read_cpu_id(int cpu, struct coresight_trace= _id_map *id_map) { - return atomic_read(&per_cpu(cpu_id, cpu)); + return atomic_read(per_cpu_ptr(id_map->cpu_map, cpu)); } =20 /* look for next available odd ID, return 0 if none found */ @@ -145,7 +147,7 @@ static void coresight_trace_id_release_all_pending(void) clear_bit(bit, id_map->pend_rel_ids); } for_each_cpu(cpu, &cpu_id_release_pending) { - atomic_set(&per_cpu(cpu_id, cpu), 0); + atomic_set(per_cpu_ptr(id_map_default.cpu_map, cpu), 0); cpumask_clear_cpu(cpu, &cpu_id_release_pending); } spin_unlock_irqrestore(&id_map_lock, flags); @@ -181,7 +183,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, stru= ct coresight_trace_id_map goto get_cpu_id_out_unlock; =20 /* allocate the new id to the cpu */ - atomic_set(&per_cpu(cpu_id, cpu), id); + atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), id); =20 get_cpu_id_clr_pend: /* we are (re)using this ID - so ensure it is not marked for release */ @@ -215,7 +217,7 @@ static void _coresight_trace_id_put_cpu_id(int cpu, str= uct coresight_trace_id_ma } else { /* otherwise clear id */ coresight_trace_id_free(id, id_map); - atomic_set(&per_cpu(cpu_id, cpu), 0); + atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); } =20 spin_unlock_irqrestore(&id_map_lock, flags); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index c16c61a8411d..7d62b88bfb5c 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -234,6 +234,7 @@ struct coresight_sysfs_link { struct coresight_trace_id_map { DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); + atomic_t __percpu *cpu_map; }; =20 /** --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02A7215FA72; Tue, 25 Jun 2024 13:34:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322458; cv=none; b=ERApU6bwAuiNDpEFZ+vHSghv14vfWuQnzYnwnuUoOKFoYiUGmrUsHDCjZm77+lQ/UCoyyC7VDn4F37ZmbuBSjQK1+vVPHA3AFMO2m9ER8bsG5jxywCdVJbF3b1WDUMHsp/xAU1o0OrVQWzc22M/lw+5XSU3bdi6q/m9tPFL1mfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322458; c=relaxed/simple; bh=sjPYU+Br/XhTOaSskUpZzUsRzQZ5GFQukILG7BLyShc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P+DQJ+0a2iqtD6jfK+Sni+PyZE3J8xdjG52PlZ63OvGt3ouKWUyrFl4Z3RP60XyFN88MRL/Ubu9hW5cu929e6UimDYQ326Outqz0EtAAhkJB1wvZDZc54ZzP9tgihEEFQ5cYE/Y0uimLOXwwwrZn5733ud0nF+1Vw+zki1s2cMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55D18DA7; Tue, 25 Jun 2024 06:34:41 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0EC143F73B; Tue, 25 Jun 2024 06:34:12 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 14/17] coresight: Use per-sink trace ID maps for Perf sessions Date: Tue, 25 Jun 2024 14:30:57 +0100 Message-Id: <20240625133105.671245-15-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs as long as there are fewer than that many ETMs connected to each sink. Each sink owns its own trace ID map, and any Perf session connecting to that sink will allocate from it, even if the sink is currently in use by other users. This is similar to the existing behavior where the dynamic trace IDs are constant as long as there is any concurrent Perf session active. It's not completely optimal because slightly more IDs will be used than necessary, but the optimal solution involves tracking the PIDs of each session and allocating ID maps based on the session owner. This is difficult to do with the combination of per-thread and per-cpu modes and some scheduling issues. The complexity of this isn't likely to worth it because even with multiple users they'd just see a difference in the ordering of ID allocations rather than hitting any limits (unless the hardware does have too many ETMs connected to one sink). Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-core.c | 10 ++++++++++ drivers/hwtracing/coresight/coresight-dummy.c | 3 ++- drivers/hwtracing/coresight/coresight-etm-perf.c | 15 ++++++++++----- .../hwtracing/coresight/coresight-etm3x-core.c | 9 +++++---- .../hwtracing/coresight/coresight-etm4x-core.c | 9 +++++---- drivers/hwtracing/coresight/coresight-stm.c | 3 ++- drivers/hwtracing/coresight/coresight-sysfs.c | 3 ++- drivers/hwtracing/coresight/coresight-tpdm.c | 3 ++- include/linux/coresight.h | 3 ++- 9 files changed, 40 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 9fc6f6b863e0..faf560ba8d64 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -902,6 +902,7 @@ static void coresight_device_release(struct device *dev) struct coresight_device *csdev =3D to_coresight_device(dev); =20 fwnode_handle_put(csdev->dev.fwnode); + free_percpu(csdev->perf_sink_id_map.cpu_map); kfree(csdev); } =20 @@ -1159,6 +1160,15 @@ struct coresight_device *coresight_register(struct c= oresight_desc *desc) csdev->dev.fwnode =3D fwnode_handle_get(dev_fwnode(desc->dev)); dev_set_name(&csdev->dev, "%s", desc->name); =20 + if (csdev->type =3D=3D CORESIGHT_DEV_TYPE_SINK || + csdev->type =3D=3D CORESIGHT_DEV_TYPE_LINKSINK) { + csdev->perf_sink_id_map.cpu_map =3D alloc_percpu(atomic_t); + if (!csdev->perf_sink_id_map.cpu_map) { + kfree(csdev); + ret =3D -ENOMEM; + goto err_out; + } + } /* * Make sure the device registration and the connection fixup * are synchronised, so that we don't see uninitialised devices diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtrac= ing/coresight/coresight-dummy.c index ac70c0b491be..1f1b9ad160f6 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -21,7 +21,8 @@ DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); =20 static int dummy_source_enable(struct coresight_device *csdev, - struct perf_event *event, enum cs_mode mode) + struct perf_event *event, enum cs_mode mode, + __maybe_unused struct coresight_trace_id_map *id_map) { dev_dbg(csdev->dev.parent, "Dummy source enabled\n"); =20 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index c0c60e6a1703..7fb55dafb639 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -229,10 +229,13 @@ static void free_event_data(struct work_struct *work) struct list_head **ppath; =20 ppath =3D etm_event_cpu_path_ptr(event_data, cpu); - if (!(IS_ERR_OR_NULL(*ppath))) + if (!(IS_ERR_OR_NULL(*ppath))) { + struct coresight_device *sink =3D coresight_get_sink(*ppath); + + coresight_trace_id_put_cpu_id_map(cpu, &sink->perf_sink_id_map); coresight_release_path(*ppath); + } *ppath =3D NULL; - coresight_trace_id_put_cpu_id(cpu); } =20 /* mark perf event as done for trace id allocator */ @@ -401,7 +404,7 @@ static void *etm_setup_aux(struct perf_event *event, vo= id **pages, } =20 /* ensure we can allocate a trace ID for this CPU */ - trace_id =3D coresight_trace_id_get_cpu_id(cpu); + trace_id =3D coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_= map); if (!IS_VALID_CS_TRACE_ID(trace_id)) { cpumask_clear_cpu(cpu, mask); coresight_release_path(path); @@ -495,7 +498,8 @@ static void etm_event_start(struct perf_event *event, i= nt flags) goto fail_end_stop; =20 /* Finally enable the tracer */ - if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) + if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF, + &sink->perf_sink_id_map)) goto fail_disable_path; =20 /* @@ -507,7 +511,8 @@ static void etm_event_start(struct perf_event *event, i= nt flags) hw_id =3D FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION); hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, - coresight_trace_id_read_cpu_id(cpu)); + coresight_trace_id_read_cpu_id_map(cpu, + &sink->perf_sink_id_map)); perf_report_aux_output_id(event, hw_id); } =20 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index 8b362605d242..c103f4c70f5d 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -481,7 +481,8 @@ void etm_release_trace_id(struct etm_drvdata *drvdata) } =20 static int etm_enable_perf(struct coresight_device *csdev, - struct perf_event *event) + struct perf_event *event, + struct coresight_trace_id_map *id_map) { struct etm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); int trace_id; @@ -500,7 +501,7 @@ static int etm_enable_perf(struct coresight_device *csd= ev, * with perf locks - we know the ID cannot change until perf shuts down * the session */ - trace_id =3D coresight_trace_id_read_cpu_id(drvdata->cpu); + trace_id =3D coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); if (!IS_VALID_CS_TRACE_ID(trace_id)) { dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", dev_name(&drvdata->csdev->dev), drvdata->cpu); @@ -553,7 +554,7 @@ static int etm_enable_sysfs(struct coresight_device *cs= dev) } =20 static int etm_enable(struct coresight_device *csdev, struct perf_event *e= vent, - enum cs_mode mode) + enum cs_mode mode, struct coresight_trace_id_map *id_map) { int ret; struct etm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -568,7 +569,7 @@ static int etm_enable(struct coresight_device *csdev, s= truct perf_event *event, ret =3D etm_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret =3D etm_enable_perf(csdev, event); + ret =3D etm_enable_perf(csdev, event, id_map); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index bf01f01964cf..66d44a404ad0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -752,7 +752,8 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, } =20 static int etm4_enable_perf(struct coresight_device *csdev, - struct perf_event *event) + struct perf_event *event, + struct coresight_trace_id_map *id_map) { int ret =3D 0, trace_id; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); @@ -775,7 +776,7 @@ static int etm4_enable_perf(struct coresight_device *cs= dev, * with perf locks - we know the ID cannot change until perf shuts down * the session */ - trace_id =3D coresight_trace_id_read_cpu_id(drvdata->cpu); + trace_id =3D coresight_trace_id_read_cpu_id_map(drvdata->cpu, id_map); if (!IS_VALID_CS_TRACE_ID(trace_id)) { dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", dev_name(&drvdata->csdev->dev), drvdata->cpu); @@ -837,7 +838,7 @@ static int etm4_enable_sysfs(struct coresight_device *c= sdev) } =20 static int etm4_enable(struct coresight_device *csdev, struct perf_event *= event, - enum cs_mode mode) + enum cs_mode mode, struct coresight_trace_id_map *id_map) { int ret; =20 @@ -851,7 +852,7 @@ static int etm4_enable(struct coresight_device *csdev, = struct perf_event *event, ret =3D etm4_enable_sysfs(csdev); break; case CS_MODE_PERF: - ret =3D etm4_enable_perf(csdev, event); + ret =3D etm4_enable_perf(csdev, event, id_map); break; default: ret =3D -EINVAL; diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracin= g/coresight/coresight-stm.c index 117dbb484543..cb3e04755c99 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -194,7 +194,8 @@ static void stm_enable_hw(struct stm_drvdata *drvdata) } =20 static int stm_enable(struct coresight_device *csdev, struct perf_event *e= vent, - enum cs_mode mode) + enum cs_mode mode, + __maybe_unused struct coresight_trace_id_map *trace_id) { struct stm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtrac= ing/coresight/coresight-sysfs.c index 1e67cc7758d7..a01c9e54e2ed 100644 --- a/drivers/hwtracing/coresight/coresight-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-sysfs.c @@ -9,6 +9,7 @@ #include =20 #include "coresight-priv.h" +#include "coresight-trace-id.h" =20 /* * Use IDR to map the hash of the source's device name @@ -63,7 +64,7 @@ static int coresight_enable_source_sysfs(struct coresight= _device *csdev, */ lockdep_assert_held(&coresight_mutex); if (coresight_get_mode(csdev) !=3D CS_MODE_SYSFS) { - ret =3D source_ops(csdev)->enable(csdev, data, mode); + ret =3D source_ops(csdev)->enable(csdev, data, mode, NULL); if (ret) return ret; } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index 0726f8842552..0a5e20cf23e8 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -439,7 +439,8 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) } =20 static int tpdm_enable(struct coresight_device *csdev, struct perf_event *= event, - enum cs_mode mode) + enum cs_mode mode, + __maybe_unused struct coresight_trace_id_map *id_map) { struct tpdm_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); =20 diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7d62b88bfb5c..9c3067e2e38b 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -290,6 +290,7 @@ struct coresight_device { bool sysfs_sink_activated; struct dev_ext_attribute *ea; struct coresight_device *def_sink; + struct coresight_trace_id_map perf_sink_id_map; /* sysfs links between components */ int nr_links; bool has_conns_grp; @@ -384,7 +385,7 @@ struct coresight_ops_link { struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, - enum cs_mode mode); + enum cs_mode mode, struct coresight_trace_id_map *id_map); void (*disable)(struct coresight_device *csdev, struct perf_event *event); }; --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF2C916A95F; Tue, 25 Jun 2024 13:34:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4AEC5DA7; Tue, 25 Jun 2024 06:34:50 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D1F4E3F73B; Tue, 25 Jun 2024 06:34:21 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 15/17] coresight: Remove pending trace ID release mechanism Date: Tue, 25 Jun 2024 14:30:58 +0100 Message-Id: <20240625133105.671245-16-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Pending the release of IDs was a way of managing concurrent sysfs and Perf sessions in a single global ID map. Perf may have finished while sysfs hadn't, and Perf shouldn't release the IDs in use by sysfs and vice versa. Now that Perf uses its own exclusive ID maps, pending release doesn't result in any different behavior than just releasing all IDs when the last Perf session finishes. As part of the per-sink trace ID change, we would have still had to make the pending mechanism work on a per-sink basis, due to the overlapping ID allocations, so instead of making that more complicated, just remove it. Signed-off-by: James Clark --- .../hwtracing/coresight/coresight-etm-perf.c | 11 ++-- .../hwtracing/coresight/coresight-trace-id.c | 62 +++++-------------- .../hwtracing/coresight/coresight-trace-id.h | 31 +++++----- include/linux/coresight.h | 6 +- 4 files changed, 34 insertions(+), 76 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 7fb55dafb639..17fa29969643 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -232,15 +232,14 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) { struct coresight_device *sink =3D coresight_get_sink(*ppath); =20 - coresight_trace_id_put_cpu_id_map(cpu, &sink->perf_sink_id_map); + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(&sink->perf_sink_id_map); + coresight_release_path(*ppath); } *ppath =3D NULL; } =20 - /* mark perf event as done for trace id allocator */ - coresight_trace_id_perf_stop(); - free_percpu(event_data->path); kfree(event_data); } @@ -328,9 +327,6 @@ static void *etm_setup_aux(struct perf_event *event, vo= id **pages, sink =3D user_sink =3D coresight_get_sink_by_id(id); } =20 - /* tell the trace ID allocator that a perf event is starting up */ - coresight_trace_id_perf_start(); - /* check if user wants a coresight configuration selected */ cfg_hash =3D (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -411,6 +407,7 @@ static void *etm_setup_aux(struct perf_event *event, vo= id **pages, continue; } =20 + coresight_trace_id_perf_start(&sink->perf_sink_id_map); *etm_event_cpu_path_ptr(event_data, cpu) =3D path; } =20 diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index 8a777c0af6ea..1e70892f5beb 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -18,12 +18,6 @@ static struct coresight_trace_id_map id_map_default =3D { .cpu_map =3D &id_map_default_cpu_ids }; =20 -/* maintain a record of the pending releases per cpu */ -static cpumask_t cpu_id_release_pending; - -/* perf session active counter */ -static atomic_t perf_cs_etm_session_active =3D ATOMIC_INIT(0); - /* lock to protect id_map and cpu data */ static DEFINE_SPINLOCK(id_map_lock); =20 @@ -122,34 +116,18 @@ static void coresight_trace_id_free(int id, struct co= resight_trace_id_map *id_ma clear_bit(id, id_map->used_ids); } =20 -static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace= _id_map *id_map) -{ - if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) - return; - set_bit(id, id_map->pend_rel_ids); -} - /* - * release all pending IDs for all current maps & clear CPU associations - * - * This currently operates on the default id map, but may be extended to - * operate on all registered id maps if per sink id maps are used. + * Release all IDs and clear CPU associations. */ -static void coresight_trace_id_release_all_pending(void) +static void coresight_trace_id_release_all(struct coresight_trace_id_map *= id_map) { - struct coresight_trace_id_map *id_map =3D &id_map_default; unsigned long flags; - int cpu, bit; + int cpu; =20 spin_lock_irqsave(&id_map_lock, flags); - for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) { - clear_bit(bit, id_map->used_ids); - clear_bit(bit, id_map->pend_rel_ids); - } - for_each_cpu(cpu, &cpu_id_release_pending) { - atomic_set(per_cpu_ptr(id_map_default.cpu_map, cpu), 0); - cpumask_clear_cpu(cpu, &cpu_id_release_pending); - } + bitmap_zero(id_map->used_ids, CORESIGHT_TRACE_IDS_MAX); + for_each_possible_cpu(cpu) + atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); spin_unlock_irqrestore(&id_map_lock, flags); DUMP_ID_MAP(id_map); } @@ -164,7 +142,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, stru= ct coresight_trace_id_map /* check for existing allocation for this CPU */ id =3D _coresight_trace_id_read_cpu_id(cpu, id_map); if (id) - goto get_cpu_id_clr_pend; + goto get_cpu_id_out_unlock; =20 /* * Find a new ID. @@ -185,11 +163,6 @@ static int _coresight_trace_id_get_cpu_id(int cpu, str= uct coresight_trace_id_map /* allocate the new id to the cpu */ atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), id); =20 -get_cpu_id_clr_pend: - /* we are (re)using this ID - so ensure it is not marked for release */ - cpumask_clear_cpu(cpu, &cpu_id_release_pending); - clear_bit(id, id_map->pend_rel_ids); - get_cpu_id_out_unlock: spin_unlock_irqrestore(&id_map_lock, flags); =20 @@ -210,15 +183,8 @@ static void _coresight_trace_id_put_cpu_id(int cpu, st= ruct coresight_trace_id_ma =20 spin_lock_irqsave(&id_map_lock, flags); =20 - if (atomic_read(&perf_cs_etm_session_active)) { - /* set release at pending if perf still active */ - coresight_trace_id_set_pend_rel(id, id_map); - cpumask_set_cpu(cpu, &cpu_id_release_pending); - } else { - /* otherwise clear id */ - coresight_trace_id_free(id, id_map); - atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); - } + coresight_trace_id_free(id, id_map); + atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); =20 spin_unlock_irqrestore(&id_map_lock, flags); DUMP_ID_CPU(cpu, id); @@ -302,17 +268,17 @@ void coresight_trace_id_put_system_id(int id) } EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); =20 -void coresight_trace_id_perf_start(void) +void coresight_trace_id_perf_start(struct coresight_trace_id_map *id_map) { - atomic_inc(&perf_cs_etm_session_active); + atomic_inc(&id_map->perf_cs_etm_session_active); PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); =20 -void coresight_trace_id_perf_stop(void) +void coresight_trace_id_perf_stop(struct coresight_trace_id_map *id_map) { - if (!atomic_dec_return(&perf_cs_etm_session_active)) - coresight_trace_id_release_all_pending(); + if (!atomic_dec_return(&id_map->perf_cs_etm_session_active)) + coresight_trace_id_release_all(id_map); PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); } EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwt= racing/coresight/coresight-trace-id.h index 840babdd0794..9aae50a553ca 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.h +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -17,9 +17,10 @@ * released when done. * * In order to ensure that a consistent cpu / ID matching is maintained - * throughout a perf cs_etm event session - a session in progress flag will - * be maintained, and released IDs not cleared until the perf session is - * complete. This allows the same CPU to be re-allocated its prior ID. + * throughout a perf cs_etm event session - a session in progress flag wil= l be + * maintained for each sink, and IDs are cleared when all the perf sessions + * complete. This allows the same CPU to be re-allocated its prior ID when + * events are scheduled in and out. * * * Trace ID maps will be created and initialised to prevent architecturally @@ -66,11 +67,7 @@ int coresight_trace_id_get_cpu_id_map(int cpu, struct co= resight_trace_id_map *id /** * Release an allocated trace ID associated with the CPU. * - * This will release the CoreSight trace ID associated with the CPU, - * unless a perf session is in operation. - * - * If a perf session is in operation then the ID will be marked as pending - * release. + * This will release the CoreSight trace ID associated with the CPU. * * @cpu: The CPU index to release the associated trace ID. */ @@ -133,21 +130,21 @@ void coresight_trace_id_put_system_id(int id); /** * Notify the Trace ID allocator that a perf session is starting. * - * Increase the perf session reference count - called by perf when setting= up - * a trace event. + * Increase the perf session reference count - called by perf when setting= up a + * trace event. * - * This reference count is used by the ID allocator to ensure that trace I= Ds - * associated with a CPU cannot change or be released during a perf sessio= n. + * Perf sessions never free trace IDs to ensure that the ID associated wit= h a + * CPU cannot change during their and other's concurrent sessions. Instead, + * this refcount is used so that the last event to finish always frees all= IDs. */ -void coresight_trace_id_perf_start(void); +void coresight_trace_id_perf_start(struct coresight_trace_id_map *id_map); =20 /** * Notify the ID allocator that a perf session is stopping. * - * Decrease the perf session reference count. - * if this causes the count to go to zero, then all Trace IDs marked as pe= nding - * release, will be released. + * Decrease the perf session reference count. If this causes the count to = go to + * zero, then all Trace IDs will be released. */ -void coresight_trace_id_perf_stop(void); +void coresight_trace_id_perf_stop(struct coresight_trace_id_map *id_map); =20 #endif /* _CORESIGHT_TRACE_ID_H */ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 9c3067e2e38b..197949fd2c35 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -227,14 +227,12 @@ struct coresight_sysfs_link { * @used_ids: Bitmap to register available (bit =3D 0) and in use (bit =3D= 1) IDs. * Initialised so that the reserved IDs are permanently marked as * in use. - * @pend_rel_ids: CPU IDs that have been released by the trace source but = not - * yet marked as available, to allow re-allocation to the same - * CPU during a perf session. + * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. */ struct coresight_trace_id_map { DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); - DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); atomic_t __percpu *cpu_map; + atomic_t perf_cs_etm_session_active; }; =20 /** --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 85D2E158D83; Tue, 25 Jun 2024 13:34:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322476; cv=none; b=DR5hlPlh6+YjUdx7MmeaHoubQyLGOd7iIx2b2K6no+dvuJLVjAoIsRk5N8O0z/+QBuusksE+lDHefy3mpk22hylLjhY/Dh6RwB0XRHTgPdHq67SSG9rT+2Sx9elrsB5+1IUc69bPqaIQt28S0WAC/ed6fhHHRtQJGXv82JJ4+s4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719322476; c=relaxed/simple; bh=qFgNbWqKqw9PxGuyaC1m+PSrSLUDlaGl12Oo39hymxo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NqhvbtvatQ9uPh3vDlK1tlz2++UHYVCei9/h/ZYmx0CgJCV1zDB+mZn2ZjG68ngvBTd5INfoEbIDlWzOFcRpgdsIC34zCE93Z4Te8Ayagovr44WDy3IyXmPlLYUhhdS/OEoy1pkKf5HsQHDy2cFawYueVGLXZTAx5zP1jRhTilQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D6ADFDA7; Tue, 25 Jun 2024 06:34:58 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 859ED3F73B; Tue, 25 Jun 2024 06:34:30 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 16/17] coresight: Emit sink ID in the HW_ID packets Date: Tue, 25 Jun 2024 14:30:59 +0100 Message-Id: <20240625133105.671245-17-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Perf to be able to decode when per-sink trace IDs are used, emit the sink that's being written to for each ETM. Perf currently errors out if it sees a newer packet version so instead of bumping it, add a new minor version field. This can be used to signify new versions that have backwards compatible fields. Considering this change is only for high core count machines, it doesn't make sense to make a breaking change for everyone. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-core.c | 26 ++++++++++--------- .../hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++---- drivers/hwtracing/coresight/coresight-priv.h | 1 + include/linux/coresight-pmu.h | 17 +++++++++--- 4 files changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index faf560ba8d64..c427e9344a84 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -487,23 +487,25 @@ struct coresight_device *coresight_get_sink(struct li= st_head *path) return csdev; } =20 +u32 coresight_get_sink_id(struct coresight_device *csdev) +{ + if (!csdev->ea) + return 0; + + /* + * See function etm_perf_add_symlink_sink() to know where + * this comes from. + */ + return (u32) (unsigned long) csdev->ea->var; +} + static int coresight_sink_by_id(struct device *dev, const void *data) { struct coresight_device *csdev =3D to_coresight_device(dev); - unsigned long hash; =20 if (csdev->type =3D=3D CORESIGHT_DEV_TYPE_SINK || - csdev->type =3D=3D CORESIGHT_DEV_TYPE_LINKSINK) { - - if (!csdev->ea) - return 0; - /* - * See function etm_perf_add_symlink_sink() to know where - * this comes from. - */ - hash =3D (unsigned long)csdev->ea->var; - - if ((u32)hash =3D=3D *(u32 *)data) + csdev->type =3D=3D CORESIGHT_DEV_TYPE_LINKSINK) { + if (coresight_get_sink_id(csdev) =3D=3D *(u32 *)data) return 1; } =20 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index 17fa29969643..9bbc41f4b0af 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -453,6 +453,7 @@ static void etm_event_start(struct perf_event *event, i= nt flags) struct coresight_device *sink, *csdev =3D per_cpu(csdev_src, cpu); struct list_head *path; u64 hw_id; + u8 trace_id; =20 if (!csdev) goto fail; @@ -505,11 +506,16 @@ static void etm_event_start(struct perf_event *event,= int flags) */ if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) { cpumask_set_cpu(cpu, &event_data->aux_hwid_done); - hw_id =3D FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, - CS_AUX_HW_ID_CURR_VERSION); - hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, - coresight_trace_id_read_cpu_id_map(cpu, - &sink->perf_sink_id_map)); + + trace_id =3D coresight_trace_id_read_cpu_id_map(cpu, &sink->perf_sink_id= _map); + + hw_id =3D FIELD_PREP(CS_AUX_HW_ID_MAJOR_VERSION_MASK, + CS_AUX_HW_ID_MAJOR_VERSION); + hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_MINOR_VERSION_MASK, + CS_AUX_HW_ID_MINOR_VERSION); + hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, trace_id); + hw_id |=3D FIELD_PREP(CS_AUX_HW_ID_SINK_ID_MASK, coresight_get_sink_id(s= ink)); + perf_report_aux_output_id(event, hw_id); } =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 61a46d3bdcc8..05f891ca6b5c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -148,6 +148,7 @@ int coresight_make_links(struct coresight_device *orig, struct coresight_device *target); void coresight_remove_links(struct coresight_device *orig, struct coresight_connection *conn); +u32 coresight_get_sink_id(struct coresight_device *csdev); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) extern int etm_readl_cp14(u32 off, unsigned int *val); diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 51ac441a37c3..89b0ac0014b0 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -49,12 +49,21 @@ * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. * Used to associate a CPU with the CoreSight Trace ID. * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. - * [59:08] - Unused (SBZ) - * [63:60] - Version + * [39:08] - Sink ID - as reported in /sys/bus/event_source/devices/cs_etm= /sinks/ + * Added in minor version 1. + * [55:40] - Unused (SBZ) + * [59:56] - Minor Version - previously existing fields are compatible with + * all minor versions. + * [63:60] - Major Version - previously existing fields mean different thi= ngs + * in new major versions. */ #define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) -#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) +#define CS_AUX_HW_ID_SINK_ID_MASK GENMASK_ULL(39, 8) =20 -#define CS_AUX_HW_ID_CURR_VERSION 0 +#define CS_AUX_HW_ID_MINOR_VERSION_MASK GENMASK_ULL(59, 56) +#define CS_AUX_HW_ID_MAJOR_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_MAJOR_VERSION 0 +#define CS_AUX_HW_ID_MINOR_VERSION 1 =20 #endif --=20 2.34.1 From nobody Wed Dec 17 19:20:54 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1A075158D83; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FF63DA7; Tue, 25 Jun 2024 06:35:07 -0700 (PDT) Received: from e127643.broadband (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 18D6C3F73B; Tue, 25 Jun 2024 06:34:38 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, suzuki.poulose@arm.com, gankulkarni@os.amperecomputing.com, mike.leach@linaro.org, leo.yan@linux.dev, anshuman.khandual@arm.com, jszu@nvidia.com, bwicaksono@nvidia.com Cc: James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , John Garry , Will Deacon , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-perf-users@vger.kernel.org Subject: [PATCH v4 17/17] coresight: Make trace ID map spinlock local to the map Date: Tue, 25 Jun 2024 14:31:00 +0100 Message-Id: <20240625133105.671245-18-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240625133105.671245-1-james.clark@arm.com> References: <20240625133105.671245-1-james.clark@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reduce contention on the lock by replacing the global lock with one for each map. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-core.c | 1 + .../hwtracing/coresight/coresight-trace-id.c | 26 +++++++++---------- include/linux/coresight.h | 1 + 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index c427e9344a84..ea38ecf26fcb 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1164,6 +1164,7 @@ struct coresight_device *coresight_register(struct co= resight_desc *desc) =20 if (csdev->type =3D=3D CORESIGHT_DEV_TYPE_SINK || csdev->type =3D=3D CORESIGHT_DEV_TYPE_LINKSINK) { + spin_lock_init(&csdev->perf_sink_id_map.lock); csdev->perf_sink_id_map.cpu_map =3D alloc_percpu(atomic_t); if (!csdev->perf_sink_id_map.cpu_map) { kfree(csdev); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwt= racing/coresight/coresight-trace-id.c index 1e70892f5beb..82bb70c1ad73 100644 --- a/drivers/hwtracing/coresight/coresight-trace-id.c +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -15,12 +15,10 @@ /* Default trace ID map. Used in sysfs mode and for system sources */ static DEFINE_PER_CPU(atomic_t, id_map_default_cpu_ids) =3D ATOMIC_INIT(0); static struct coresight_trace_id_map id_map_default =3D { - .cpu_map =3D &id_map_default_cpu_ids + .cpu_map =3D &id_map_default_cpu_ids, + .lock =3D __SPIN_LOCK_UNLOCKED(id_map_default.lock) }; =20 -/* lock to protect id_map and cpu data */ -static DEFINE_SPINLOCK(id_map_lock); - /* #define TRACE_ID_DEBUG 1 */ #if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST) =20 @@ -124,11 +122,11 @@ static void coresight_trace_id_release_all(struct cor= esight_trace_id_map *id_map unsigned long flags; int cpu; =20 - spin_lock_irqsave(&id_map_lock, flags); + spin_lock_irqsave(&id_map->lock, flags); bitmap_zero(id_map->used_ids, CORESIGHT_TRACE_IDS_MAX); for_each_possible_cpu(cpu) atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); - spin_unlock_irqrestore(&id_map_lock, flags); + spin_unlock_irqrestore(&id_map->lock, flags); DUMP_ID_MAP(id_map); } =20 @@ -137,7 +135,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, stru= ct coresight_trace_id_map unsigned long flags; int id; =20 - spin_lock_irqsave(&id_map_lock, flags); + spin_lock_irqsave(&id_map->lock, flags); =20 /* check for existing allocation for this CPU */ id =3D _coresight_trace_id_read_cpu_id(cpu, id_map); @@ -164,7 +162,7 @@ static int _coresight_trace_id_get_cpu_id(int cpu, stru= ct coresight_trace_id_map atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), id); =20 get_cpu_id_out_unlock: - spin_unlock_irqrestore(&id_map_lock, flags); + spin_unlock_irqrestore(&id_map->lock, flags); =20 DUMP_ID_CPU(cpu, id); DUMP_ID_MAP(id_map); @@ -181,12 +179,12 @@ static void _coresight_trace_id_put_cpu_id(int cpu, s= truct coresight_trace_id_ma if (!id) return; =20 - spin_lock_irqsave(&id_map_lock, flags); + spin_lock_irqsave(&id_map->lock, flags); =20 coresight_trace_id_free(id, id_map); atomic_set(per_cpu_ptr(id_map->cpu_map, cpu), 0); =20 - spin_unlock_irqrestore(&id_map_lock, flags); + spin_unlock_irqrestore(&id_map->lock, flags); DUMP_ID_CPU(cpu, id); DUMP_ID_MAP(id_map); } @@ -196,10 +194,10 @@ static int coresight_trace_id_map_get_system_id(struc= t coresight_trace_id_map *i unsigned long flags; int id; =20 - spin_lock_irqsave(&id_map_lock, flags); + spin_lock_irqsave(&id_map->lock, flags); /* prefer odd IDs for system components to avoid legacy CPU IDS */ id =3D coresight_trace_id_alloc_new_id(id_map, 0, true); - spin_unlock_irqrestore(&id_map_lock, flags); + spin_unlock_irqrestore(&id_map->lock, flags); =20 DUMP_ID(id); DUMP_ID_MAP(id_map); @@ -210,9 +208,9 @@ static void coresight_trace_id_map_put_system_id(struct= coresight_trace_id_map * { unsigned long flags; =20 - spin_lock_irqsave(&id_map_lock, flags); + spin_lock_irqsave(&id_map->lock, flags); coresight_trace_id_free(id, id_map); - spin_unlock_irqrestore(&id_map_lock, flags); + spin_unlock_irqrestore(&id_map->lock, flags); =20 DUMP_ID(id); DUMP_ID_MAP(id_map); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 197949fd2c35..c13342594278 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -233,6 +233,7 @@ struct coresight_trace_id_map { DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); atomic_t __percpu *cpu_map; atomic_t perf_cs_etm_session_active; + spinlock_t lock; }; =20 /** --=20 2.34.1