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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:23 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:10 +0200 Subject: [PATCH v4 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-5-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=BlXBbM1o+PokhijSw+a2fl1gngXBbq3ayq9OQmI+TCgtGvPpsbaOQBkdjIvAjvDF7aXjlDpJH esr8rfv+fDKDgRA+7vpMkcyhgkuyqJI/f62VXU0kMJnbmcR074FZ4FI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region =3D <&gpu_micro_code_mem>; }; =20 - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 + opp-719000000 { + opp-hz =3D /bits/ 64 <719000000>; + opp-level =3D ; + opp-supported-hw =3D <0x1>; + }; + opp-680000000 { opp-hz =3D /bits/ 64 <680000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-615000000 { opp-hz =3D /bits/ 64 <615000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-550000000 { opp-hz =3D /bits/ 64 <550000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-475000000 { opp-hz =3D /bits/ 64 <475000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-401000000 { opp-hz =3D /bits/ 64 <401000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-348000000 { opp-hz =3D /bits/ 64 <348000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-295000000 { opp-hz =3D /bits/ 64 <295000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-220000000 { opp-hz =3D /bits/ 64 <220000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; + }; + + opp-124800000 { + opp-hz =3D /bits/ 64 <124800000>; + opp-level =3D ; + opp-supported-hw =3D <0x3>; }; }; }; --=20 2.45.2