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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:15 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:06 +0200 Subject: [PATCH v4 1/5] drm/msm/adreno: Implement SMEM-based speed bin Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-1-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=5838; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZXaBkJpkEi6I9lto/tGjByodIdA+A4HUW8SYjctW8+0=; b=7EbrsfA01bwk4JX0dOd021Lq44oCnoz/hsE+x15jRkJm2+pP6b+4RD6RGaveF7IiCeVYhv9SI SWjs8yQ7sFHB8vwYlQX3GdafSYlma2n1DeBvzX4tRAgsx9JkhGEoXpu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Due to the product code being ignored in the context of Adreno on production parts (as of SM8650), hardcode it to SOCINFO_PC_UNKNOWN. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 41 ++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++- 4 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index c98cdb1e9326..8ace096bb68c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2124,13 +2124,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info= *info, u32 fuse) return UINT_MAX; } =20 -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_i= nfo *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; =20 - ret =3D adreno_read_speedbin(dev, &speedbin); + ret =3D adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -2290,7 +2292,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 - ret =3D a6xx_set_supported_hw(&pdev->dev, config->info); + ret =3D a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 1e789ff6945e..e514346088f9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ =20 +#include + #include "adreno_gpu.h" =20 bool hang_debug =3D false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 1c6626747b98..6ffd02f38499 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" =20 +#include +#include + static u64 address_space_size =3D 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes priva= te GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1061,9 +1064,39 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *a= dreno_ocmem) adreno_ocmem->hdl); } =20 -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode; + int ret; + + /* + * Try reading the speedbin via a nvmem cell first + * -ENOENT means "no nvmem-cells" and essentially means "old DT" or + * "nvmem fuse is irrelevant", simply assume it's fine. + */ + ret =3D nvmem_cell_read_variable_le_u32(dev, "speed_bin", fuse); + if (!ret) + return 0; + else if (ret !=3D -ENOENT) + return dev_err_probe(dev, ret, "Couldn't read the speed bin fuse value\n= "); + +#ifdef CONFIG_QCOM_SMEM + /* + * Only check the feature code - the product code only matters for + * proto SoCs unavailable outside Qualcomm labs, as far as GPU bin + * matching is concerned. + * + * Ignore EOPNOTSUPP, as not all SoCs expose this info through SMEM. + */ + ret =3D qcom_smem_get_feature_code(&fcode); + if (!ret) + *fuse =3D ADRENO_SKU_ID(fcode); + else if (ret !=3D -EOPNOTSUPP) + return dev_err_probe(dev, ret, "Couldn't get feature code from SMEM\n"); +#endif + + return 0; } =20 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1102,9 +1135,9 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } =20 - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin =3D 0xffff; - adreno_gpu->speedbin =3D (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin =3D speedbin; =20 gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index cff8ce541d2c..563c08b44624 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -79,6 +79,10 @@ struct adreno_reglist { =20 struct adreno_speedbin { uint16_t fuse; +/* As of SM8650, PCODE on production SoCs is meaningless wrt the GPU bin */ +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(fcode) (fcode) + uint16_t speedbin; }; =20 @@ -545,7 +549,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned = long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); =20 -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); =20 /* * For a5xx and a6xx targets load the zap shader that is used to pull the = GPU --=20 2.45.2 From nobody Thu Dec 18 20:24:59 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D4AD17C230 for ; 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:17 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:07 +0200 Subject: [PATCH v4 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-2-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=1481; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=pgXB3ku76GP+Ynds4TGlmCZD8EhfvV2JMzgzNC6TMuc=; b=4pAQCD48WMIG4yPsA0ws8Nht+e2p4Y2ez7R8+XZVKTh1CmihZSf2KTi89K6tp6SMOv2htCcc3 eDOPlXUrflcDo3HEbFZc5BtkIKqfE7vvJ9frwICe6+2ScwBiA3Jwcrx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add speebin data for A740, as found on SM8550 and derivative SoCs. For non-development SoCs it seems that "everything except FC_AC, FC_AF should be speedbin 1", but what the values are for said "everything" are not known, so that's an exercise left to the user.. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 53e33ff78411..8f280d69ba71 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -11,6 +11,9 @@ #include "a6xx.xml.h" #include "a6xx_gmu.xml.h" =20 +#include +#include + static const struct adreno_reglist a612_hwcg[] =3D { {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, @@ -1208,6 +1211,11 @@ static const struct adreno_info a7xx_gpus[] =3D { .protect =3D &a730_protect, }, .address_space_size =3D SZ_16G, + .speedbins =3D ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, + /* Other feature codes (on prod SoCs) should match to speedbin 1 */ + ), }, { .chip_ids =3D ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family =3D ADRENO_7XX_GEN3, --=20 2.45.2 From nobody Thu Dec 18 20:24:59 2025 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35AA017C22A for ; Tue, 25 Jun 2024 18:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340103; cv=none; b=qr91u1r8qa80YJhC8pbaxArdAzxddvAZ++ElBkePZGGDUS+q7VfJODHz3JT9UeEJvY7ef4y75WObucRY8ozvLW6aSMxoNLeTF09CuotBuFNNABQ65GJaYKc3wbHlBl4ScYLxKPFaDsFQ4SF15j2BXrNIBAWu778m7AOKHueE0CQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340103; c=relaxed/simple; bh=hlAsvCKJeJlsvCjk6T4iu/SvTfq4qoydQ2dHeLtqkkA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oyXWR54H/sxgeKyKW5FnXoOCx88KLrtV/P/VxkBC7tz++18vo05GmiwXLyjhWv19XjP1wO8kmtql8yZQ9Xh0UQXzXbYiaPJQe0l0QvdjQLqnVA8cF43vLJL54XzDx6QJXroPTs1MgrXX4B7AuchwsXlt0eUjAZM26cStPVyPOt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VT6AykHP; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VT6AykHP" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-57cb9a370ddso6878030a12.1 for ; Tue, 25 Jun 2024 11:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340100; x=1719944900; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xNl1LGe+OUBjKkWza/syUNm4iRQsXOqi9TzG6uI03xo=; b=VT6AykHPus/YVtB0DbJKyFvP92iUb59yDh3Cta7j8SMj6HaSliBYYuzNsbJaVOzRue e8+hoF8e2NkoMcnCuGySNDN0qfh8lm9njH0Dr3DuNLJFiioIVvrg0oy7OOoiVahliVzR 6sTzxpbgL/yf1fbLvjQL11/hc2h7zY0LLrRsAPiwXVkuxr7XfcCagZUfsdSkCsm9W+1y lz/V24AajqW+SQjKxPPGAtM7O3v5LzEpCFelS1KM1KiLrqGnEN5uN4fwYz9x9+uGQTwM eZlivp7MVMmmGVPPa15fZPvsapmucgjfKxi2ikC0o885d/VyHDl6EEcfLJCKSl2ZNQir bvVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340100; x=1719944900; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xNl1LGe+OUBjKkWza/syUNm4iRQsXOqi9TzG6uI03xo=; b=Ngtqov/F64EBztdHt5vlmNBYOJlHIlbmFLkjHpvpgmJXgHrlQ/Bn6mDsMb4l8x8WgG UXqXwvqlCLrbmDBmcOxthnq11a2UH+we09zhuo0UHiKIRMhXFx5WGKHQ7STbveFdrz4u MmFrqiMlMTpYg3PHfD1nw7sm8cwg0c00pugbsZmz4OZ3bw5kSrVf1jVVOHcLjyg/EF8H lUgCKUEYDmPL0azH9oUENsx4VOA+a4wZ9oyVI5mo0Og0u3eQMuOUUbAWS/SMNQg7Pr/M agZSZ577UIQZhVGxm+3Qeqn1VFHAb4IK4I0n92Bk+HuRzp5zsOyeTAdjzOeeXquA8Q5R k+Ww== X-Forwarded-Encrypted: i=1; AJvYcCUDj5l23Gv+DG7qFWns6UQd3PeW46AaQd7akt4aMZoYw9ayd5pWDyZsDc6j8jQwYb3x95+tS/1esp5fqD/NO5o4hvhQHxpzGUGOZek8 X-Gm-Message-State: AOJu0YyZ0vaRvL87AApWLi1epvgKdRUklwNfdozrsmJ9rrydKdYXAIgO TRHmtqVBtMPazY8kfKsuC/u2rsg1S++NwPdRCf13YLJhtGDoBHZ1WgY0VlEXLKM= X-Google-Smtp-Source: AGHT+IFZf75V6EVKFoeMMT86fpiVICPajQFEHJC9qNUtbTjyoSjlwEE+EJZ1PD+TboCYI1SSsb8bUw== X-Received: by 2002:aa7:d393:0:b0:57d:5600:2c94 with SMTP id 4fb4d7f45d1cf-57d56003448mr5183567a12.0.1719340100400; Tue, 25 Jun 2024 11:28:20 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:20 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:08 +0200 Subject: [PATCH v4 3/5] drm/msm/adreno: Define A530 speed bins explicitly Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-3-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hlAsvCKJeJlsvCjk6T4iu/SvTfq4qoydQ2dHeLtqkkA=; b=IRMR1HRLN2YRjxVqz6xKwmuxF680eWYXDX4vQzB+gFNVfylWuVcDos2bQwzKA7wmZ4U3gJ32x gg7nzrlgLmLBSFRvmSiO2FyHkPwIZb+ULPTqUvjdw9Y1u9Ob9HaCm+V X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In preparation for commonizing the speedbin handling code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a5xx_catalog.c index 455a953dee67..c98ad4ea558c 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_catalog.c @@ -116,6 +116,12 @@ static const struct adreno_info a5xx_gpus[] =3D { ADRENO_QUIRK_FAULT_DETECT_MASK, .init =3D a5xx_gpu_init, .zapfw =3D "a530_zap.mdt", + .speedbins =3D ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 2 }, + { 3, 3 }, + ), }, { .chip_ids =3D ADRENO_CHIP_IDS(0x05040001), .family =3D ADRENO_5XX, --=20 2.45.2 From nobody Thu Dec 18 20:24:59 2025 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4212E17C9FE for ; Tue, 25 Jun 2024 18:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340106; cv=none; b=G1jmkrfXlHw7v0WcBAhtCtZ9lQKItIkAJvKH43ztwl79xW0Z30GDLAzMKa2RKVUx5rOy2wPZZMatLVoUq1HGGAeAgyOq8ysrnfHu5SWmySFoBBoACg/knSx4995GiMYgK34KLZ63CGKX0lBv7od/SlrPRpn7UeskoXZ/Zt3qtTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719340106; c=relaxed/simple; bh=Ry862n+FpOLTGn5MkJgx2cTKUCkA2znjulWGMtUKONA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tyrYFikZboZ0Z1fyQNSI8Grkc69Y1DFgwKZGm5/eY+0G0HQ1h1pX8qAGo2KFIGbj914RjKpS3gGCVvUPgCjddtaT5Ja6oMnczwxdl5f642omRziDooLiuvx+pbC9qF0G/ZdXuoqIQOnCcTt+HuTTp6O5vCan2w7UNHObVqqpOvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=apww7SLt; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="apww7SLt" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-57cbc66a0a6so795646a12.1 for ; Tue, 25 Jun 2024 11:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1719340102; x=1719944902; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ICbp0JfVRMLkS3xURaXu0M0XpmVLimtiYC+UR97idFU=; b=apww7SLtmNdcXVoVmEilwtDUevykqIXkf5+WSnzu8TC/napcBrVoH7t0fxw23SRxsA 7Cj/HCWTZA5kxqdpHz0W84sxPcyduocgjHg9YS8uLCsggg6x188dnGlHqYQTXDuvOiFB gwCJDTtmSXT5TS+1HBidKOo7pmZwDuOenrOJJ6gvSYxV+v1OHE9mgCIicy8dtgWMocFp 2GFCdP9f6m8D3XrhmQWB1ohFwI2Qr9jCohz57xT53HQs2JNqfDmYMXJUHI8YEzb9FfCj iMVHJAWsXExaIv9hXlif9xRy0cXzbgLfc864tFddEEHRRQ3dtqEM/Mpn7KrCjsupzMZQ Ly0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719340102; x=1719944902; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICbp0JfVRMLkS3xURaXu0M0XpmVLimtiYC+UR97idFU=; b=SMbkg/Hex8byWpcGaqqnGvjHBgUndp+k8EvmDCEfNRpMqbDAoTJgwf7mX8Ajpascf7 4kZ3wL6cEW6EMtTLfTOjyWpt5DQfAoWNHS4xBmVoaD/KsR93TT3yrFw12hWSzuTve+aJ SCCtaSaXMftkXPY31vCDWl2fxTMcvYJ2Rse0Vp2f93u1D1Vj/3fLqgSz8S6J1ZRIvYVl cUKHl4YRn5DVJPJKBizyi/SsRpR8ZP6CqYtsRmFdpWaICCV27ceUDrw93k7YWoEO4iRT f5GqJ+3a1jig8OZBcVmo9Rw/WN3cQd0Kyxp7oHehCwjIme+bt9Dz8PwGctJ5fmlCWgpO LFpA== X-Forwarded-Encrypted: i=1; AJvYcCXzqce9FmP07Xqt/G25ZMEDuiL62VMb21WVdqJBmzBHiNae3QjIb6ZuPF4VAlMDCLdeVWn+unOp18MBuCWp/Rl7d57yPYcf16oZscko X-Gm-Message-State: AOJu0YxhWzcKrxwOa4TCL6On7HSMEKK77CZc0YagkhVFww/ZGNo6i94p 3xlrNBOjswQXIFtVwWmZmtIpZ9Cl+dH/w2j5IylXhgebr5a4i1jsDeEEw+UZFcg= X-Google-Smtp-Source: AGHT+IEup2qBc5JcOlhxwWSxCRUG0VZjYJJ5OJmMrT6P7/hUolkL818OjgSFrl9/U6AvA2SIUaakbw== X-Received: by 2002:a50:c004:0:b0:57c:b82e:884b with SMTP id 4fb4d7f45d1cf-57d70231a13mr2763887a12.19.1719340101898; Tue, 25 Jun 2024 11:28:21 -0700 (PDT) Received: from [192.168.215.29] (078088045245.garwolin.vectranet.pl. [78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:21 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:09 +0200 Subject: [PATCH v4 4/5] drm/msm/adreno: Redo the speedbin assignment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-4-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=7850; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Ry862n+FpOLTGn5MkJgx2cTKUCkA2znjulWGMtUKONA=; b=2LmKQAnmlokuLtndRqTr2Z3i2J0lqsGeDMaZsU18gChXDudlcRZx15ncjbOib6T6l7AtVtPZ1 TMErj+zPijiDgD+q/z7JuXbZCMBias3Xv48gCqRY7CtMehIxctR1B5S X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= There is no need to reinvent the wheel for simple read-match-set logic. Make speedbin discovery and assignment generation independent. This implicitly removes the bogus 0x80 / BIT(7) speed bin on A5xx, which has no representation in hardware whatshowever. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -------------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 -----------------------------= ---- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 51 ++++++++++++++++++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 -- 4 files changed, 45 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index c003f970189b..eed6a2eb1731 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1704,38 +1704,6 @@ static const struct adreno_gpu_funcs funcs =3D { .get_timestamp =3D a5xx_get_timestamp, }; =20 -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* - * If the OPP table specifies a opp-supported-hw property then we have - * to set something with dev_pm_opp_set_supported_hw() or the table - * doesn't get populated so pick an arbitrary value that should - * ensure the default frequencies are selected but not conflict with any - * actual bins - */ - val =3D 0x80; - - cell =3D nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf =3D nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin =3D *((u8 *) buf); - - val =3D (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - devm_pm_opp_set_supported_hw(dev, &val, 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv =3D dev->dev_private; @@ -1763,8 +1731,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) =20 a5xx_gpu->lm_leakage =3D 0x4E001A; =20 - check_speed_bin(&pdev->dev); - nr_rings =3D 4; =20 if (config->info->revn =3D=3D 510) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 8ace096bb68c..f038e5f1fe59 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2112,55 +2112,6 @@ static bool a6xx_progress(struct msm_gpu *gpu, struc= t msm_ringbuffer *ring) return progress; } =20 -static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) -{ - if (!info->speedbins) - return UINT_MAX; - - for (int i =3D 0; info->speedbins[i].fuse !=3D SHRT_MAX; i++) - if (info->speedbins[i].fuse =3D=3D fuse) - return BIT(info->speedbins[i].speedbin); - - return UINT_MAX; -} - -static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, - struct device *dev, - const struct adreno_info *info) -{ - u32 supp_hw; - u32 speedbin; - int ret; - - ret =3D adreno_read_speedbin(adreno_gpu, dev, &speedbin); - /* - * -ENOENT means that the platform doesn't support speedbin which is - * fine - */ - if (ret =3D=3D -ENOENT) { - return 0; - } else if (ret) { - dev_err_probe(dev, ret, - "failed to read speed-bin. Some OPPs may not be supported by hard= ware\n"); - return ret; - } - - supp_hw =3D fuse_to_supp_hw(info, speedbin); - - if (supp_hw =3D=3D UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by h= ardware\n", - speedbin); - supp_hw =3D BIT(0); /* Default */ - } - - ret =3D devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (ret) - return ret; - - return 0; -} - static const struct adreno_gpu_funcs funcs =3D { .base =3D { .get_param =3D adreno_get_param, @@ -2292,13 +2243,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 - ret =3D a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); - if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); - kfree(a6xx_gpu); - return ERR_PTR(ret); - } - if (is_a7xx) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); else if (adreno_has_gmu_wrapper(adreno_gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 6ffd02f38499..5b4205b76cdf 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1064,8 +1064,8 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ad= reno_ocmem) adreno_ocmem->hdl); } =20 -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *fuse) +static int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *fuse) { u32 fcode; int ret; @@ -1099,6 +1099,46 @@ int adreno_read_speedbin(struct adreno_gpu *adreno_g= pu, return 0; } =20 +#define ADRENO_SPEEDBIN_FUSE_NODATA 0xFFFF /* Made-up large value, expecte= d by mesa */ +static int adreno_set_speedbin(struct adreno_gpu *adreno_gpu, struct devic= e *dev) +{ + const struct adreno_info *info =3D adreno_gpu->info; + u32 fuse =3D ADRENO_SPEEDBIN_FUSE_NODATA; + u32 supp_hw =3D UINT_MAX; + int ret; + + /* No speedbins defined for this GPU SKU =3D> allow all defined OPPs */ + if (!info->speedbins) { + adreno_gpu->speedbin =3D ADRENO_SPEEDBIN_FUSE_NODATA; + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + /* + * If a real error (not counting older devicetrees having no nvmem refere= nces) + * occurs when trying to get the fuse value, bail out. + */ + ret =3D adreno_read_speedbin(adreno_gpu, dev, &fuse); + if (ret) { + return ret; + } else if (fuse =3D=3D ADRENO_SPEEDBIN_FUSE_NODATA) { + /* The info struct has speedbin data, but the DT is too old =3D> allow a= ll OPPs */ + DRM_DEV_INFO(dev, "No GPU speed bin fuse, please update your device tree= \n"); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + + adreno_gpu->speedbin =3D fuse; + + /* Traverse the known speedbins */ + for (int i =3D 0; info->speedbins[i].fuse !=3D SHRT_MAX; i++) { + if (info->speedbins[i].fuse =3D=3D fuse) { + supp_hw =3D BIT(info->speedbins[i].speedbin); + return devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + } + } + + return dev_err_probe(dev, -EINVAL, "Unknown speed bin fuse value: 0x%x\n"= , fuse); +} + int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs, int nr_rings) @@ -1108,7 +1148,6 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, struct msm_gpu_config adreno_gpu_config =3D { 0 }; struct msm_gpu *gpu =3D &adreno_gpu->base; const char *gpu_name; - u32 speedbin; int ret; =20 adreno_gpu->funcs =3D funcs; @@ -1135,9 +1174,9 @@ int adreno_gpu_init(struct drm_device *drm, struct pl= atform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } =20 - if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) - speedbin =3D 0xffff; - adreno_gpu->speedbin =3D speedbin; + ret =3D adreno_set_speedbin(adreno_gpu, dev); + if (ret) + return ret; =20 gpu_name =3D devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index 563c08b44624..dc579f7afdc7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -549,9 +549,6 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned = long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); =20 -int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, - struct device *dev, u32 *speedbin); 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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:23 -0700 (PDT) From: Konrad Dybcio Date: Tue, 25 Jun 2024 20:28:10 +0200 Subject: [PATCH v4 5/5] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240625-topic-smem_speedbin-v4-5-f6f8493ab814@linaro.org> References: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> In-Reply-To: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=2474; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Il2UvibnuII6pAMEt7ZcsOO48MoDeeFboVabC36fJtY=; b=BlXBbM1o+PokhijSw+a2fl1gngXBbq3ayq9OQmI+TCgtGvPpsbaOQBkdjIvAjvDF7aXjlDpJH esr8rfv+fDKDgRA+7vpMkcyhgkuyqJI/f62VXU0kMJnbmcR074FZ4FI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 4c9820adcf52..c1e3cec1540a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2119,48 +2119,67 @@ zap-shader { memory-region =3D <&gpu_micro_code_mem>; }; =20 - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 + opp-719000000 { + opp-hz =3D /bits/ 64 <719000000>; + opp-level =3D ; + opp-supported-hw =3D <0x1>; + }; + opp-680000000 { opp-hz =3D /bits/ 64 <680000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-615000000 { opp-hz =3D /bits/ 64 <615000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-550000000 { opp-hz =3D /bits/ 64 <550000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-475000000 { opp-hz =3D /bits/ 64 <475000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-401000000 { opp-hz =3D /bits/ 64 <401000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-348000000 { opp-hz =3D /bits/ 64 <348000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-295000000 { opp-hz =3D /bits/ 64 <295000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-220000000 { opp-hz =3D /bits/ 64 <220000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; + }; + + opp-124800000 { + opp-hz =3D /bits/ 64 <124800000>; + opp-level =3D ; + opp-supported-hw =3D <0x3>; }; }; }; --=20 2.45.2