From nobody Wed Dec 17 17:41:43 2025 Received: from mail-qv1-f41.google.com (mail-qv1-f41.google.com [209.85.219.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2195219DF6F for ; Mon, 24 Jun 2024 15:13:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719241995; cv=none; b=WCduuoC95MR//YFeF6h1AiMyyiVmf53tGhhXZRO4uR8bsHM4iIfkURe+Pe0K8ri0aBF8Uizy1BOSGtb4Q07U33vjzWVf8TOlSd/HGGACVC8YWexC6+JswIQ1oEjSIZmQ+gZsu+/In4BovkboM71ZXU3y+M/3513ozVECtnHD1MU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719241995; c=relaxed/simple; bh=EbvUhI6TnOt1pOp6/IX+Tt52ZjulXB3KrYG+OfhJmiI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XCoDfDghxXSVFo/HN/0QCY9OfPtHaZ65JKpbfZxJ14kDk62lnfiMFN/DQ0MAop5wgTUr6ew4qcVBg3S3slT7KDEXfazANIFPv3Kgac9Zuw2qGQqqvgMgGTrDnPodNaS6SzLODhEvGDGOaFsAVlrwSZJx1t00IZShzrthxFSZeJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VvWFLOcT; arc=none smtp.client-ip=209.85.219.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VvWFLOcT" Received: by mail-qv1-f41.google.com with SMTP id 6a1803df08f44-6b2c6291038so35115506d6.0 for ; Mon, 24 Jun 2024 08:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719241992; x=1719846792; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9nYYzlPy5SI7PVhpCb/BENiLzYELRokf+ehigNOLV50=; b=VvWFLOcTRYQOq17fCPnR14SHj8hJUEOSWhA93+6k/WE5VmxEHvGUZE2dJ07Ofp7kTB ItUOxkDH2GYZa6Te1q2FDAhIkHhc6CGv2R+lC5Esdfpf1rU1cKeoyKdv0DTrfYmGNYUy AZN7Yd0bOCQBhg8GxEAd+LnjhOxjoRSDPqp+iy5G5ruH0oP0CFIOI1HzhF2gF7SQML1C NStb2Qkxu5HeG+Td0VAjAyYIZ1iKaD+NICblgdWU5DpDZvE+m0KTRjcsiqlQQzSNMqZy 8xcaL0IqbCTqvwwt2ZSy0cjfXx3+wNzFuD8qrJ+V6kV9dVxQmCZcROc1NhM05m9sGQ1J VcQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719241992; x=1719846792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9nYYzlPy5SI7PVhpCb/BENiLzYELRokf+ehigNOLV50=; b=trSOyehKzB3yNCWSS4+Tj3xsSXaGOh8vA4ceF9nSpYNn7+Jc/P4S+EdzkWaeomDdqd kz8DqAGiURvVEFZEjilUCVVvJEB8xC3zWPrlKl/sq4tckL6PWV0zdnudLmemgOu3HYDc stb8DQROLewV+/oAbmvM013ams9zY1gvNne9QPblEZGXUxOwIenXd+84SX3Ra+xKrBf6 CbOBuS6jwFECWDS2/X2KkTK5bLeLrq6vuz1VVurRJs9Dbswhs4zn4RdGyf0OJlRPfNln CLO5Q3QLek1ERugy/5pDAp3G5U3Iqoa+1m8wCbklUWlCWrc/gJknbkW7Ue24Z8a4zLKN TWow== X-Forwarded-Encrypted: i=1; AJvYcCX67Q93kMPe1QRd+ZECbY1raXMtt0cAs+K4s7SJuO8zgWJSAb5ayTUA2lZofQW6iVeC0kMtRPr9EDv3dhFEY6J0l75nmhwQo5BtaKfO X-Gm-Message-State: AOJu0Yz+mmNourBXqpcw0Lejq2zx0KiJiUZj6eQEqfyC3EhkjFiZrLyf 4X2jowmhATmbPKs2B8J81FqH5vVDwoEYW36/SHn+T+e1GEnsFS8/ X-Google-Smtp-Source: AGHT+IEprwN5h8WZ1/wkonQOxrwmg5w7UCx+KUVlukokHQdSgRbfniLRd92MnIdCJU/0QhN19UEuEg== X-Received: by 2002:ad4:5f8a:0:b0:6b5:5687:8f7a with SMTP id 6a1803df08f44-6b55687df85mr31921576d6.21.1719241992057; Mon, 24 Jun 2024 08:13:12 -0700 (PDT) Received: from localhost.localdomain ([142.198.217.108]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6b529eb3decsm27243976d6.12.2024.06.24.08.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 08:13:10 -0700 (PDT) From: Wu Hoi Pok To: Cc: Thomas Zimmermann , Wu Hoi Pok , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/7] drm/radeon: rdev->ddev to rdev_to_drm(rdev) 4 Date: Mon, 24 Jun 2024 11:10:49 -0400 Message-ID: <20240624151122.23724-6-wuhoipok@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240624151122.23724-1-wuhoipok@gmail.com> References: <20240624151122.23724-1-wuhoipok@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Please refer to patch 1. Signed-off-by: Wu Hoi Pok --- drivers/gpu/drm/radeon/radeon_device.c | 19 +++---- drivers/gpu/drm/radeon/radeon_display.c | 74 ++++++++++++------------- drivers/gpu/drm/radeon/radeon_fbdev.c | 26 ++++----- drivers/gpu/drm/radeon/radeon_fence.c | 8 +-- drivers/gpu/drm/radeon/radeon_gem.c | 2 +- drivers/gpu/drm/radeon/radeon_i2c.c | 2 +- 6 files changed, 63 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeo= n/radeon_device.c index afbb3a80c0c6..127d8fd7f7cd 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -760,7 +760,7 @@ bool radeon_boot_test_post_card(struct radeon_device *r= dev) if (rdev->is_atom_bios) atom_asic_init(rdev->mode_info.atom_context); else - radeon_combios_asic_init(rdev->ddev); + radeon_combios_asic_init(rdev_to_drm(rdev)); return true; } else { dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); @@ -980,7 +980,7 @@ int radeon_atombios_init(struct radeon_device *rdev) return -ENOMEM; =20 rdev->mode_info.atom_card_info =3D atom_card_info; - atom_card_info->dev =3D rdev->ddev; + atom_card_info->dev =3D rdev_to_drm(rdev); atom_card_info->reg_read =3D cail_reg_read; atom_card_info->reg_write =3D cail_reg_write; /* needed for iio ops */ @@ -1005,7 +1005,7 @@ int radeon_atombios_init(struct radeon_device *rdev) =20 mutex_init(&rdev->mode_info.atom_context->mutex); mutex_init(&rdev->mode_info.atom_context->scratch_mutex); - radeon_atom_initialize_bios_scratch_regs(rdev->ddev); + radeon_atom_initialize_bios_scratch_regs(rdev_to_drm(rdev)); atom_allocate_fb_scratch(rdev->mode_info.atom_context); return 0; } @@ -1049,7 +1049,7 @@ void radeon_atombios_fini(struct radeon_device *rdev) */ int radeon_combios_init(struct radeon_device *rdev) { - radeon_combios_initialize_bios_scratch_regs(rdev->ddev); + radeon_combios_initialize_bios_scratch_regs(rdev_to_drm(rdev)); return 0; } =20 @@ -1267,8 +1267,6 @@ static const struct vga_switcheroo_client_ops radeon_= switcheroo_ops =3D { * radeon_device_init - initialize the driver * * @rdev: radeon_device pointer - * @ddev: drm dev pointer - * @pdev: pci dev pointer * @flags: driver flags * * Initializes the driver info and hw (all asics). @@ -1276,18 +1274,15 @@ static const struct vga_switcheroo_client_ops radeo= n_switcheroo_ops =3D { * Called at driver startup. */ int radeon_device_init(struct radeon_device *rdev, - struct drm_device *ddev, - struct pci_dev *pdev, uint32_t flags) { + struct pci_dev *pdev =3D rdev->pdev; + struct drm_device *ddev =3D rdev_to_drm(rdev); int r, i; int dma_bits; bool runtime =3D false; =20 rdev->shutdown =3D false; - rdev->dev =3D &pdev->dev; - rdev->ddev =3D ddev; - rdev->pdev =3D pdev; rdev->flags =3D flags; rdev->family =3D flags & RADEON_FAMILY_MASK; rdev->is_atom_bios =3D false; @@ -1847,7 +1842,7 @@ int radeon_gpu_reset(struct radeon_device *rdev) =20 downgrade_write(&rdev->exclusive_lock); =20 - drm_helper_resume_force_mode(rdev->ddev); + drm_helper_resume_force_mode(rdev_to_drm(rdev)); =20 /* set the power state here in case we are a PX system or headless */ if ((rdev->pm.pm_method =3D=3D PM_METHOD_DPM) && rdev->pm.dpm_enabled) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/rade= on/radeon_display.c index 843383f7237f..10fd58f400bc 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -302,13 +302,13 @@ void radeon_crtc_handle_vblank(struct radeon_device *= rdev, int crtc_id) if ((radeon_use_pflipirq =3D=3D 2) && ASIC_IS_DCE4(rdev)) return; =20 - spin_lock_irqsave(&rdev->ddev->event_lock, flags); + spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); if (radeon_crtc->flip_status !=3D RADEON_FLIP_SUBMITTED) { DRM_DEBUG_DRIVER("radeon_crtc->flip_status =3D %d !=3D " "RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED); - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); return; } =20 @@ -334,7 +334,7 @@ void radeon_crtc_handle_vblank(struct radeon_device *rd= ev, int crtc_id) */ if (update_pending && (DRM_SCANOUTPOS_VALID & - radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, + radeon_get_crtc_scanoutpos(rdev_to_drm(rdev), crtc_id, GET_DISTANCE_TO_VBLANKSTART, &vpos, &hpos, NULL, NULL, &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && @@ -347,7 +347,7 @@ void radeon_crtc_handle_vblank(struct radeon_device *rd= ev, int crtc_id) */ update_pending =3D 0; } - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); if (!update_pending) radeon_crtc_handle_flip(rdev, crtc_id); } @@ -370,14 +370,14 @@ void radeon_crtc_handle_flip(struct radeon_device *rd= ev, int crtc_id) if (radeon_crtc =3D=3D NULL) return; =20 - spin_lock_irqsave(&rdev->ddev->event_lock, flags); + spin_lock_irqsave(&rdev_to_drm(rdev)->event_lock, flags); work =3D radeon_crtc->flip_work; if (radeon_crtc->flip_status !=3D RADEON_FLIP_SUBMITTED) { DRM_DEBUG_DRIVER("radeon_crtc->flip_status =3D %d !=3D " "RADEON_FLIP_SUBMITTED(%d)\n", radeon_crtc->flip_status, RADEON_FLIP_SUBMITTED); - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); return; } =20 @@ -389,7 +389,7 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev= , int crtc_id) if (work->event) drm_crtc_send_vblank_event(&radeon_crtc->base, work->event); =20 - spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); + spin_unlock_irqrestore(&rdev_to_drm(rdev)->event_lock, flags); =20 drm_crtc_vblank_put(&radeon_crtc->base); radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id); @@ -408,7 +408,7 @@ static void radeon_flip_work_func(struct work_struct *_= _work) struct radeon_flip_work *work =3D container_of(__work, struct radeon_flip_work, flip_work); struct radeon_device *rdev =3D work->rdev; - struct drm_device *dev =3D rdev->ddev; + struct drm_device *dev =3D rdev_to_drm(rdev); struct radeon_crtc *radeon_crtc =3D rdev->mode_info.crtcs[work->crtc_id]; =20 struct drm_crtc *crtc =3D &radeon_crtc->base; @@ -1401,7 +1401,7 @@ static int radeon_modeset_create_props(struct radeon_= device *rdev) =20 if (rdev->is_atom_bios) { rdev->mode_info.coherent_mode_property =3D - drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); + drm_property_create_range(rdev_to_drm(rdev), 0, "coherent", 0, 1); if (!rdev->mode_info.coherent_mode_property) return -ENOMEM; } @@ -1409,57 +1409,57 @@ static int radeon_modeset_create_props(struct radeo= n_device *rdev) if (!ASIC_IS_AVIVO(rdev)) { sz =3D ARRAY_SIZE(radeon_tmds_pll_enum_list); rdev->mode_info.tmds_pll_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "tmds_pll", radeon_tmds_pll_enum_list, sz); } =20 rdev->mode_info.load_detect_property =3D - drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); + drm_property_create_range(rdev_to_drm(rdev), 0, "load detection", 0, 1); if (!rdev->mode_info.load_detect_property) return -ENOMEM; =20 - drm_mode_create_scaling_mode_property(rdev->ddev); + drm_mode_create_scaling_mode_property(rdev_to_drm(rdev)); =20 sz =3D ARRAY_SIZE(radeon_tv_std_enum_list); rdev->mode_info.tv_std_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "tv standard", radeon_tv_std_enum_list, sz); =20 sz =3D ARRAY_SIZE(radeon_underscan_enum_list); rdev->mode_info.underscan_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "underscan", radeon_underscan_enum_list, sz); =20 rdev->mode_info.underscan_hborder_property =3D - drm_property_create_range(rdev->ddev, 0, + drm_property_create_range(rdev_to_drm(rdev), 0, "underscan hborder", 0, 128); if (!rdev->mode_info.underscan_hborder_property) return -ENOMEM; =20 rdev->mode_info.underscan_vborder_property =3D - drm_property_create_range(rdev->ddev, 0, + drm_property_create_range(rdev_to_drm(rdev), 0, "underscan vborder", 0, 128); if (!rdev->mode_info.underscan_vborder_property) return -ENOMEM; =20 sz =3D ARRAY_SIZE(radeon_audio_enum_list); rdev->mode_info.audio_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "audio", radeon_audio_enum_list, sz); =20 sz =3D ARRAY_SIZE(radeon_dither_enum_list); rdev->mode_info.dither_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "dither", radeon_dither_enum_list, sz); =20 sz =3D ARRAY_SIZE(radeon_output_csc_enum_list); rdev->mode_info.output_csc_property =3D - drm_property_create_enum(rdev->ddev, 0, + drm_property_create_enum(rdev_to_drm(rdev), 0, "output_csc", radeon_output_csc_enum_list, sz); =20 @@ -1578,29 +1578,29 @@ int radeon_modeset_init(struct radeon_device *rdev) int i; int ret; =20 - drm_mode_config_init(rdev->ddev); + drm_mode_config_init(rdev_to_drm(rdev)); rdev->mode_info.mode_config_initialized =3D true; =20 - rdev->ddev->mode_config.funcs =3D &radeon_mode_funcs; + rdev_to_drm(rdev)->mode_config.funcs =3D &radeon_mode_funcs; =20 if (radeon_use_pflipirq =3D=3D 2 && rdev->family >=3D CHIP_R600) - rdev->ddev->mode_config.async_page_flip =3D true; + rdev_to_drm(rdev)->mode_config.async_page_flip =3D true; =20 if (ASIC_IS_DCE5(rdev)) { - rdev->ddev->mode_config.max_width =3D 16384; - rdev->ddev->mode_config.max_height =3D 16384; + rdev_to_drm(rdev)->mode_config.max_width =3D 16384; + rdev_to_drm(rdev)->mode_config.max_height =3D 16384; } else if (ASIC_IS_AVIVO(rdev)) { - rdev->ddev->mode_config.max_width =3D 8192; - rdev->ddev->mode_config.max_height =3D 8192; + rdev_to_drm(rdev)->mode_config.max_width =3D 8192; + rdev_to_drm(rdev)->mode_config.max_height =3D 8192; } else { - rdev->ddev->mode_config.max_width =3D 4096; - rdev->ddev->mode_config.max_height =3D 4096; + rdev_to_drm(rdev)->mode_config.max_width =3D 4096; + rdev_to_drm(rdev)->mode_config.max_height =3D 4096; } =20 - rdev->ddev->mode_config.preferred_depth =3D 24; - rdev->ddev->mode_config.prefer_shadow =3D 1; + rdev_to_drm(rdev)->mode_config.preferred_depth =3D 24; + rdev_to_drm(rdev)->mode_config.prefer_shadow =3D 1; =20 - rdev->ddev->mode_config.fb_modifiers_not_supported =3D true; + rdev_to_drm(rdev)->mode_config.fb_modifiers_not_supported =3D true; =20 ret =3D radeon_modeset_create_props(rdev); if (ret) { @@ -1618,11 +1618,11 @@ int radeon_modeset_init(struct radeon_device *rdev) =20 /* allocate crtcs */ for (i =3D 0; i < rdev->num_crtc; i++) { - radeon_crtc_init(rdev->ddev, i); + radeon_crtc_init(rdev_to_drm(rdev), i); } =20 /* okay we should have all the bios connectors */ - ret =3D radeon_setup_enc_conn(rdev->ddev); + ret =3D radeon_setup_enc_conn(rdev_to_drm(rdev)); if (!ret) { return ret; } @@ -1639,7 +1639,7 @@ int radeon_modeset_init(struct radeon_device *rdev) /* setup afmt */ radeon_afmt_init(rdev); =20 - drm_kms_helper_poll_init(rdev->ddev); + drm_kms_helper_poll_init(rdev_to_drm(rdev)); =20 /* do pm late init */ ret =3D radeon_pm_late_init(rdev); @@ -1650,11 +1650,11 @@ int radeon_modeset_init(struct radeon_device *rdev) void radeon_modeset_fini(struct radeon_device *rdev) { if (rdev->mode_info.mode_config_initialized) { - drm_kms_helper_poll_fini(rdev->ddev); + drm_kms_helper_poll_fini(rdev_to_drm(rdev)); radeon_hpd_fini(rdev); - drm_helper_force_disable_all(rdev->ddev); + drm_helper_force_disable_all(rdev_to_drm(rdev)); radeon_afmt_fini(rdev); - drm_mode_config_cleanup(rdev->ddev); + drm_mode_config_cleanup(rdev_to_drm(rdev)); rdev->mode_info.mode_config_initialized =3D false; } =20 diff --git a/drivers/gpu/drm/radeon/radeon_fbdev.c b/drivers/gpu/drm/radeon= /radeon_fbdev.c index 02bf25759059..fb70de29545c 100644 --- a/drivers/gpu/drm/radeon/radeon_fbdev.c +++ b/drivers/gpu/drm/radeon/radeon_fbdev.c @@ -67,7 +67,7 @@ static int radeon_fbdev_create_pinned_object(struct drm_f= b_helper *fb_helper, int height =3D mode_cmd->height; u32 cpp; =20 - info =3D drm_get_format_info(rdev->ddev, mode_cmd); + info =3D drm_get_format_info(rdev_to_drm(rdev), mode_cmd); cpp =3D info->cpp[0]; =20 /* need to align pitch with crtc limits */ @@ -148,15 +148,15 @@ static int radeon_fbdev_fb_open(struct fb_info *info,= int user) struct radeon_device *rdev =3D fb_helper->dev->dev_private; int ret; =20 - ret =3D pm_runtime_get_sync(rdev->ddev->dev); + ret =3D pm_runtime_get_sync(rdev_to_drm(rdev)->dev); if (ret < 0 && ret !=3D -EACCES) goto err_pm_runtime_mark_last_busy; =20 return 0; =20 err_pm_runtime_mark_last_busy: - pm_runtime_mark_last_busy(rdev->ddev->dev); - pm_runtime_put_autosuspend(rdev->ddev->dev); + pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); + pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); return ret; } =20 @@ -165,8 +165,8 @@ static int radeon_fbdev_fb_release(struct fb_info *info= , int user) struct drm_fb_helper *fb_helper =3D info->par; struct radeon_device *rdev =3D fb_helper->dev->dev_private; =20 - pm_runtime_mark_last_busy(rdev->ddev->dev); - pm_runtime_put_autosuspend(rdev->ddev->dev); + pm_runtime_mark_last_busy(rdev_to_drm(rdev)->dev); + pm_runtime_put_autosuspend(rdev_to_drm(rdev)->dev); =20 return 0; } @@ -236,7 +236,7 @@ static int radeon_fbdev_fb_helper_fb_probe(struct drm_f= b_helper *fb_helper, ret =3D -ENOMEM; goto err_radeon_fbdev_destroy_pinned_object; } - ret =3D radeon_framebuffer_init(rdev->ddev, fb, &mode_cmd, gobj); + ret =3D radeon_framebuffer_init(rdev_to_drm(rdev), fb, &mode_cmd, gobj); if (ret) { DRM_ERROR("failed to initialize framebuffer %d\n", ret); goto err_kfree; @@ -374,12 +374,12 @@ void radeon_fbdev_setup(struct radeon_device *rdev) fb_helper =3D kzalloc(sizeof(*fb_helper), GFP_KERNEL); if (!fb_helper) return; - drm_fb_helper_prepare(rdev->ddev, fb_helper, bpp_sel, &radeon_fbdev_fb_he= lper_funcs); + drm_fb_helper_prepare(rdev_to_drm(rdev), fb_helper, bpp_sel, &radeon_fbde= v_fb_helper_funcs); =20 - ret =3D drm_client_init(rdev->ddev, &fb_helper->client, "radeon-fbdev", + ret =3D drm_client_init(rdev_to_drm(rdev), &fb_helper->client, "radeon-fb= dev", &radeon_fbdev_client_funcs); if (ret) { - drm_err(rdev->ddev, "Failed to register client: %d\n", ret); + drm_err(rdev_to_drm(rdev), "Failed to register client: %d\n", ret); goto err_drm_client_init; } =20 @@ -394,13 +394,13 @@ void radeon_fbdev_setup(struct radeon_device *rdev) =20 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) { - if (rdev->ddev->fb_helper) - drm_fb_helper_set_suspend(rdev->ddev->fb_helper, state); + if (rdev_to_drm(rdev)->fb_helper) + drm_fb_helper_set_suspend(rdev_to_drm(rdev)->fb_helper, state); } =20 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo = *robj) { - struct drm_fb_helper *fb_helper =3D rdev->ddev->fb_helper; + struct drm_fb_helper *fb_helper =3D rdev_to_drm(rdev)->fb_helper; struct drm_gem_object *gobj; =20 if (!fb_helper) diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon= /radeon_fence.c index 4fb780d96f32..daff61586be5 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -150,7 +150,7 @@ int radeon_fence_emit(struct radeon_device *rdev, rdev->fence_context + ring, seq); radeon_fence_ring_emit(rdev, ring, *fence); - trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq); + trace_radeon_fence_emit(rdev_to_drm(rdev), ring, (*fence)->seq); radeon_fence_schedule_check(rdev, ring); return 0; } @@ -489,7 +489,7 @@ static long radeon_fence_wait_seq_timeout(struct radeon= _device *rdev, if (!target_seq[i]) continue; =20 - trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]); + trace_radeon_fence_wait_begin(rdev_to_drm(rdev), i, target_seq[i]); radeon_irq_kms_sw_irq_get(rdev, i); } =20 @@ -511,7 +511,7 @@ static long radeon_fence_wait_seq_timeout(struct radeon= _device *rdev, continue; =20 radeon_irq_kms_sw_irq_put(rdev, i); - trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]); + trace_radeon_fence_wait_end(rdev_to_drm(rdev), i, target_seq[i]); } =20 return r; @@ -995,7 +995,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(radeon_debugfs_gpu_reset_fops, void radeon_debugfs_fence_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) - struct dentry *root =3D rdev->ddev->primary->debugfs_root; + struct dentry *root =3D rdev_to_drm(rdev)->primary->debugfs_root; =20 debugfs_create_file("radeon_gpu_reset", 0444, root, rdev, &radeon_debugfs_gpu_reset_fops); diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/r= adeon_gem.c index 2ef201a072f1..9dd4ff09d562 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -899,7 +899,7 @@ DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_gem_info); void radeon_gem_debugfs_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) - struct dentry *root =3D rdev->ddev->primary->debugfs_root; + struct dentry *root =3D rdev_to_drm(rdev)->primary->debugfs_root; =20 debugfs_create_file("radeon_gem_info", 0444, root, rdev, &radeon_debugfs_gem_info_fops); diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/r= adeon_i2c.c index 3d174390a8af..1f16619ed06e 100644 --- a/drivers/gpu/drm/radeon/radeon_i2c.c +++ b/drivers/gpu/drm/radeon/radeon_i2c.c @@ -1011,7 +1011,7 @@ void radeon_i2c_add(struct radeon_device *rdev, struct radeon_i2c_bus_rec *rec, const char *name) { - struct drm_device *dev =3D rdev->ddev; + struct drm_device *dev =3D rdev_to_drm(rdev); int i; =20 for (i =3D 0; i < RADEON_MAX_I2C_BUS; i++) { --=20 2.45.2