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charset="utf-8" Currently, the init_code of the jd9365da driver is placed in the enable() function and sent, but this seems to take a long time. It takes 17ms to send each instruction (an init code consists of about 200 instructions), so it takes about 3.5s to send the init_code. So we moved the sending of the inti_code to the prepare() function, and each instruction seemed to take only 25\ufffd\ufffds. We checked the DSI host and found that the difference in command sending time is caused by the different modes of the DSI host in prepare() and enable() functions. Our DSI Host only supports sending cmd in LP mode, The prepare() function can directly send init_code (LP->cmd) in LP mode, but the enable() function is in HS mode and needs to switch to LP mode before sending init code (HS->LP->cmd->HS). Therefore, it takes longer to send the command. Signed-off-by: Zhaoxiong Lv Reviewed-by: Douglas Anderson Reviewed-by: Neil Armstrong --- Changes between V5 and V4: - 1. No changes. V4:https://lore.kernel.org/all/20240620080509.18504-2-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V4 and V3: - 1. Only move mipi_dsi_dcs_write_buffer from enable() function to prepare(= ) function, - and no longer use mipi_dsi_dcs_write_seq_multi. V3:https://lore.kernel.org/all/20240614145510.22965-2-lvzhaoxiong@huaqin.co= rp-partner.google.com/ --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index 4879835fe101..a9c483a7b3fa 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -52,21 +52,9 @@ static int jadard_enable(struct drm_panel *panel) { struct device *dev =3D panel->dev; struct jadard *jadard =3D panel_to_jadard(panel); - const struct jadard_panel_desc *desc =3D jadard->desc; struct mipi_dsi_device *dsi =3D jadard->dsi; - unsigned int i; int err; =20 - msleep(10); - - for (i =3D 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd =3D &desc->init_cmds[i]; - - err =3D mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (err < 0) - return err; - } - msleep(120); =20 err =3D mipi_dsi_dcs_exit_sleep_mode(dsi); @@ -100,6 +88,8 @@ static int jadard_disable(struct drm_panel *panel) static int jadard_prepare(struct drm_panel *panel) { struct jadard *jadard =3D panel_to_jadard(panel); + const struct jadard_panel_desc *desc =3D jadard->desc; + unsigned int i; int ret; =20 ret =3D regulator_enable(jadard->vccio); @@ -117,7 +107,15 @@ static int jadard_prepare(struct drm_panel *panel) msleep(10); =20 gpiod_set_value(jadard->reset, 1); - msleep(120); + msleep(130); + + for (i =3D 0; i < desc->num_init_cmds; i++) { + const struct jadard_init_cmd *cmd =3D &desc->init_cmds[i]; + + ret =3D mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); + if (ret < 0) + return ret; + } =20 return 0; } --=20 2.17.1 From nobody Wed Dec 17 15:57:33 2025 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2BFB16F90F for ; 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Mon, 24 Jun 2024 07:20:46 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb3d5fa9sm63243855ad.206.2024.06.24.07.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:20:46 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 2/5] dt-bindings: display: panel: Add compatible for kingdisplay-kd101ne3 Date: Mon, 24 Jun 2024 22:19:23 +0800 Message-Id: <20240624141926.5250-3-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The kingdisplay-kd101ne3 is a 10.1" WXGA TFT-LCD panel with jadard-jd9365da controller. Hence, we add a new compatible with panel specific config. Signed-off-by: Zhaoxiong Lv Acked-by: Conor Dooley --- Changes between V5 and V4: - 1. No changes. V4:https://lore.kernel.org/all/20240620080509.18504-3-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V4 and V3: - 1. Move positions to keep the list sorted. V3:https://lore.kernel.org/all/20240614145510.22965-3-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V3 and V2: - 1. Abandon the V2 patch and add kingdisplay kd101ne3-40ti binding to=20 - jadard,jd9365da-h3.yaml again. V2:https://lore.kernel.org/all/20240601084528.22502-2-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V2 and V1: - Drop some properties that have already been defined in panel-common. - The header file 'dt-bindings/gpio/gpio.h' is not used, delete it V1: https://lore.kernel.org/all/20240418081548.12160-2-lvzhaoxiong@huaqin.c= orp-partner.google.com/ --- .../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365d= a-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da= -h3.yaml index 41eb7fbf7715..2b977292dc48 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.ya= ml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.ya= ml @@ -17,6 +17,7 @@ properties: items: - enum: - chongzhou,cz101b4001 + - kingdisplay,kd101ne3-40ti - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 - const: jadard,jd9365da-h3 --=20 2.17.1 From nobody Wed Dec 17 15:57:33 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F23417D882 for ; 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Mon, 24 Jun 2024 07:21:00 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb3d5fa9sm63243855ad.206.2024.06.24.07.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:20:59 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 3/5] drm/panel: panel-jadard-jd9365da-h3: use wrapped MIPI DCS functions Date: Mon, 24 Jun 2024 22:19:24 +0800 Message-Id: <20240624141926.5250-4-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove conditional code and always use mipi_dsi_dcs_*multi() wrappers to simplify driver's init/enable/exit code. Signed-off-by: Zhaoxiong Lv Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Reviewed-by: Jessica Zhang --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 793 +++++++++--------- 1 file changed, 390 insertions(+), 403 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index a9c483a7b3fa..e836260338bf 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -19,17 +19,13 @@ #include #include =20 -#define JD9365DA_INIT_CMD_LEN 2 - -struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; -}; +struct jadard; =20 struct jadard_panel_desc { const struct drm_display_mode mode; unsigned int lanes; enum mipi_dsi_pixel_format format; - const struct jadard_init_cmd *init_cmds; + int (*init)(struct jadard *jadard); u32 num_init_cmds; }; =20 @@ -50,46 +46,33 @@ static inline struct jadard *panel_to_jadard(struct drm= _panel *panel) =20 static int jadard_enable(struct drm_panel *panel) { - struct device *dev =3D panel->dev; struct jadard *jadard =3D panel_to_jadard(panel); - struct mipi_dsi_device *dsi =3D jadard->dsi; - int err; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; =20 msleep(120); =20 - err =3D mipi_dsi_dcs_exit_sleep_mode(dsi); - if (err < 0) - DRM_DEV_ERROR(dev, "failed to exit sleep mode ret =3D %d\n", err); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); =20 - err =3D mipi_dsi_dcs_set_display_on(dsi); - if (err < 0) - DRM_DEV_ERROR(dev, "failed to set display on ret =3D %d\n", err); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); =20 - return 0; + return dsi_ctx.accum_err; } =20 static int jadard_disable(struct drm_panel *panel) { - struct device *dev =3D panel->dev; struct jadard *jadard =3D panel_to_jadard(panel); - int ret; + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; =20 - ret =3D mipi_dsi_dcs_set_display_off(jadard->dsi); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to set display off: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); =20 - ret =3D mipi_dsi_dcs_enter_sleep_mode(jadard->dsi); - if (ret < 0) - DRM_DEV_ERROR(dev, "failed to enter sleep mode: %d\n", ret); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); =20 - return 0; + return dsi_ctx.accum_err; } =20 static int jadard_prepare(struct drm_panel *panel) { struct jadard *jadard =3D panel_to_jadard(panel); - const struct jadard_panel_desc *desc =3D jadard->desc; - unsigned int i; int ret; =20 ret =3D regulator_enable(jadard->vccio); @@ -109,13 +92,9 @@ static int jadard_prepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(130); =20 - for (i =3D 0; i < desc->num_init_cmds; i++) { - const struct jadard_init_cmd *cmd =3D &desc->init_cmds[i]; - - ret =3D mipi_dsi_dcs_write_buffer(dsi, cmd->data, JD9365DA_INIT_CMD_LEN); - if (ret < 0) - return ret; - } + ret =3D jadard->desc->init(jadard); + if (ret) + return ret; =20 return 0; } @@ -165,176 +144,181 @@ static const struct drm_panel_funcs jadard_funcs = =3D { .get_modes =3D jadard_get_modes, }; =20 -static const struct jadard_init_cmd radxa_display_8hd_ad002_init_cmds[] = =3D { - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE1, 0x93 } }, - { .data =3D { 0xE2, 0x65 } }, - { .data =3D { 0xE3, 0xF8 } }, - { .data =3D { 0x80, 0x03 } }, - { .data =3D { 0xE0, 0x01 } }, - { .data =3D { 0x00, 0x00 } }, - { .data =3D { 0x01, 0x7E } }, - { .data =3D { 0x03, 0x00 } }, - { .data =3D { 0x04, 0x65 } }, - { .data =3D { 0x0C, 0x74 } }, - { .data =3D { 0x17, 0x00 } }, - { .data =3D { 0x18, 0xB7 } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x00 } }, - { .data =3D { 0x1B, 0xB7 } }, - { .data =3D { 0x1C, 0x00 } }, - { .data =3D { 0x24, 0xFE } }, - { .data =3D { 0x37, 0x19 } }, - { .data =3D { 0x38, 0x05 } }, - { .data =3D { 0x39, 0x00 } }, - { .data =3D { 0x3A, 0x01 } }, - { .data =3D { 0x3B, 0x01 } }, - { .data =3D { 0x3C, 0x70 } }, - { .data =3D { 0x3D, 0xFF } }, - { .data =3D { 0x3E, 0xFF } }, - { .data =3D { 0x3F, 0xFF } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0xA0 } }, - { .data =3D { 0x43, 0x1E } }, - { .data =3D { 0x44, 0x0F } }, - { .data =3D { 0x45, 0x28 } }, - { .data =3D { 0x4B, 0x04 } }, - { .data =3D { 0x55, 0x02 } }, - { .data =3D { 0x56, 0x01 } }, - { .data =3D { 0x57, 0xA9 } }, - { .data =3D { 0x58, 0x0A } }, - { .data =3D { 0x59, 0x0A } }, - { .data =3D { 0x5A, 0x37 } }, - { .data =3D { 0x5B, 0x19 } }, - { .data =3D { 0x5D, 0x78 } }, - { .data =3D { 0x5E, 0x63 } }, - { .data =3D { 0x5F, 0x54 } }, - { .data =3D { 0x60, 0x49 } }, - { .data =3D { 0x61, 0x45 } }, - { .data =3D { 0x62, 0x38 } }, - { .data =3D { 0x63, 0x3D } }, - { .data =3D { 0x64, 0x28 } }, - { .data =3D { 0x65, 0x43 } }, - { .data =3D { 0x66, 0x41 } }, - { .data =3D { 0x67, 0x43 } }, - { .data =3D { 0x68, 0x62 } }, - { .data =3D { 0x69, 0x50 } }, - { .data =3D { 0x6A, 0x57 } }, - { .data =3D { 0x6B, 0x49 } }, - { .data =3D { 0x6C, 0x44 } }, - { .data =3D { 0x6D, 0x37 } }, - { .data =3D { 0x6E, 0x23 } }, - { .data =3D { 0x6F, 0x10 } }, - { .data =3D { 0x70, 0x78 } }, - { .data =3D { 0x71, 0x63 } }, - { .data =3D { 0x72, 0x54 } }, - { .data =3D { 0x73, 0x49 } }, - { .data =3D { 0x74, 0x45 } }, - { .data =3D { 0x75, 0x38 } }, - { .data =3D { 0x76, 0x3D } }, - { .data =3D { 0x77, 0x28 } }, - { .data =3D { 0x78, 0x43 } }, - { .data =3D { 0x79, 0x41 } }, - { .data =3D { 0x7A, 0x43 } }, - { .data =3D { 0x7B, 0x62 } }, - { .data =3D { 0x7C, 0x50 } }, - { .data =3D { 0x7D, 0x57 } }, - { .data =3D { 0x7E, 0x49 } }, - { .data =3D { 0x7F, 0x44 } }, - { .data =3D { 0x80, 0x37 } }, - { .data =3D { 0x81, 0x23 } }, - { .data =3D { 0x82, 0x10 } }, - { .data =3D { 0xE0, 0x02 } }, - { .data =3D { 0x00, 0x47 } }, - { .data =3D { 0x01, 0x47 } }, - { .data =3D { 0x02, 0x45 } }, - { .data =3D { 0x03, 0x45 } }, - { .data =3D { 0x04, 0x4B } }, - { .data =3D { 0x05, 0x4B } }, - { .data =3D { 0x06, 0x49 } }, - { .data =3D { 0x07, 0x49 } }, - { .data =3D { 0x08, 0x41 } }, - { .data =3D { 0x09, 0x1F } }, - { .data =3D { 0x0A, 0x1F } }, - { .data =3D { 0x0B, 0x1F } }, - { .data =3D { 0x0C, 0x1F } }, - { .data =3D { 0x0D, 0x1F } }, - { .data =3D { 0x0E, 0x1F } }, - { .data =3D { 0x0F, 0x5F } }, - { .data =3D { 0x10, 0x5F } }, - { .data =3D { 0x11, 0x57 } }, - { .data =3D { 0x12, 0x77 } }, - { .data =3D { 0x13, 0x35 } }, - { .data =3D { 0x14, 0x1F } }, - { .data =3D { 0x15, 0x1F } }, - { .data =3D { 0x16, 0x46 } }, - { .data =3D { 0x17, 0x46 } }, - { .data =3D { 0x18, 0x44 } }, - { .data =3D { 0x19, 0x44 } }, - { .data =3D { 0x1A, 0x4A } }, - { .data =3D { 0x1B, 0x4A } }, - { .data =3D { 0x1C, 0x48 } }, - { .data =3D { 0x1D, 0x48 } }, - { .data =3D { 0x1E, 0x40 } }, - { .data =3D { 0x1F, 0x1F } }, - { .data =3D { 0x20, 0x1F } }, - { .data =3D { 0x21, 0x1F } }, - { .data =3D { 0x22, 0x1F } }, - { .data =3D { 0x23, 0x1F } }, - { .data =3D { 0x24, 0x1F } }, - { .data =3D { 0x25, 0x5F } }, - { .data =3D { 0x26, 0x5F } }, - { .data =3D { 0x27, 0x57 } }, - { .data =3D { 0x28, 0x77 } }, - { .data =3D { 0x29, 0x35 } }, - { .data =3D { 0x2A, 0x1F } }, - { .data =3D { 0x2B, 0x1F } }, - { .data =3D { 0x58, 0x40 } }, - { .data =3D { 0x59, 0x00 } }, - { .data =3D { 0x5A, 0x00 } }, - { .data =3D { 0x5B, 0x10 } }, - { .data =3D { 0x5C, 0x06 } }, - { .data =3D { 0x5D, 0x40 } }, - { .data =3D { 0x5E, 0x01 } }, - { .data =3D { 0x5F, 0x02 } }, - { .data =3D { 0x60, 0x30 } }, - { .data =3D { 0x61, 0x01 } }, - { .data =3D { 0x62, 0x02 } }, - { .data =3D { 0x63, 0x03 } }, - { .data =3D { 0x64, 0x6B } }, - { .data =3D { 0x65, 0x05 } }, - { .data =3D { 0x66, 0x0C } }, - { .data =3D { 0x67, 0x73 } }, - { .data =3D { 0x68, 0x09 } }, - { .data =3D { 0x69, 0x03 } }, - { .data =3D { 0x6A, 0x56 } }, - { .data =3D { 0x6B, 0x08 } }, - { .data =3D { 0x6C, 0x00 } }, - { .data =3D { 0x6D, 0x04 } }, - { .data =3D { 0x6E, 0x04 } }, - { .data =3D { 0x6F, 0x88 } }, - { .data =3D { 0x70, 0x00 } }, - { .data =3D { 0x71, 0x00 } }, - { .data =3D { 0x72, 0x06 } }, - { .data =3D { 0x73, 0x7B } }, - { .data =3D { 0x74, 0x00 } }, - { .data =3D { 0x75, 0xF8 } }, - { .data =3D { 0x76, 0x00 } }, - { .data =3D { 0x77, 0xD5 } }, - { .data =3D { 0x78, 0x2E } }, - { .data =3D { 0x79, 0x12 } }, - { .data =3D { 0x7A, 0x03 } }, - { .data =3D { 0x7B, 0x00 } }, - { .data =3D { 0x7C, 0x00 } }, - { .data =3D { 0x7D, 0x03 } }, - { .data =3D { 0x7E, 0x7B } }, - { .data =3D { 0xE0, 0x04 } }, - { .data =3D { 0x00, 0x0E } }, - { .data =3D { 0x02, 0xB3 } }, - { .data =3D { 0x09, 0x60 } }, - { .data =3D { 0x0E, 0x2A } }, - { .data =3D { 0x36, 0x59 } }, - { .data =3D { 0xE0, 0x00 } }, +static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + + return dsi_ctx.accum_err; }; =20 static const struct jadard_panel_desc radxa_display_8hd_ad002_desc =3D { @@ -357,205 +341,209 @@ static const struct jadard_panel_desc radxa_display= _8hd_ad002_desc =3D { }, .lanes =3D 4, .format =3D MIPI_DSI_FMT_RGB888, - .init_cmds =3D radxa_display_8hd_ad002_init_cmds, - .num_init_cmds =3D ARRAY_SIZE(radxa_display_8hd_ad002_init_cmds), + .init =3D radxa_display_8hd_ad002_init_cmds, }; =20 -static const struct jadard_init_cmd cz101b4001_init_cmds[] =3D { - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE1, 0x93 } }, - { .data =3D { 0xE2, 0x65 } }, - { .data =3D { 0xE3, 0xF8 } }, - { .data =3D { 0x80, 0x03 } }, - { .data =3D { 0xE0, 0x01 } }, - { .data =3D { 0x00, 0x00 } }, - { .data =3D { 0x01, 0x3B } }, - { .data =3D { 0x0C, 0x74 } }, - { .data =3D { 0x17, 0x00 } }, - { .data =3D { 0x18, 0xAF } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x00 } }, - { .data =3D { 0x1B, 0xAF } }, - { .data =3D { 0x1C, 0x00 } }, - { .data =3D { 0x35, 0x26 } }, - { .data =3D { 0x37, 0x09 } }, - { .data =3D { 0x38, 0x04 } }, - { .data =3D { 0x39, 0x00 } }, - { .data =3D { 0x3A, 0x01 } }, - { .data =3D { 0x3C, 0x78 } }, - { .data =3D { 0x3D, 0xFF } }, - { .data =3D { 0x3E, 0xFF } }, - { .data =3D { 0x3F, 0x7F } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0xA0 } }, - { .data =3D { 0x42, 0x81 } }, - { .data =3D { 0x43, 0x14 } }, - { .data =3D { 0x44, 0x23 } }, - { .data =3D { 0x45, 0x28 } }, - { .data =3D { 0x55, 0x02 } }, - { .data =3D { 0x57, 0x69 } }, - { .data =3D { 0x59, 0x0A } }, - { .data =3D { 0x5A, 0x2A } }, - { .data =3D { 0x5B, 0x17 } }, - { .data =3D { 0x5D, 0x7F } }, - { .data =3D { 0x5E, 0x6B } }, - { .data =3D { 0x5F, 0x5C } }, - { .data =3D { 0x60, 0x4F } }, - { .data =3D { 0x61, 0x4D } }, - { .data =3D { 0x62, 0x3F } }, - { .data =3D { 0x63, 0x42 } }, - { .data =3D { 0x64, 0x2B } }, - { .data =3D { 0x65, 0x44 } }, - { .data =3D { 0x66, 0x43 } }, - { .data =3D { 0x67, 0x43 } }, - { .data =3D { 0x68, 0x63 } }, - { .data =3D { 0x69, 0x52 } }, - { .data =3D { 0x6A, 0x5A } }, - { .data =3D { 0x6B, 0x4F } }, - { .data =3D { 0x6C, 0x4E } }, - { .data =3D { 0x6D, 0x20 } }, - { .data =3D { 0x6E, 0x0F } }, - { .data =3D { 0x6F, 0x00 } }, - { .data =3D { 0x70, 0x7F } }, - { .data =3D { 0x71, 0x6B } }, - { .data =3D { 0x72, 0x5C } }, - { .data =3D { 0x73, 0x4F } }, - { .data =3D { 0x74, 0x4D } }, - { .data =3D { 0x75, 0x3F } }, - { .data =3D { 0x76, 0x42 } }, - { .data =3D { 0x77, 0x2B } }, - { .data =3D { 0x78, 0x44 } }, - { .data =3D { 0x79, 0x43 } }, - { .data =3D { 0x7A, 0x43 } }, - { .data =3D { 0x7B, 0x63 } }, - { .data =3D { 0x7C, 0x52 } }, - { .data =3D { 0x7D, 0x5A } }, - { .data =3D { 0x7E, 0x4F } }, - { .data =3D { 0x7F, 0x4E } }, - { .data =3D { 0x80, 0x20 } }, - { .data =3D { 0x81, 0x0F } }, - { .data =3D { 0x82, 0x00 } }, - { .data =3D { 0xE0, 0x02 } }, - { .data =3D { 0x00, 0x02 } }, - { .data =3D { 0x01, 0x02 } }, - { .data =3D { 0x02, 0x00 } }, - { .data =3D { 0x03, 0x00 } }, - { .data =3D { 0x04, 0x1E } }, - { .data =3D { 0x05, 0x1E } }, - { .data =3D { 0x06, 0x1F } }, - { .data =3D { 0x07, 0x1F } }, - { .data =3D { 0x08, 0x1F } }, - { .data =3D { 0x09, 0x17 } }, - { .data =3D { 0x0A, 0x17 } }, - { .data =3D { 0x0B, 0x37 } }, - { .data =3D { 0x0C, 0x37 } }, - { .data =3D { 0x0D, 0x47 } }, - { .data =3D { 0x0E, 0x47 } }, - { .data =3D { 0x0F, 0x45 } }, - { .data =3D { 0x10, 0x45 } }, - { .data =3D { 0x11, 0x4B } }, - { .data =3D { 0x12, 0x4B } }, - { .data =3D { 0x13, 0x49 } }, - { .data =3D { 0x14, 0x49 } }, - { .data =3D { 0x15, 0x1F } }, - { .data =3D { 0x16, 0x01 } }, - { .data =3D { 0x17, 0x01 } }, - { .data =3D { 0x18, 0x00 } }, - { .data =3D { 0x19, 0x00 } }, - { .data =3D { 0x1A, 0x1E } }, - { .data =3D { 0x1B, 0x1E } }, - { .data =3D { 0x1C, 0x1F } }, - { .data =3D { 0x1D, 0x1F } }, - { .data =3D { 0x1E, 0x1F } }, - { .data =3D { 0x1F, 0x17 } }, - { .data =3D { 0x20, 0x17 } }, - { .data =3D { 0x21, 0x37 } }, - { .data =3D { 0x22, 0x37 } }, - { .data =3D { 0x23, 0x46 } }, - { .data =3D { 0x24, 0x46 } }, - { .data =3D { 0x25, 0x44 } }, - { .data =3D { 0x26, 0x44 } }, - { .data =3D { 0x27, 0x4A } }, - { .data =3D { 0x28, 0x4A } }, - { .data =3D { 0x29, 0x48 } }, - { .data =3D { 0x2A, 0x48 } }, - { .data =3D { 0x2B, 0x1F } }, - { .data =3D { 0x2C, 0x01 } }, - { .data =3D { 0x2D, 0x01 } }, - { .data =3D { 0x2E, 0x00 } }, - { .data =3D { 0x2F, 0x00 } }, - { .data =3D { 0x30, 0x1F } }, - { .data =3D { 0x31, 0x1F } }, - { .data =3D { 0x32, 0x1E } }, - { .data =3D { 0x33, 0x1E } }, - { .data =3D { 0x34, 0x1F } }, - { .data =3D { 0x35, 0x17 } }, - { .data =3D { 0x36, 0x17 } }, - { .data =3D { 0x37, 0x37 } }, - { .data =3D { 0x38, 0x37 } }, - { .data =3D { 0x39, 0x08 } }, - { .data =3D { 0x3A, 0x08 } }, - { .data =3D { 0x3B, 0x0A } }, - { .data =3D { 0x3C, 0x0A } }, - { .data =3D { 0x3D, 0x04 } }, - { .data =3D { 0x3E, 0x04 } }, - { .data =3D { 0x3F, 0x06 } }, - { .data =3D { 0x40, 0x06 } }, - { .data =3D { 0x41, 0x1F } }, - { .data =3D { 0x42, 0x02 } }, - { .data =3D { 0x43, 0x02 } }, - { .data =3D { 0x44, 0x00 } }, - { .data =3D { 0x45, 0x00 } }, - { .data =3D { 0x46, 0x1F } }, - { .data =3D { 0x47, 0x1F } }, - { .data =3D { 0x48, 0x1E } }, - { .data =3D { 0x49, 0x1E } }, - { .data =3D { 0x4A, 0x1F } }, - { .data =3D { 0x4B, 0x17 } }, - { .data =3D { 0x4C, 0x17 } }, - { .data =3D { 0x4D, 0x37 } }, - { .data =3D { 0x4E, 0x37 } }, - { .data =3D { 0x4F, 0x09 } }, - { .data =3D { 0x50, 0x09 } }, - { .data =3D { 0x51, 0x0B } }, - { .data =3D { 0x52, 0x0B } }, - { .data =3D { 0x53, 0x05 } }, - { .data =3D { 0x54, 0x05 } }, - { .data =3D { 0x55, 0x07 } }, - { .data =3D { 0x56, 0x07 } }, - { .data =3D { 0x57, 0x1F } }, - { .data =3D { 0x58, 0x40 } }, - { .data =3D { 0x5B, 0x30 } }, - { .data =3D { 0x5C, 0x16 } }, - { .data =3D { 0x5D, 0x34 } }, - { .data =3D { 0x5E, 0x05 } }, - { .data =3D { 0x5F, 0x02 } }, - { .data =3D { 0x63, 0x00 } }, - { .data =3D { 0x64, 0x6A } }, - { .data =3D { 0x67, 0x73 } }, - { .data =3D { 0x68, 0x1D } }, - { .data =3D { 0x69, 0x08 } }, - { .data =3D { 0x6A, 0x6A } }, - { .data =3D { 0x6B, 0x08 } }, - { .data =3D { 0x6C, 0x00 } }, - { .data =3D { 0x6D, 0x00 } }, - { .data =3D { 0x6E, 0x00 } }, - { .data =3D { 0x6F, 0x88 } }, - { .data =3D { 0x75, 0xFF } }, - { .data =3D { 0x77, 0xDD } }, - { .data =3D { 0x78, 0x3F } }, - { .data =3D { 0x79, 0x15 } }, - { .data =3D { 0x7A, 0x17 } }, - { .data =3D { 0x7D, 0x14 } }, - { .data =3D { 0x7E, 0x82 } }, - { .data =3D { 0xE0, 0x04 } }, - { .data =3D { 0x00, 0x0E } }, - { .data =3D { 0x02, 0xB3 } }, - { .data =3D { 0x09, 0x61 } }, - { .data =3D { 0x0E, 0x48 } }, - { .data =3D { 0xE0, 0x00 } }, - { .data =3D { 0xE6, 0x02 } }, - { .data =3D { 0xE7, 0x0C } }, +static int cz101b4001_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); + + return dsi_ctx.accum_err; }; =20 static const struct jadard_panel_desc cz101b4001_desc =3D { @@ -578,8 +566,7 @@ static const struct jadard_panel_desc cz101b4001_desc = =3D { }, .lanes =3D 4, .format =3D MIPI_DSI_FMT_RGB888, - .init_cmds =3D cz101b4001_init_cmds, - .num_init_cmds =3D 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d9443c01a7336-1fa23f227b5mr50831475ad.7.1719238868461; Mon, 24 Jun 2024 07:21:08 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb3d5fa9sm63243855ad.206.2024.06.24.07.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:21:08 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 4/5] drm/panel: jd9365da: Support for kd101ne3-40ti MIPI-DSI panel Date: Mon, 24 Jun 2024 22:19:25 +0800 Message-Id: <20240624141926.5250-5-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The K&d kd101ne3-40ti is a 10.1" WXGA TFT-LCD panel, use jd9365da controller,which fits in nicely with the existing panel-jadard-jd9365da-h3 driver.Hence,we add a new compatible with panel specific config. Although they have the same control IC, the two panels are different, and the timing will be slightly different, so we added some variables in struct jadard_panel_desc to control the timing. Signed-off-by: Zhaoxiong Lv Acked-by: Jessica Zhang Reviewed-by: Douglas Anderson --- Changes between V5 and V4: - 1. Add a "_ms" suffix to the variables. - 2. Use more "_multi" in the enable/disable function - 3. Use mipi_dsi_dcs_write_seq_multi() in the init() function. V4:https://lore.kernel.org/all/20240620080509.18504-4-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V4 and V3: - 1. Use mipi_dsi_msleep. - 2. Adjust the ".clock" assignment format. - 3. Adjust "compatible" positions to keep the list sorted. V3:https://lore.kernel.org/all/20240614145510.22965-4-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V3 and V2: - 1. Give up creating a new driver and re-add K&d kd101ne3-40ti=20 - configuration to the panel-jadard-jd9365da-h3.c driver. V2:https://lore.kernel.org/all/20240601084528.22502-3-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V2 and V1: - 1. Use the new mipi_dsi_dcs_write_seq_multi() function. - 2. Modify Move mipi_dsi_dcs_set_display_off() and mipi_dsi_dcs_enter_sle= ep_mode() to disable(), - and drop kingdisplay_panel_enter_sleep_mode(). - 3. If prepare fails, disable GPIO before regulators. - 4. This function drm_connector_set_panel_orientation() is no longer used= . Delete it. - 5. Drop ".shutdown =3D kingdisplay_panel_shutdown". --- .../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 277 ++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index e836260338bf..593e12b31ebd 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -27,6 +27,15 @@ struct jadard_panel_desc { enum mipi_dsi_pixel_format format; int (*init)(struct jadard *jadard); u32 num_init_cmds; + bool lp11_before_reset; + bool reset_before_power_off_vcioo; + unsigned int vcioo_to_lp11_delay_ms; + unsigned int lp11_to_reset_delay_ms; + unsigned int exit_sleep_to_display_on_delay_ms; + unsigned int display_on_delay_ms; + unsigned int backlight_off_to_display_off_delay_ms; + unsigned int display_off_to_enter_sleep_delay_ms; + unsigned int enter_sleep_to_reset_down_delay_ms; }; =20 struct jadard { @@ -53,8 +62,14 @@ static int jadard_enable(struct drm_panel *panel) =20 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); =20 + if (jadard->desc->exit_sleep_to_display_on_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->exit_sleep_to_display_on_delay_m= s); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); =20 + if (jadard->desc->display_on_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_on_delay_ms); + return dsi_ctx.accum_err; } =20 @@ -63,10 +78,19 @@ static int jadard_disable(struct drm_panel *panel) struct jadard *jadard =3D panel_to_jadard(panel); struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; =20 + if (jadard->desc->backlight_off_to_display_off_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->backlight_off_to_display_off_del= ay_ms); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); =20 + if (jadard->desc->display_off_to_enter_sleep_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_off_to_enter_sleep_delay= _ms); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); =20 + if (jadard->desc->enter_sleep_to_reset_down_delay_ms) + mipi_dsi_msleep(&dsi_ctx, jadard->desc->enter_sleep_to_reset_down_delay_= ms); + return dsi_ctx.accum_err; } =20 @@ -83,6 +107,18 @@ static int jadard_prepare(struct drm_panel *panel) if (ret) return ret; =20 + if (jadard->desc->vcioo_to_lp11_delay_ms) + msleep(jadard->desc->vcioo_to_lp11_delay_ms); + + if (jadard->desc->lp11_before_reset) { + ret =3D mipi_dsi_dcs_nop(jadard->dsi); + if (ret) + return ret; + } + + if (jadard->desc->lp11_to_reset_delay_ms) + msleep(jadard->desc->lp11_to_reset_delay_ms); + gpiod_set_value(jadard->reset, 1); msleep(5); =20 @@ -106,6 +142,12 @@ static int jadard_unprepare(struct drm_panel *panel) gpiod_set_value(jadard->reset, 1); msleep(120); =20 + if (jadard->desc->reset_before_power_off_vcioo) { + gpiod_set_value(jadard->reset, 0); + + usleep_range(1000, 2000); + } + regulator_disable(jadard->vdd); regulator_disable(jadard->vccio); =20 @@ -569,6 +611,237 @@ static const struct jadard_panel_desc cz101b4001_desc= =3D { .init =3D cz101b4001_init_cmds, }; =20 +static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D jadard->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + return dsi_ctx.accum_err; +}; + +static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc =3D { + .mode =3D { + .clock =3D (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000, + + .hdisplay =3D 800, + .hsync_start =3D 800 + 24, + .hsync_end =3D 800 + 24 + 24, + .htotal =3D 800 + 24 + 24 + 24, + + .vdisplay =3D 1280, + .vsync_start =3D 1280 + 30, + .vsync_end =3D 1280 + 30 + 4, + .vtotal =3D 1280 + 30 + 4 + 8, + + .width_mm =3D 135, + .height_mm =3D 216, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .init =3D kingdisplay_kd101ne3_init_cmds, + .lp11_before_reset =3D true, + .reset_before_power_off_vcioo =3D true, + .vcioo_to_lp11_delay_ms =3D 5, + .lp11_to_reset_delay_ms =3D 10, + .exit_sleep_to_display_on_delay_ms =3D 120, + .display_on_delay_ms =3D 20, + .backlight_off_to_display_off_delay_ms =3D 100, + .display_off_to_enter_sleep_delay_ms =3D 50, + .enter_sleep_to_reset_down_delay_ms =3D 100, +}; + static int jadard_dsi_probe(struct mipi_dsi_device *dsi) { struct device *dev =3D &dsi->dev; @@ -637,6 +910,10 @@ static const struct of_device_id jadard_of_match[] =3D= { .compatible =3D "chongzhou,cz101b4001", .data =3D &cz101b4001_desc }, + { + .compatible =3D "kingdisplay,kd101ne3-40ti", + .data =3D &kingdisplay_kd101ne3_40ti_desc + }, { .compatible =3D "radxa,display-10hd-ad001", .data =3D &cz101b4001_desc --=20 2.17.1 From nobody Wed Dec 17 15:57:33 2025 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8C3A17622E for ; Mon, 24 Jun 2024 14:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719238886; cv=none; b=o4PNwb5IQBNK5bR1xQRiog2zpbxYJTzo3mpfE13Q1fsVbDu4uz7lQvHECfMuWZMCENX/sQYH2frd9765qdjw0kqRoy/IAZ5Y8dD12qQhTp9m9o7LOZVYBt13xZNkY3OaRuQzDxnuGHPugNWcicGw5+tQ+qwk80LCffysddgNWcI= ARC-Message-Signature: i=1; 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Mon, 24 Jun 2024 07:21:14 -0700 (PDT) Received: from lvzhaoxiong-KLVC-WXX9.huaqin.com ([116.66.212.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb3d5fa9sm63243855ad.206.2024.06.24.07.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 07:21:13 -0700 (PDT) From: Zhaoxiong Lv To: dmitry.torokhov@gmail.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jikos@kernel.org, benjamin.tissoires@redhat.co, dianders@google.com, hsinyi@google.com, jagan@edgeble.ai, neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, dmitry.baryshkov@linaro.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zhaoxiong Lv Subject: [PATCH v5 5/5] drm/panel: jd9365da: Add the function of adjusting orientation Date: Mon, 24 Jun 2024 22:19:26 +0800 Message-Id: <20240624141926.5250-6-lvzhaoxiong@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> References: <20240624141926.5250-1-lvzhaoxiong@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This driver does not have the function to adjust the orientation, so this function is added. Signed-off-by: Zhaoxiong Lv Reviewed-by: Douglas Anderson Reviewed-by: Jessica Zhang --- Changes between V5 and V4: - 1. Change dev_err() to dev_err_probe(). V4:https://lore.kernel.org/all/20240620080509.18504-5-lvzhaoxiong@huaqin.co= rp-partner.google.com/ Changes between V4 and V3: - No changes. --- drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu= /drm/panel/panel-jadard-jd9365da-h3.c index 593e12b31ebd..c6b669866fed 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -42,7 +42,7 @@ struct jadard { struct drm_panel panel; struct mipi_dsi_device *dsi; const struct jadard_panel_desc *desc; - + enum drm_panel_orientation orientation; struct regulator *vdd; struct regulator *vccio; struct gpio_desc *reset; @@ -178,12 +178,20 @@ static int jadard_get_modes(struct drm_panel *panel, return 1; } =20 +static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_= panel *panel) +{ + struct jadard *jadard =3D panel_to_jadard(panel); + + return jadard->orientation; +} + static const struct drm_panel_funcs jadard_funcs =3D { .disable =3D jadard_disable, .unprepare =3D jadard_unprepare, .prepare =3D jadard_prepare, .enable =3D jadard_enable, .get_modes =3D jadard_get_modes, + .get_orientation =3D jadard_panel_get_orientation, }; =20 static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) @@ -880,6 +888,10 @@ static int jadard_dsi_probe(struct mipi_dsi_device *ds= i) drm_panel_init(&jadard->panel, dev, &jadard_funcs, DRM_MODE_CONNECTOR_DSI); =20 + ret =3D of_drm_get_panel_orientation(dev->of_node, &jadard->orientation); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get orientation\n"); + ret =3D drm_panel_of_backlight(&jadard->panel); if (ret) return ret; --=20 2.17.1